KR100569708B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

Disclosed are a semiconductor device having a recessed channel and a method of manufacturing the same. A semiconductor substrate having active and field regions is provided. A semiconductor layer is formed on the active region and has a gate trench in a gate formation portion. A gate structure partially protruding above the semiconductor layer while filling the gate trench is provided. Impurity regions formed under the surface of the semiconductor layer on both sides of the gate structure are provided. A semiconductor device provided with a conductive pattern connected to the impurity regions and covering at least the entire impurity region is provided. Since the semiconductor device includes the conductive pattern, the alignment margin is increased during subsequent contact formation, thereby further reducing the area of the active region formed on the substrate.

Description

Semiconductor device and method of manufacturing the same

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

2 is a layout diagram of a semiconductor device according to a first embodiment of the present invention.

3A to 3N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4 is a layout diagram of a semiconductor device according to a second embodiment of the present invention.

5 is a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view of a semiconductor device according to a third exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate 102: field area

103: active region 105a: buffer oxide film pattern

107a: dummy gate pattern 108: dummy gate structure

110: semiconductor layer 112a: low concentration impurity region

120: gate trench 122: gate insulating film pattern

126: gate electrode pattern 128: spacer

130: high concentration impurity region 132: capping pattern

134: conductive pattern 136: metal silicide pattern

138: interlayer insulating film 140: contact

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor semiconductor device having a recess channel and a method of manufacturing the same.

As semiconductor devices become more integrated, the gate length of MOS transistors is greatly reduced. As the gate length decreases, the channel length of the MOS transistor also decreases. As the channel length of the MOS transistor decreases, the channel driving ability by the gate electrode decreases, and the influence of the electric field generated by the source / drain on the channel region becomes remarkable. This phenomenon is referred to as a short channel effect. It is called. That is, as the gate length decreases, the off current increases, and power consumption of the transistor increases.

In addition, in order to increase the degree of integration of the semiconductor device, the horizontal area of the active and field is further reduced. However, when the active area is reduced, the misalignment margin between the active area and each pattern (eg, gate and contact) is narrowed. If misalignment occurs between the patterns, the semiconductor device may not have desired characteristics or may cause a problem in the reliability of the semiconductor device. In addition, when the field area is reduced, a defect such as latch-up may occur because electrical isolation between the elements is not normally performed.

In order to solve the above problems, methods for improving the characteristics of the MOS transistor while reducing the gate length formed on the substrate have been researched and developed.

US patent 6391720 discloses a method for fabricating a self-aligned recess channel MOS transistor to reduce short channel effects and hot carrier effects. According to the disclosed method, the substrate is partially etched to form a gate recess, and then a gate electrode is formed in the gate recess. According to the method, the gate electrode characteristics vary according to the thickness and line width of the gate recess. Therefore, when the silicon substrate is not etched uniformly, it is difficult to form a gate having desired characteristics. In addition, the misalignment margin problem between the active region and the patterns still remains.

Accordingly, a first object of the present invention is to provide a semiconductor device in which the effective length of the channel is increased and the overlap margin with the active is increased.

A second object of the present invention is to provide a method for manufacturing a semiconductor device suitable for manufacturing the semiconductor device.

In order to achieve the first object described above, the present invention,

A semiconductor substrate is divided into active and field regions. A semiconductor layer is formed on the active region and has a gate trench in a gate formation portion. The gate structure may partially fill the gate trench and protrude upwardly from the semiconductor layer. Impurity regions formed under the surface of the semiconductor layer. A semiconductor device including a conductive pattern in contact with the impurity regions and covering at least the entire impurity region is provided.

In order to achieve the above second object, the present invention,

An active region and a field region are divided on a semiconductor substrate. A semiconductor layer having a gate trench for selectively exposing a gate formation region is formed on the active region. While filling the gate trench, a gate structure protruding above the semiconductor layer is formed. An impurity region is formed under the surface of the semiconductor layer. Subsequently, a semiconductor device is manufactured by contacting the impurity regions and forming a conductive pattern covering at least the entire impurity region.

According to the method, the effective channel length of the MOS transistor is increased because the channel is also formed at the bottom and side portions of the gate. Therefore, the length of the gate can be further reduced.

In addition, the conductive pattern connected to the impurity regions on both sides of the gate may be larger than the impurity region to increase the alignment margin at the time of subsequent contact formation. Therefore, the area of the active region formed on the substrate can be further reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 2 is a layout diagram of a semiconductor device according to a first embodiment of the present invention.

1 and 2, a semiconductor substrate 100 including silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or silicon germanium-on-insulator (SGOI) is provided. The semiconductor substrate 100 may also be a strained silicon substrate having a strained epitaxial layer formed thereon. In the present embodiment, only the MOS transistor formed on the substrate 100 made of bulk silicon will be described.

The active region 103 and the field region 102 are separated from the semiconductor substrate 100. An impurity is implanted into the active region 103 to form a well region or a channel region.

On the active region 103, a semiconductor layer having a gate trench is provided at a portion where a gate is to be formed. The semiconductor layer may be made of silicon formed by epitaxial growth. Alternatively, the semiconductor layer may be made of SiGe or GaAs.

A gate structure partially protruding above the semiconductor layer while filling the gate trench is provided. The gate structure includes a gate insulating layer pattern 122a and a gate electrode pattern 126. The gate insulating layer pattern 122a is formed at an interface between the semiconductor layer and the gate electrode pattern 126.

The gate electrode pattern 126 may be made of polysilicon or may be made of a composite layer including doped silicon and germanium. In addition, the gate electrode may have a polysilicon structure in which a metal silicide pattern is formed on the polysilicon pattern and the polysilicon pattern. The gate insulating layer pattern 122a may be formed of a silicon oxide film, a metal oxide film having a high dielectric constant, or a SiON series film. Examples of the metal oxide film having the high dielectric constant include a Ta ₂ O ₅ film, a TiO ₂ film, an Al ₂ O ₃ film, a Y ₂ O ₃ film, a ZrO ₂ film, an HfO ₂ film, a BaTiO ₃ film, a SrTiO ₃ film, or a composite thereof. And the like.

Spacers 128 are provided on both sidewalls of the protrusion of the gate electrode pattern 126. The spacer 128 may be made of silicon nitride or silicon oxide, or may be made of a composite layer made of a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

A capping pattern 132 is provided on the protruding upper surface of the gate electrode pattern 126 and the surface of the spacer 128. The capping pattern 132 may be formed of silicon nitride or silicon oxide.

The semiconductor layers on both sides of the gate electrode pattern 126 are provided with a low concentration impurity region 112a and a high concentration impurity region 130 provided as a source and a drain. The source and drain have an LDD structure.

And a conductive pattern 134 that contacts the high concentration impurity regions 130 and covers at least the entire exposed impurity region. The conductive pattern 134 is formed of doped polysilicon or doped epitaxial silicon.

A metal silicide pattern 136 is further formed on the surface of the conductive pattern 134. The conductive pattern 134 increases the contact alignment margin when forming a contact electrically connected to the impurity regions 112a and 130. Therefore, the horizontal area of the active region 103 formed on the substrate can be reduced.

In another embodiment, although not illustrated, the conductive pattern 134 may be entirely formed of metal silicide.

An interlayer insulating layer 138 is provided on the conductive pattern 134, and the interlayer insulating layer 138 is provided with a contact 140 that connects to the conductive pattern 134.

In the MOS transistor of the present invention, source and drain regions are formed on both sides of the gate electrode, and the gate insulating film extends to the bottom and side surfaces of the gate electrode. Therefore, the channel region of the transistor extends to the bottom side as well as the bottom surface of the gate electrode. In other words, the MOS transistor has a longer transistor channel length than that of the gate electrode, thereby increasing the integration of the semiconductor device. In addition, the channel length of the MOS transistor is increased to minimize the problems caused by the short channel effect.

In addition, by forming a conductive pattern to be connected to the impurity region, the alignment margin at the time of forming a contact to be connected to the impurity region is increased. Therefore, the area of the active region formed on the substrate can be further reduced.

3A to 3N are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a first embodiment of the present invention.

Referring to FIG. 3A, a trench isolation process may be performed on the semiconductor substrate 100 to separate the active region 103 and the field region 102.

Next, impurity ions are implanted into the active region 103 to form a well region and a channel region of the MOS transistor. Group 3 or 5 impurity ions are implanted according to the type of the MOS transistor.

Referring to FIG. 3B, a buffer oxide film 105 is formed on the active region 103 of the semiconductor substrate 100. The buffer oxide film 105 is formed to a thickness of about 100 to about 200 kPa by thermal oxidation or CVD. The buffer oxide layer 105 prevents the surface of the active region 103 from being damaged during the subsequent process.

Next, a dummy gate nitride film 107 is deposited on the buffer oxide film 105. The dummy gate nitride film 107 is deposited to a thickness thicker than the height of the gate electrode pattern to be formed in consideration of the thickness polished in a later CMP process. Considering that the height of the gate electrode pattern to be formed in this embodiment is 1500 kW, the nitride film 107 for the dummy gate is deposited to a thickness of about 2000 kW.

Referring to FIG. 3C, the buffer oxide layer pattern 105a and the dummy gate pattern 107a are stacked by sequentially dry etching a predetermined portion of the dummy gate nitride layer 107 and the buffer oxide layer 105 by a photolithography process. To form the dummy gate structure 108 of the present invention. The dummy gate structure 108 is formed to define a gate electrode formation region. Accordingly, the line width of the dummy gate structure 108 may have a line width similar to the line width of the gate electrode pattern to be formed.

Referring to FIG. 3D, the epitaxial mask is selectively formed by using the dummy gate structure 108 formed in the active region 103 as an epitaxial mask and seeding the silicon exposed on the surface. Growing to form a semiconductor layer (110).

The semiconductor layer 110 is a layer for forming a recess channel in a MOS transistor. The semiconductor layer 110 may be formed to a thickness lower than the thickness of the dummy gate structure 108. Specifically, the semiconductor layer 110 is formed to a thickness of about 100 to 1000Å. Thus, as shown, the dummy gate structure 108 may protrude from the semiconductor layer 110.

A channel of the MOS transistor is formed along the semiconductor layer 110 formed on the side of the dummy gate structure 108. Therefore, the channel length of the MOS transistor may be adjusted by variously changing the thickness of the semiconductor layer 110 according to the designed operating characteristics of the MOS transistor.

Referring to FIG. 3E, an impurity ion implantation process is performed to form a low concentration impurity region under the surface of the semiconductor layer 100 using the dummy gate structure 108 as an ion implantation mask. Impurities that can be injected include Group 3 or Group 5 impurities such as B, As, or P depending on the type of the MOS transistor.

The impurity ion implantation process forms a low concentration impurity region 112 by a predetermined thickness below the surface of the semiconductor layer 110 on both sides of the dummy gate structure 108. The low concentration impurity region 112 is formed to have a depth of about 200 to about 500 kHz from the surface of the semiconductor layer 100. Preferably, the depth of the low concentration impurity region 112 is formed to be smaller than the thickness of the semiconductor layer 100. As a result, the transistor of the recess structure formed by a subsequent process has a channel length of about twice the difference between the thickness of the semiconductor layer 110 and the depth of the low concentration impurity region 112 compared to the conventional planar transistor. Is extended.

Although not shown, after the low concentration impurity region 112 is formed, a halo process of doping impurities of a type opposite to that of the low concentration impurity region 112 may be further performed. have. The threshold voltage of the transistor can be controlled by performing the halo process.

Referring to FIG. 3F, the dummy gate structure 108 is removed to form the gate trench 120 in the semiconductor layer 110. Specifically, the dummy gate pattern 107a included in the dummy gate structure 108 is wet etched using an etchant containing phosphoric acid. Subsequently, the buffer oxide layer pattern 105a provided under the dummy gate pattern 107a is removed by wet etching or dry etching.

Referring to FIG. 3G, the gate insulating layer 122 is formed on the surface of the gate trench 120 to have a thin thickness of 30 to 200 μm. In this case, the gate insulating layer 122 is formed by heat-treating a substrate including the gate trench 120 in an oxygen atmosphere to react silicon exposed to a surface with oxygen. In detail, the gate insulating layer 122 is formed on an inner surface of the gate trench 120, an active region of the substrate exposed by the gate trench 120, and an upper surface of the semiconductor layer 110.

Subsequently, the gate forming conductive layer 124 is formed thick so as to completely fill the gate trench 120 in which the gate insulating layer 122 is formed. The gate forming conductive layer 124 may be formed of a layer or a metal layer in which a polysilicon layer, a polysilicon layer, and a metal silicide are stacked. In the present embodiment, the gate forming conductive layer 124 is formed of a doped polysilicon layer.

Referring to FIG. 3H, the gate forming conductive layer 124 is patterned to form a gate electrode pattern 126. The gate electrode pattern 126 has a shape protruding from the semiconductor layer 110 while filling the inside of the gate trench 120 formed in the semiconductor layer 110.

Referring to FIG. 3I, a silicon nitride film is formed on the gate electrode pattern 126 and the semiconductor layer 110 to a thickness of about 100 to 700 GPa. Subsequently, the silicon nitride layer is anisotropically etched to form spacers 128 on sidewalls of the protrusions of the gate electrode pattern 126.

The spacer 128 defines a low concentration impurity doping region (hereinafter referred to as LDD region) of the source and the drain of the LDD structure of the MOS transistor through a subsequent process. That is, the thickness in the horizontal direction of the bottom portion of the spacer 128 determines the width of the LDD region.

In the present embodiment, the spacer 128 made of a silicon nitride film is illustrated, but instead of the silicon nitride film, the spacer 128 is stacked in the form of a composite layer of a silicon oxide film and a silicon nitride film. The parasitic capacitance generated between the contact and the gate electrode connected to the drain or the source can be reduced.

Referring to FIG. 3J, a high concentration of impurity ions are implanted under the surface of the semiconductor layer 110 by using the gate electrode pattern 126 including the spacer 128 as an ion implantation mask, and thus high concentration in the semiconductor layer 110. Impurity regions (hereinafter referred to as HDD regions) 130 are formed.

Subsequently, after implanting the impurity ions, the substrate is heat-treated to activate the impurity ions.

The impurity is injected below the surface of the semiconductor layer 110 at the portion exposed by the spacer 128, and is not injected into the lower portion of the bottom surface of the semiconductor layer 110 covered by the spacer 128. Therefore, the low concentration impurity region 112a (hereinafter, referred to as LDD region) is limited to a region corresponding to the bottom surface of the spacer 128. The LDD region 112a is determined by the horizontal thickness of the bottom surface of the spacer 128.

Referring to FIG. 3K, an insulating capping layer is formed on surfaces of the semiconductor layer, the spacer, and the gate electrode. The capping insulating layer may be formed of silicon nitride or silicon oxide.

Subsequently, the capping insulating layer is patterned to expose the high concentration impurity region 130 while covering at least an upper surface of the gate electrode pattern 126 to form a capping pattern 132. Preferably, the capping pattern 132 is formed by patterning the insulating film for capping to remain only on the upper surface of the spacer and the gate electrode. If the patterning is performed so as to cover only the upper surface of the gate electrode pattern 126, the pattern size is very small and the patterning process is not easy.

When the capping pattern 132 is formed, the gate insulating layer 122 formed on the exposed semiconductor layer 110 is removed to form the gate insulating layer pattern 122a.

Referring to FIG. 3L, a preliminary conductive layer is formed on the surfaces of the semiconductor layer 110 and the capping pattern 132. The preliminary conductive layer may be formed of silicon formed by polysilicon or epitaxial growth.

Subsequently, the preliminary conductive layer is patterned to contact the impurity region formed on the first side of the gate electrode pattern 126 and the impurity region formed on the second side opposite to the first side. 2 preliminary conductive patterns are formed, respectively. The first and second preliminary conductive patterns may have an extended shape near the field region. In this case, the first and second conductive patterns may not be in contact with each other.

When the preliminary conductive layer is formed of epitaxial silicon, silicon is selectively grown only on the exposed semiconductor layer, that is, on the surface of the exposed impurity region, so that a separate patterning process may not be performed. In this case, however, the process conditions must be adjusted so that the preliminary conductive patterns do not contact each other in the field region due to over-silicon growth.

Subsequently, impurity ions are implanted into the first and second preliminary conductive patterns to form conductive patterns 134.

Since the conductive pattern 134 is formed on the capping pattern 132, the conductive pattern 134 and the gate electrode pattern 126 are not shorted to each other.

Referring to FIG. 3M, metal silicide patterns 136 are formed on the conductive patterns 134. The metal silicide pattern 136 includes a cobalt silicide, a tungsten silicide, or a titanium silicide pattern. When forming the metal silicide pattern, contact resistance with an impurity region provided as a source / drain may be reduced.

Although not shown, the entire conductive pattern may be formed as a metal silicide pattern during the metal silicide forming process. In this case, the conductive pattern itself is converted into the metal silicide pattern, not the structure in which the metal silicide pattern is formed on the conductive pattern.

Alternatively, the metal silicide pattern 136 forming process may be omitted for the convenience of the process.

Referring to FIG. 3N, subsequent processes such as an interlayer insulating layer 138 forming process and a contact 140 forming process for connecting the conductive pattern 134 may be performed to complete a semiconductor device.

According to the present embodiment, in the MOS transistor, the channel region extends not only on the bottom of the gate electrode but also on both sides of the bottom of the gate electrode. That is, the channel length of the MOS transistor is formed longer than the width of the gate. Therefore, it is possible to minimize the occurrence of defects due to the short channel effect while reducing the threshold of the gate electrode. In addition, since the semiconductor substrate is not dry etched to define the gate electrode formation region in the MOS transistor, substrate damage caused by the dry etching may be minimized. In addition, since the margin at the time of contact formation for connecting to the source / drain is increased, the horizontal area of the active region formed on the substrate can be further reduced.

Example 2

4 is a layout diagram of a semiconductor device according to a second embodiment of the present invention. 5 is a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention.

As shown in FIGS. 4 and 5, the semiconductor device according to the present embodiment is implemented except that the conductive pattern 150 is configured to electrically connect independent active regions formed on both sides of the gate electrode pattern 126 to each other. Same as the structure of Example 1.

Embodiment 2 can be applied to a semiconductor device having a structure in which respective independent active regions are connected to each other. According to the apparatus of Embodiment 2, the conductive pattern may have a form extended in the horizontal direction compared to the active region 103 defined on the substrate. Therefore, the area of the active region 103 formed on the substrate can be further reduced, whereby the semiconductor device can be further integrated.

A manufacturing method of the semiconductor device according to the second embodiment will be briefly described.

First, the same process as described with reference to FIGS. 3A to 3K is performed.

Subsequently, a preliminary conductive layer is formed on the surfaces of the semiconductor layer 110 and the capping pattern 134. The preliminary conductive layer may be formed of silicon formed by polysilicon or epitaxial growth.

Subsequently, the preliminary conductive pattern for patterning the preliminary conductive layer to contact the high concentration impurity regions 130 formed on both sides of the gate electrode pattern 126 to electrically conduct the exposed high concentration impurity regions 130 to each other. Each pattern is formed. In this case, the preliminary conductive pattern is formed to be electrically insulated from the impurity regions of neighboring transistors.

In the case of the second embodiment, it is more preferable to form the preliminary conductive film with polysilicon. When the preliminary conductive layer is formed of epitaxial silicon, silicon is grown from the impurity regions on both sides of the gate structure onto the gate electrode pattern 126 on which the capping pattern 132 is formed. The silicon films must be connected to each other on the gate electrode. However, due to the slow silicon growth rate, it is difficult to progress the process.

Subsequently, impurity ions are implanted into the preliminary conductive pattern to form a conductive pattern 150.

Subsequently, metal silicide patterns 152 are selectively formed on the conductive patterns 150.

When the process is performed as described above, a contact forming process for connecting the active regions on the substrate to each other can be omitted, and the process is very simple. In addition, the area of the active region formed on the substrate can be further reduced, whereby the semiconductor device can be further integrated.

Example 3

6 is a cross-sectional view of a semiconductor device according to a third exemplary embodiment of the present invention.

As shown in FIG. 6, the semiconductor device according to the present exemplary embodiment is the same as the first exemplary embodiment except that the metal silicide pattern is selectively formed on the high concentration impurity region and the gate electrode upper surface. The source / drain resistance may be reduced by forming a metal silicide pattern on the surface of the high concentration impurity region.

A manufacturing method of the semiconductor device according to the third embodiment will be briefly described.

First, the same process as described with reference to FIGS. 3A to 3J is performed.

Subsequently, metal silicide patterns 160 are selectively formed on the exposed semiconductor layer 110 and the gate electrode pattern 126, respectively. The metal silicide pattern 160 may include a cobalt silicide pattern, a tungsten silicide pattern, or a titanium silicide pattern.

Thereafter, the processes of 3k to 3n are performed in the same manner to complete the semiconductor device.

As described above, according to the present invention, a channel of the MOS transistor is formed along the semiconductor layer under the side and bottom of the gate electrode. Thus, a recess channel longer than the length of the gate electrode can be formed to minimize the short channel effect. In addition, the margin at the time of source / drain contact formation can be sufficiently secured, thereby further reducing the horizontal area of the active region.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (15)

A semiconductor substrate divided into active and field regions; A semiconductor layer formed on the active region and having a gate trench positioned at a portion where a gate is to be formed and exposing the substrate on a bottom surface thereof; A gate structure partially protruding above the semiconductor layer while filling the gate trench; Spacers disposed on sidewalls of the gate structure protruding from the gate structure; An insulating pattern for capping formed on an upper surface of the gate structure and a surface of the spacer; Impurity regions formed under a surface of the semiconductor layer on both sides of the gate structure; And And a conductive pattern connected to the impurity regions and covering at least the entire impurity region. delete The semiconductor device of claim 1, wherein the conductive pattern comprises a first pattern connected to an impurity region formed on a first side of the gate structure and a second pattern connected to an impurity region formed on a second side opposite to the first side. The semiconductor device characterized by consisting of. The semiconductor device of claim 1, wherein the conductive pattern electrically connects independent active regions formed on the substrate. The semiconductor device of claim 1, wherein the conductive pattern is made of polysilicon or doped epitaxial silicon. The semiconductor device of claim 5, further comprising a metal silicide pattern on an upper surface of the conductive pattern. The semiconductor device of claim 1, further comprising a metal silicide pattern on an upper surface of the impurity region and the gate structure. Separating an active region and a field region on a semiconductor substrate; Forming a semiconductor layer on the active region, the semiconductor layer having a gate trench for selectively exposing a substrate portion for forming a gate; Filling the gate trench, forming a gate structure protruding above the semiconductor layer; Forming spacers on sidewalls of the gate structure protruding from the gate structure; Forming an insulating pattern for capping formed on an upper surface of the gate structure and a surface of the spacer; Forming an impurity region under a surface of the semiconductor layer; And Forming a conductive pattern in contact with the impurity regions and covering at least the entire impurity region. The semiconductor layer of claim 8, wherein the semiconductor layer having the gate trench comprises: Forming a dummy gate pattern on a portion where a gate is to be formed in the active region; Using the dummy gate pattern as an epitaxial mask to form a silicon film on the active region by an epitaxial method; And And removing the dummy gate pattern. delete delete The method of claim 8, wherein a metal silicide pattern is further formed on the impurity region and the upper surface of the gate electrode prior to forming the capping insulating pattern. The method of claim 8, wherein the conductive pattern, Forming a preliminary conductive film of polysilicon or epitaxial silicon on the substrate surface; Patterning the preliminary conductive layer to form a first preliminary conductive pattern contacting the impurity region formed on the first side of the gate structure and a second preliminary conductive pattern contacting the impurity region formed on the second side opposite to the first side, respectively. Forming; And And forming a conductive pattern by implanting impurity ions into the first and second preliminary conductive patterns. The method of claim 8, wherein the conductive pattern, Forming a preliminary conductive layer of polysilicon or epitaxial silicon on the substrate surface; Patterning the preliminary conductive layer to form a preliminary conductive pattern connecting the independent active regions on the substrate to each other; And And implanting impurity ions into the preliminary conductive pattern to form a conductive pattern. The method of manufacturing a semiconductor device according to claim 8, further comprising forming a metal silicide pattern on the conductive pattern surface.

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