JP2001015751A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor which is applicable to a circuit requiring symmetry and can materialize high drain breakdown strength, a satisfactory S factor, and high drive capacity at the same time. SOLUTION: This field effect transistor has an insulator region 102, which extends to the position under a drain region 104, passing under a channel region 109 from the position under a source region 103. This has semiconductor regions 110a and 110b, and 111a and 111b which have the same conductive type as the conductive type of the channel region 109, respectively, between the source region 103 and a drain region 140 and the insulator region 102. Then, the channel region 109 and the semiconductor substrate 101 ranges via the semiconductor regions 110a, 110b and 111a, 111b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same. More specifically, the present invention relates to a field effect transistor suitable for forming a basic unit of an integrated circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art LS
MOSFE that constitutes the basic unit of I (Large Scale Integrated Circuit)
In a T (field effect transistor), as the gate length becomes shorter with miniaturization, the S factor (formula (4) described later)
However, as a countermeasure, an SOI (silicon-on-insulator) MOSFET as shown in FIG. 22 has been proposed. This SOI MOSFET includes an active layer 812 (thickness t) made of single-crystal silicon having a low impurity concentration on a silicon substrate 801 via a buried insulator layer 802, and a gate 814 formed on the active layer 812. (Gate insulating film 8
15 and a gate electrode 816), and the gate 8
14, source regions 803 formed in the active layer on both sides,
And a drain region 804. Source region 803
Is a high-concentration source region 805 and a gate 814 therefrom.
Similarly, the drain region 804 includes a high-concentration drain region 806 and a drain-side LDD extending therefrom immediately below the end of the gate 814.
D region 808. The thickness t of the active layer 812
In operation, the extension of the depletion layer into the active layer 812 due to the potential of the gate 814 is limited by the buried insulator 802, and as a result, of the gate potential, The component that extends the depletion layer into the layer 812 decreases, and the component that forms the inversion layer of the channel region 809 increases accordingly. Therefore, the sub-threshold characteristic that determines the switching characteristics of the transistor is improved, and the S factor can be improved.
At the same time, as compared with the planar MOSFET, the threshold voltage can be reduced at the same off-state current, so that high driving capability can be realized.

However, in this SOI type MOSFET, since the active layer 812 including the channel region 809 and the substrate 801 are separated by the buried insulator 802, hot carriers generated in the active layer 812 during operation are generated by the substrate 801.
Not released to Therefore, there is a problem that the drain withstand voltage is reduced due to the substrate floating effect.

On the other hand, a pseudo (Quasi) SOI type MOSFET as shown in FIG. 24D has been proposed (Nguyen et. Al, IEDM92 Tec).
h. Dig. Pp. 341). This pseudo SOI type MOS
In the FET, a buried insulator 912 is formed only below the drain-side portion (half) of the active layer 1012, and the active layer 1012 is formed on the epitaxial silicon 10
13 and the silicon substrate 1001. When fabricating this pseudo SOI MOSFET, typically, first, as shown in FIG.
An oxide film 1035 having a thickness of 0.6 μm is formed on a P-type silicon substrate 1017 by thermal oxidation.
35 to form a two-step groove 1036 reaching the substrate surface 1001a as shown (It should be noted that the upper opening dimension d ₂ is about twice that of the lower opening size d _1.). Next, FIG.
As shown in (b), the epitaxial silicon layer 101 is completely buried by a selective epitaxial growth method at a temperature of 900 ° C. and an atmospheric pressure of 15 torr using a single-wafer lamp heat ASM reactor.
Form 3 The growth rate is about 60 ° / sec. Next, as shown in FIG.
estech) Nalco (Nal), a sheet-fed polisher
(Co) 2354 is used to polish silicon, and the surface of the epitaxial silicon layer 1013 is processed flat (the surface of the epitaxial silicon layer 1013a and the surface of the oxide film 1).
035a. ). The portion of the epitaxial silicon layer 1013 that fills the upper stage of the trench 1036 becomes the active layer 1012. Thereafter, as shown in FIG. 24D, the gate 1014 including the gate insulating film 1015 and the gate electrode 1016 and the source including the high-concentration source region 1005 and the source-side LDD region 1007 are formed by using a normal MOSFET forming process. A region 1003 and a drain region 1004 including a high-concentration drain region 1006 and a drain-side LDD region 1008 are formed.

In this pseudo-SOI type MOSFET, since the active layer 1012 and the silicon substrate 1001 are conductive, the phenomenon that the drain withstand voltage is lowered due to the substrate floating effect does not occur. However, since the source side and the drain side are configured asymmetrically, there is a problem that asymmetry is exhibited also in electrical characteristics. For example, this pseudo SOI
Type MOSFET has a gate width of 20 μm, an effective channel length of 1.2 μm, a gate 1014 and a buried insulator 100.
The overlap length with No. 2 is set to 0.75 μm. When the drain voltage is set to 3 V as an operating condition, the gate overdrive value is fixed, and the gate voltage is set to 3 V higher than the threshold voltage in order to correct the difference in threshold voltage,
The difference between the drive currents when the source and the drain were exchanged was about 1 mA. When the gate voltage was set equal to the threshold voltage, the difference in withstand voltage between the source and the drain was 1.5 V or more. Therefore, this pseudo SOI type MOS
There is a problem that the application of the FET is limited to only a circuit in which such asymmetry can be ignored.

As another type of MOSFET, FIG.
As shown in JP-A-5-206455, an element having a buried insulator 1140 below the center of a channel region 1109 and having a symmetric structure has been proposed. This MOSFET is provided on a silicon substrate 1101, an insulator region 1140 having a mesa cross section, semiconductor regions 1110, 1111, 1112 surrounding the left, right, and upper sides of the insulator region 1140 in the drawing, and a semiconductor region 1112. A gate region 1114 (including a gate insulating film 1115 and a gate electrode 1116), a source region 1103 adjacent to the semiconductor region 1110, and a drain region 1104 adjacent to the semiconductor region 1111.

In this MOSFET, the channel region 11
09 including the semiconductor region 1110,1
Since it is electrically connected to the silicon substrate 1101 via 111, the substrate floating effect can be prevented. Also, the insulator region 11
40 is formed close to the center of the channel region 1109 and suppresses the extension of the depletion layer from the drain 1104, so that DIBL (drain induced barrier lowering) and punch through Can be effectively suppressed. Therefore, the drain withstand voltage can be increased. Further, since the MOSFET has a symmetric structure between the source and the drain, the MOSFET can be applied to a circuit requiring symmetry.

However, since the insulator region 1140 is provided only in the central portion, not in the entire region in the channel direction, the substrate (or well) 1101 and the source 1
When a potential difference is generated between at least one of the drain 103 and the drain 1104 and the gate 1114, the extension of the depletion layer into the active region 1112 due to the potential of the gate 1114 can be limited only to a part (the center of the channel region). . For this reason, there is a problem that a desired improvement in the S factor and the driving capability cannot be obtained.

Therefore, the object of the present invention can be applied to a circuit requiring symmetry, and a high drain breakdown voltage and a good S
It is an object of the present invention to provide a field effect transistor capable of realizing both a factor and a high driving capability at the same time.

Another object of the present invention is to provide a method for manufacturing such a field effect transistor.

[0011]

In order to achieve the above object, a field effect transistor according to the present invention comprises a source region and a drain region provided separately from each other on a semiconductor substrate or a well region; A field-effect transistor having a gate covering a channel region between the drain region and a region under the channel region from a position below the source region on the semiconductor substrate or the well region. A semiconductor region having the same conductivity type as that of the channel region between the source region, the drain region, and the insulator region; The semiconductor substrate or the well region may be continuous via the semiconductor region.

Since the field-effect transistor of the present invention has a symmetric structure between the source and the drain, it can be applied to a circuit that requires symmetry such that the source and the drain are switched and operated. During operation, the depletion layer extends into a region between the gate and the insulator region (hereinafter referred to as an “active region” including the channel region) due to the potential of the gate, so that the insulating region is insulated over the entire region in the channel direction. Since it is limited by the body region, the component of the gate potential that extends the depletion layer into the active region decreases, and the component that forms the inversion layer of the channel region increases accordingly. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristics can be improved (the threshold voltage can be kept low while suppressing the off-state current), and high driving capability can be realized. In addition, the source region,
A semiconductor region having the same conductivity type as that of the channel region is provided between the drain region and the insulator region, and the channel region and the semiconductor substrate or the well region are connected via the semiconductor region. Therefore, charge can be transferred between the active region and the semiconductor substrate or the well region. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. as a result,
Higher voltage can be applied to the source region and the drain region correspondingly, and high-speed operation can be performed.

In a thermal equilibrium state or during operation, a depletion layer extending from one of the source region and the drain region reaches the insulator region to deplete the semiconductor region, or extends from the gate side due to a gate potential. Even if the depletion layer reaches the insulator region and the active region is completely depleted, the movement of the charge itself is possible and the substrate floating effect is prevented.

A method of manufacturing a field-effect transistor according to the present invention is a method of manufacturing a field-effect transistor for manufacturing the above-mentioned field-effect transistor.
Photolithography and etching are performed on the wafer to form a plurality of grooves at predetermined intervals on the SOI wafer from the single crystal silicon layer to the base silicon substrate, and separate the insulator layer into a plurality of insulator regions. Performing the epitaxial growth, filling the trenches with epitaxial silicon, and polishing the surface side of the SOI wafer so that the surface of the single crystal silicon layer and the surface of the epitaxial silicon in the trenches are formed. Flattening so as to form the same surface, forming a gate electrode on a single crystal silicon layer present on each of the insulator layers via a gate insulating film, and using the gate electrode as a mask to form the single crystal. Impurity is ion-implanted into the surface of the silicon layer and annealing is performed. And characterized by having a step of forming a source region, a drain region extending to a position above the insulator layer.

According to the method for manufacturing a field effect transistor of the present invention, the field effect transistor can be easily manufactured. Moreover, the active region (including the channel region) is not the epitaxial silicon layer but the original SOI.
Since the wafer is a single crystal silicon layer, an active region with few defects is provided. When the active region is formed of epitaxial silicon, a problem such as a dislocation or a grain boundary in the epitaxial silicon (which occurs during epitaxial growth) may cause a problem of a reduction in current driving capability.

In one embodiment, the field-effect transistor is different from the field-effect transistor in that it is separated from an insulator region passing below the channel region and the source region,
The semiconductor device is characterized by having second and third insulator regions at positions contacting the lower part of the drain region.

In the field-effect transistor according to this embodiment, the second and third insulator regions are spaced apart from the insulator region passing below the channel region and are in contact with the lower portions of the source region and the drain region, respectively. Have
The junction capacitance of the source region and the drain region is lower than when the entire source region and the drain region are in contact with the semiconductor region. Therefore, higher-speed operation is possible.

In one embodiment of the present invention, in the method for manufacturing a field-effect transistor, the step of forming the plurality of grooves and separating the insulator layer into a plurality of insulator regions comprises the step of: The groove is formed so as to form an insulator region passing below the region and second and third insulator regions that are separated from the insulator region and are to be arranged below the source region and the drain region, respectively. Is set.

According to the method of manufacturing the field effect transistor of the embodiment, the field effect transistor of the embodiment can be easily manufactured without unnecessarily increasing the number of steps.

In one embodiment, in the field effect transistor, a depletion layer reaches the lower insulator region from the gate electrode according to the potential of the gate electrode. And

In the field effect transistor of this embodiment, the depletion layer reaches the lower insulator region from the gate electrode side according to the potential of the gate electrode, and the extension of the depletion layer is limited. Therefore, the component of the gate potential that extends the depletion layer into the active region decreases, and the component that forms the inversion layer of the channel region increases accordingly. As a result, the S factor of the transistor can be improved, the sub-threshold characteristics that determine the switching characteristics are improved, and high driving capability can be realized.

In one embodiment of the field effect transistor, the source region and the drain region are each formed of a high-concentration semiconductor having a certain junction depth provided at a side of the gate. Region and a LD having a junction depth shallower than the high-concentration region and extending from a gate-side end of the high-concentration region to a position immediately below the gate.
D region, both ends of the insulator region passing below the channel region stop at positions below the source-side LDD region and the drain-side LDD region, respectively, and the level of the upper surface of the insulator region is set to each of the high-concentration regions. Characterized by being at a level shallower than the junction depth.

In the field effect transistor of this embodiment, the level of the upper surface of the insulator region passing below the channel region is lower than the junction depth of each of the high-concentration regions forming the source region and the drain region. , The depletion layer easily reaches the lower insulator region from the gate electrode side, and the extension of the depletion layer is strongly restricted. Therefore, the component of the gate potential that extends the depletion layer into the active region further decreases, and the component that forms the inversion layer of the channel region increases accordingly. As a result, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be further improved, and high driving capability can be realized.

Further, since the insulator region exists from near the high-concentration source region to below the channel region and near the high-concentration drain region, the extension of the depletion layer from the drain region can be efficiently restricted. Therefore, DIBL (Drain Induced Barrier Lowering) and punch-through can be suppressed, and further miniaturization can be performed.

According to the method of manufacturing a field effect transistor of the present invention, a step of depositing an insulator over the entire surface of a semiconductor substrate having a groove with a concave cross section on the surface and filling the groove with the insulator is provided. Polishing the side to planarize the surface of the semiconductor substrate and the surface of the insulator in the groove so as to be flush with each other; A step of leaving an insulator having a flat surface at the bottom of the groove, and performing epitaxial growth to form a cross section with a substantially uniform thickness at least along the insulator surface and the silicon sidewall in the groove. A step of growing a single-crystal silicon layer in a concave shape, a step of depositing an insulator containing impurities with a substantially uniform thickness and a concave cross-section along at least the inner surface of the concave portion formed by the single-crystal silicon layer, Different Etching to remove the bottom of the insulator having a concave cross section and exposing the single crystal silicon layer to the gap between the sidewalls made of the remaining insulator; and performing oxidation to expose the single crystal silicon layer to the gap. Forming a gate oxide film on the surface of the formed single crystal silicon layer, and diffusing impurities in the insulator side wall into the inner surface portion of the single crystal silicon layer in contact with the insulator side wall,
A step of forming at least a part of the drain region; and a step of forming a gate electrode so as to fill a gap between the insulator side walls.

According to the method for manufacturing a field effect transistor of the present invention, a field effect transistor which can be applied to a circuit requiring symmetry and can simultaneously realize a high drain withstand voltage, a good S factor and a high driving capability can be manufactured. Is done. That is, since the field effect transistor manufactured according to the present invention has a symmetric structure between the source and the drain, the field effect transistor can be applied to a circuit that requires symmetry such that the source and the drain are switched and operated. Also, during operation,
Since the extension of the depletion layer into the active region due to the gate potential is limited by the insulator region over the entire channel direction, the component of the gate potential that extends the depletion layer into the active region is reduced, and the component is accordingly reduced. The components forming the inversion layer in the channel region increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, a portion (semiconductor region) of the single crystal silicon layer where impurities are not diffused remains between the source region and the drain region of the inner surface portion of the single crystal silicon layer and the insulator region, and a channel Since the region and the semiconductor substrate are connected to each other via the semiconductor region, charge can be transferred between the active region and the semiconductor substrate. Therefore, the substrate floating effect does not occur,
High drain withstand voltage can be realized. As a result, a higher voltage can be applied to the source region and the drain region, and high-speed operation can be performed.

According to the method of manufacturing a field effect transistor of the present invention, when an insulator is formed in a groove having a concave cross section, the insulator can be formed in a self-aligned manner without performing photolithography. Also, when the source region and the drain region are formed by diffusion and when the gate is formed, the grooves are self-aligned (indirectly via a single crystal silicon layer or an insulator side wall) without performing photolithography. (Although it is possible to form it). Therefore, the above-described field-effect transistor can be easily manufactured.

According to a method of manufacturing a field effect transistor of the present invention, oxygen ions are implanted into a semiconductor substrate having a groove having a concave cross section on the surface at a predetermined implantation energy, and a predetermined distance from the bottom of the groove into the semiconductor substrate. Forming a first oxygen ion implantation region extending in parallel with the bottom surface of the groove at a depth level entered, and implanting a second oxygen ion region at a depth level outside the groove and above a lower portion of the groove; Forming a region, annealing and reacting oxygen in the first and second oxygen ion implanted regions with the semiconductor substrate material to form the first and second oxygen ion implanted regions respectively in the first and second oxygen ion implanted regions; Changing the second insulator region, polishing the surface side of the semiconductor substrate, removing the second insulator region while leaving the lower portion of the groove, and at least the remaining groove Along the inside of , Depositing an insulator containing impurities in concave section with a substantially uniform thickness, anisotropically etching the insulator to remove the bottom of the concave cross section of the insulator,
Exposing the bottom surface of the groove in the gap between the sidewalls made of the remaining insulator; performing oxidation to form a gate oxide film on the bottom surface of the groove exposed in the gap; Forming a source region and a drain region at least in part by diffusing the impurities of the type described above into the inner surface of the trench in contact with the insulator side wall; and forming a gate electrode so as to fill a gap between the insulator side walls. Is formed.

According to the method for manufacturing a field effect transistor of the present invention, a field effect transistor which can be applied to a circuit requiring symmetry and which can simultaneously realize a high drain withstand voltage, a good S factor and a high driving capability is manufactured. Is done. That is, since the field effect transistor manufactured according to the present invention has a symmetric structure between the source and the drain, the field effect transistor can be applied to a circuit that requires symmetry such that the source and the drain are switched and operated. Also, during operation,
Since the extension of the depletion layer into the active region due to the gate potential is limited by the insulator region over the entire channel direction, the component of the gate potential that extends the depletion layer into the active region is reduced, and the component is accordingly reduced. The components forming the inversion layer in the channel region increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, a portion (semiconductor region) of the semiconductor substrate material where impurities are not diffused remains between the source region and the drain region of the inner surface portion of the groove and the insulator region, and the channel region and the insulator region Is connected to the semiconductor substrate below the semiconductor region via the semiconductor region, so that charges can be transferred between the active region and the semiconductor substrate below the insulator region. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, a higher voltage can be applied to the source region and the drain region, and high-speed operation can be performed. In addition, since the active region (including the channel region) is not the epitaxial silicon layer but the original semiconductor substrate material, an active region with few defects is provided. Therefore, the current driving capability can be further improved.

According to the method of manufacturing a field effect transistor of the present invention, photolithography is performed when forming an insulator region below a groove having a concave cross section and when forming a source region and a drain region by diffusion. Without
The groove can be formed in a self-aligned manner. Also, when the gate is formed, the gate can be formed in a self-aligned manner (although indirectly via the insulator side wall) without performing photolithography. Therefore, the above-described field-effect transistor can be easily manufactured.

According to the method of manufacturing a field effect transistor of the present invention, a step of forming a resist pattern having an opening corresponding to the groove by performing photolithography on a semiconductor substrate having a groove having a concave cross section on the surface; Oxygen ions are implanted into the surface of the semiconductor substrate at a predetermined implantation energy using the mask as a mask, and oxygen extending parallel to the bottom surface of the groove at a depth level that is a predetermined distance from the bottom surface of the groove into the semiconductor substrate. Forming an ion-implanted region, annealing to cause oxygen in the oxygen-ion-implanted region to react with a semiconductor substrate material to change the oxygen-ion-implanted region into an insulator region, and After removing, at least along the inner surface of the groove, a step of depositing an insulator containing impurities with a substantially uniform thickness in a concave cross section, Anisotropically etching the insulator, removing the bottom of the insulator having a concave cross-section, exposing the bottom surface of the groove to the gap between the sidewalls made of the remaining insulator, and performing oxidation, A gate oxide film is formed on the bottom surface of the groove exposed in the gap, and impurities in the insulator side wall are diffused into an inner surface portion of the groove in contact with the insulator side wall to form at least a source region and a drain region. A step of forming a part and a step of forming a gate electrode so as to fill a gap between the insulator side walls.

According to the method of manufacturing a field effect transistor of the present invention, a field effect transistor which can be applied to a circuit requiring symmetry and which can simultaneously realize a high drain withstand voltage, a good S factor and a high driving capability can be manufactured. Is done. That is, since the field effect transistor manufactured according to the present invention has a symmetric structure between the source and the drain, the field effect transistor can be applied to a circuit that requires symmetry such that the source and the drain are switched and operated. Also, during operation,
Since the extension of the depletion layer into the active region due to the gate potential is limited by the insulator region over the entire channel direction, the component of the gate potential that extends the depletion layer into the active region is reduced, and the component is accordingly reduced. The components forming the inversion layer in the channel region increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, a portion (semiconductor region) of the semiconductor substrate material where impurities are not diffused remains between the source region and the drain region of the inner surface portion of the groove and the insulator region, and the channel region and the insulator region Is connected to the semiconductor substrate below the semiconductor region via the semiconductor region, so that charges can be transferred between the active region and the semiconductor substrate below the insulator region. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, a higher voltage can be applied to the source region and the drain region, and high-speed operation can be performed. Therefore, the current driving capability can be further improved.

According to the method of manufacturing a field effect transistor of the present invention, photolithography is performed when forming an insulator region below a groove having a concave cross section and when forming a source region and a drain region by diffusion. Without
The groove can be formed in a self-aligned manner. Also, when the gate is formed, the gate can be formed in a self-aligned manner (although indirectly via the insulator side wall) without performing photolithography. Therefore, the above-described field-effect transistor can be easily manufactured.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First Embodiment) FIG.
The figure shows a MOS transistor. This NMOS transistor includes an n-type source region 103 and an n-type drain region 104 provided on a p-type silicon substrate 101 at a distance from each other, and the source region 103 and the drain region 1
04 covering the p-type channel region 109 between
4 is provided. The source region 103 has a high-concentration source region 105 having a certain junction depth, which is provided on the left side of the gate 114 in the drawing and a junction depth shallower than the high-concentration source region 105. Source area 1
And a source-side LDD region 107 extending from the gate-side end portion 05 to a position immediately below the gate. The drain region 104 includes a high-concentration drain region 106 having a certain junction depth and spaced to the right of the gate 114.
A drain-side LDD region 108 having a junction depth smaller than that of the high-concentration drain region 106 and extending from a gate-side end of the high-concentration drain region 106 to a position immediately below the gate.
It consists of

On the silicon substrate 101, a channel region 109 is formed from a position below the source side LDD region 107.
And a buried insulator region 102 extending to a position below the drain side LDD region 108 is provided. The level of the upper surface of the insulator region 102 is lower than the junction depth of the high-concentration source region 105 and the high-concentration drain region 106. This defines the thickness t of the active region 112 (including the channel region) between the gate 114 and the insulator region 102.

There are p-type semiconductor regions 110a and 110b between the source-side LDD region 107, the high-concentration source region 105 and the upper left corner of the insulator region 102, and the drain-side LDD region 108 and the high-concentration drain region 106 There are p-type semiconductor regions 111a and 111b between the semiconductor region and the upper right corner of the insulator region 102. As a result, the channel region 109 and the silicon substrate 101 have the same conductivity type as the semiconductor regions 110a, 110b, and 111.
a, 111b.

The dimensions of this transistor are set as follows. First, the length of the gate 114 is 2 μm
It is about. The expression "degree"
The range of the setting error is shown (the same applies hereinafter). Further, the thickness of the gate oxide film 115 is about 100
Is about 510 °, the thickness of the buried insulator region 102 is about 1 μm, and the width d of the semiconductor regions 110a, 110b and 111a, 111b between the buried insulator region and the source / drain region is about 500 °. . The junction depth of the high concentration source / drain regions 105 and 106 is 1
The impurity concentration is about 100 °, the impurity concentration is about 3 × 10 ²⁰ cm ⁻³ , the junction depth of the LDD regions 107 and 108 is about 360 °, and the impurity concentration is about 6 × 10 ¹⁹ cm ⁻³ . The impurity concentration of the channel region 109 is set to about 3 × 10 ¹⁷ cm ⁻³ .

In the transistor of this embodiment, the channel region 109 and the silicon substrate 101 are not insulated by the semiconductor regions 110a, 110b and 111a, 111b. Carriers can be efficiently released to the silicon substrate 101. In the dimension, the drain withstand voltage is 8 V or more, and a high drain withstand voltage can be obtained. In an SOI MOSFET having the same dimensions, hot carriers generated in the active layer 112 are accumulated in the active layer without being released to the substrate. Therefore, the drain withstand voltage is only about 4 V. Therefore, in the transistor of this embodiment, the drain withstand voltage can be improved by about 4 V.

Further, since the transistor of this embodiment has a symmetrical structure unlike the pseudo SOI type MOSFET, the symmetry is guaranteed electrically. Therefore, the present invention can be favorably applied to a circuit that requires symmetry, such as a pass transistor circuit, which operates by exchanging a source and a drain.

Further, the depletion layer existing in active layer 112 reaches the maximum depletion layer width Wmax when the inversion layer starts to be formed in channel region 109, and the maximum depletion layer width Wmax is reached.
Is defined as in the following equation (1).

[0042]

(Equation 1) Here, ε _S is the relative dielectric constant of the semiconductor (11.
9), ε ₀ is the dielectric constant of vacuum (8.85 × 10 ⁻¹⁴ F / c)
m). k is Boltzmann's constant (1.38 × 10 ^{- 23}
J / K), T is absolute temperature, ni is intrinsic carrier density (T
= 300K, Si 1.45 × 10 ¹⁰ cm ^-3 ), q
Is the elementary charge (1.60 × 10 ⁻¹⁹ C), and Na is the channel impurity concentration.

The absolute temperature T is 300 K, and the channel impurity concentration Na is
When an impurity concentration of 3 × 10 ¹⁷ cm ⁻³ of 9 is used, the maximum depletion layer width Wmax is about 620 ° from the equation (1). Since the thickness of the active layer 112 is about 510 °, in the transistor of this embodiment, the active layer 112 is completely depleted during operation. Therefore, the component of the gate potential that extends the depletion layer in active layer 112 decreases, and the component that forms the inversion layer of channel region 109 increases accordingly. As a result, fully depleted device characteristics are obtained, and S
Factor can be improved, and high driving capability can be achieved.

For complete depletion, it is necessary to set the channel impurity concentration Na so that the maximum depletion layer width Wmax does not fall below 510 °. In the case of the dimension of the present embodiment, the channel impurity concentration Na is 3.
It should be less than 5 × 10 ¹⁷ cm ⁻³ . When the thickness of the active layer 112 is changed, the channel impurity concentration N
If a is set so that the maximum depletion layer width Wmax in the equation (1) does not become less than the thickness of the active layer 112, the active layer can be completely depleted, and the S factor can be improved.
High drive capability can be achieved.

In the dimension shown in this embodiment, the S factor is 61 mV / dec. Has been achieved. In a planar MOSFET having a dimension similar to that of the present embodiment, the S factor is 92
mV / dec. It is. Also, with the same dimensions as those of the present embodiment, the fully depleted SOI type M
In OSFET, the S factor is 61 mV / de.
c. It is. That is, the transistor of the present embodiment has an S factor of 31 mV / de as compared with the planar MOSFET.
c. And fully depleted SOI MOS
It achieves the same S factor as FET. This is because, similarly to a fully depleted SOI MOSFET, when a potential difference is generated between one or more of the source and the substrate or the well and the drain and the gate, the active layer is completely depleted and the complete depletion occurs. This shows that depletion-type device characteristics can be obtained.

However, even when the entire region of the active layer 112 is not depleted, when a potential difference is generated between one or more of the source, the substrate or the well, and the drain and the gate, or In either case, the depletion layer existing in the active layer 112 and affected by the potential of the gate reaches the buried insulator 102, and the active layer 112
The extension of the depletion layer inside is limited. Thereby, the S factor and the driving capability are improved.

Further, since the buried insulator region 102 exists between the high-concentration source region 105 and the high-concentration drain region 106, the extension of the depletion layer from the drain region 104 can be efficiently restricted. It is effective in suppressing DIBL and punch-through. As a result, further miniaturization can be easily performed.

In addition, a punch-through current may flow when the depletion layer on the source side and the depletion layer on the drain side approach each other regardless of the control of the gate voltage. In order to reduce the current that cannot be controlled with such a gate voltage, it is effective to suppress the extension of the depletion layer in a deeper portion of the channel. Therefore, as in the present embodiment, the lower surface of the buried insulator 102 is
By forming it below the lower surface of the semiconductor region 05 and the high-concentration drain region 106, punch-through can be suppressed, and further miniaturization can be easily performed.

Further, even when the thickness of the active layer 112 is larger than the junction depth of the high-concentration source region 105 and the high-concentration drain region 106, the extension of the depletion layer in the deeper portion of the channel is suppressed. A structure in which a buried insulator is formed can suppress punch-through and facilitate further miniaturization.

The depletion layer extending from the source region 103 and the drain region 104 has a capacitance and becomes a parasitic capacitance when the transistor is turned on / off, preventing the high speed operation of the transistor. However, when the depletion layer is in contact with the buried insulator, the total capacitance is a series capacitance of the depletion layer capacitance and the buried insulator capacitance. Therefore, the parasitic capacitance can be reduced. The width W _SD of the depletion layer extending from the source region 103 and the drain region 104 is defined as in the following equation (2).

[0051]

(Equation 2) Here, the built-in potential Vb is

[0052]

(Equation 3) Is defined by Ε _S is the relative dielectric constant of the semiconductor (11.9 in the case of Si), and ε ₀ is the dielectric constant of vacuum (8.85 × 10
^-14 F / cm). k is Boltzmann's constant (1.38
× 10 ^-23 J / K), T is absolute temperature, q is elementary charge (1.
60 × 10 ⁻¹⁹ C). Also, ni is the intrinsic carrier density, Na is the concentration of the p-type semiconductor regions 110 and 111,
Nd is the concentration of the source / drain regions 103 and 104;
Is a voltage applied to the source electrode and the drain electrode.

By substituting the dimensions of the present embodiment into the equations (2) and (3), the depletion layer width W _SD when no voltage is applied to the source electrode and the drain electrode with respect to the substrate potential is equal to the high-concentration source. Is approximately 680 ° at the junction of the drain / drain regions 105 and 106 and the LDD regions 107 and 1
08 is about 660 ° at the junction.

According to the dimensions of the present embodiment, the distance between the source and drain regions 103 and 104 and the buried insulator 102 is as follows. That is,
The horizontal distance between the high-concentration source region 105, the high-concentration drain region 106 and the buried insulator 102, that is, the lateral dimension of the semiconductor regions 110b and 111b is about 270 ° at the shortest part, and is almost 600 ° or less. is there.
The vertical distance between the source-side LDD region 107, the drain-side LDD region 108, and the buried insulator 102, in other words, the vertical dimension of the semiconductor regions 110a and 111a is about 150 °.

Therefore, source and drain regions 10
Most of the depletion layer extending between the third and the 104 and the buried insulator 102 is in contact with the buried insulator 102, so that the parasitic capacitance can be greatly reduced in the contact portion, and the high-speed operation of the transistor Becomes possible.

In order to reduce the parasitic capacitance, a depletion layer extending from the source region 103 and the drain region 104 needs to be in contact with the buried insulator 102.
For that purpose, the p-type semiconductor regions 110a, 110b,
The concentration of 111a and 111b must be 2 × 10 ¹⁸ cm ⁻³ or less.

The position of the buried insulator 102 and p
Semiconductor regions 110a, 110b, 111a, 111
The concentration of b and the concentration of source / drain regions 103 and 104 are determined by the relationship between W _SD and Na and Nd in equations (2) and (3). Can be set freely within a range that does not exceed the depletion layer width W _SD . Within this range, the parasitic capacitance is reduced, and the transistor can operate at high speed.

In this embodiment, the gate length is set to 2 μm. However, even if the gate length is shortened to 0.4 μm, the S factor is 65.9 mV / dec. Therefore, the deterioration of the S factor due to the short channel is suppressed. The difference Δ between the threshold voltage when the gate length is 0.4 μm and the threshold voltage when the gate length is 2 μm
Vth is suppressed to 0.03V. As described above, when the gate length is between 2 μm and 0.4 μm, the deterioration of the transistor characteristics due to the short channel effect is suppressed low. Therefore, the channel can be easily shortened. Further, by reducing the gate length in accordance with the design rules, high integration of the semiconductor element can be achieved.

In the present embodiment, the thickness of the gate oxide film 115 and the thickness of the active layer 112 are each set to 10
Although they are set to 0 ° and 510 °, they can be changed as follows to improve the S factor.

The S factor is defined by the following equation (4).

[0061]

(Equation 4) Here, k is Boltzmann's constant (1.38 × 10 ⁻²³ J /
K), T is absolute temperature, q is elementary charge (1.60 × 10 ⁻¹⁹⁾
C). Cd is the capacitance of the depletion layer of the active layer controlled by the gate potential, and Cox is the capacitance of the gate oxide film. From equation (4), to lower the S factor:
It can be seen that it is effective to increase Cox and decrease Cd.

In practice, the thickness of the gate oxide film 115 is
It is possible to reduce the thickness to about 30 to 50 °, at which the tunnel current does not flow. Gate oxide film 115
From the above-mentioned 100 ° to a practical lower limit of 30 to
When the angle is changed to about 50 °, Cox increases, the S factor is improved based on the equation (4), and high-speed operation of the transistor becomes possible.

Further, the thickness of the active layer 112 is set to 510
When 薄 く is changed to a smaller value, Cd becomes smaller, the S factor is improved based on the equation (4), and the transistor can operate at high speed.

When the conductivity type of the channel region is desired to be different from the conductivity type of the semiconductor substrate 101, a transistor is not formed directly on the semiconductor substrate as shown in FIG. Region 129 (usually referred to as “well region”) of a conductivity type different from
Is formed, and a transistor is formed on the well region 129. As a result, the conductivity type of the semiconductor substrate 101 becomes N
Regardless of the type or the P type, a transistor of a desired channel type can be manufactured.

Further, as shown in FIG.
The second and third buried insulators 102 ′ and 102 ′ may be formed below the high-concentration source region 105 and the high-concentration drain region 106 together with the buried insulator 102 passing below the portion 09. Thus, the junction capacitance between the high-concentration source region 105 and the high-concentration drain region 106 is significantly reduced, so that the operation speed and power consumption of the transistor can be improved. The buried insulator 102 and the second and third buried insulators 102 ′, 102 ′
They may be formed at the same time, or may be formed in different steps at different times.

Further, as shown in FIG. 4, the structure shown in FIG. 2 may be combined with the structure shown in FIG. Accordingly, a transistor of a desired channel type can be manufactured regardless of whether the conductivity type of the semiconductor substrate 101 is N-type or P-type, and the junction capacitance of the high-concentration source region 105 and the high-concentration drain region 106 is significantly increased. As a result, the operation speed and power consumption of the transistor can be improved.

As shown in FIG. 5, the structure shown in FIGS. 3 and 4 may be integrated on the same semiconductor substrate 101. Accordingly, the junction capacitance of the high-concentration source region 105 and the high-concentration drain region 106 is significantly reduced, and an integrated circuit with improved operation speed and power consumption of a transistor can be manufactured. In this case, it is desirable to form the buried insulator 102 in each transistor at the same time. By doing so, the process can be simplified as compared with the case where they are not formed at the same time.

As described above, the field effect transistor of the present invention can be variously modified without departing from the gist thereof.

Referring to FIGS. 6 to 10, a method of manufacturing the field effect transistor will be described step by step. Note that a transistor which is substantially the same as the transistor illustrated in FIGS.

First, as shown in FIG.
Having a buried oxide film 719 as an insulator layer and a single-crystal silicon layer 730 on a silicon substrate 717
An OI wafer is prepared. Single crystal silicon layer 730 has a thickness of about 780 °, and buried oxide film 719 has a thickness of 1 μm.
Degree. By performing dry oxidation on the SOI wafer, an injection protection oxide film 727 having a thickness of about 200 ° is formed on the surface of the single crystal silicon layer 730. Next, FIG.
As shown in (b), a well implantation is performed to form a P-type well implantation region 729. In this well implantation, boron ions are implanted at an implantation energy of about 150
× injected with 10 ^{1 5} cm approximately ^-2 performs rotational implantation or step implanted at angle of about 7 degrees for preventing channeling. Next, after removing the implantation protection film 727, boron ions in the well implantation region 729 are activated by performing N ₂ annealing treatment at a temperature of 1200 ° C. for 800 minutes using a diffusion furnace. As a result, a P-type well region 729 (for simplicity, represented by the same reference numeral as before activation) could be formed.

Of course, when an SOI wafer whose base is a P-type silicon substrate is used, the well region 729 is used.
Need not be formed.

Next, as shown in FIG. 6C, photolithography is performed to provide a resist pattern 725 for separating the buried oxide film 719 into a plurality of insulator regions. Then, anisotropic silicon etching is performed using the resist 725 as a mask, a groove 733 is formed in accordance with the resist pattern, and the single crystal silicon layer 730 is separated into a plurality of regions.

In a later step, a channel region is formed in active layer 712 formed of single crystal silicon layer 730. Since a channel region important for determining transistor characteristics is formed in the single-crystal silicon layer of the original SOI wafer, a problem occurs in a pseudo-SOI MOSFET in which the channel region is formed of an epitaxial silicon layer. It is possible to avoid a decrease in current driving capability due to defects such as grain boundaries.

Next, as shown in FIG. 7D, anisotropic oxide film etching is further performed using the resist 725 as a mask, and a groove 733 is formed deeply until the silicon substrate 717 (well region 729) is reached. , Buried oxide film 71
9 into a plurality of regions.

By forming a semiconductor region of the same conductivity type as that of the channel region in this groove 733 in a later step, charges are transferred between the channel region and the silicon substrate or the well region via the semiconductor region. Movement becomes possible.
In a later step, epitaxial silicon is grown in the groove 733. Therefore, in order to reduce the aspect ratio sufficiently so that the trench 733 is filled with epitaxial silicon, it is necessary to secure a certain width of the trench 733. In this example, the width of the groove 733 is about 2 μm. However, when the selective epitaxial growth method in which the lateral growth is suppressed is used, the width of the groove 733 can be set to 2 μm or less.

Next, as shown in FIG. 7E, a single crystal silicon layer (epitaxial silicon layer) 713 containing boron is grown thereon by a selective epitaxial growth method to a thickness of about 1.5 μm. Thereby, each groove 73
3 is filled with epitaxial silicon. here,
The impurity concentration of the epitaxial silicon layer 713 is 4 × 10 ¹⁵ cm ⁻³ , similarly to the impurity concentration of the well region 729.
Degree. At this time, epitaxial growth does not occur on both sides of the buried oxide film 719. Therefore, a facet may be generated between the epitaxial silicon grown from the substrate silicon 717 and the buried oxide film 719. Similarly, a facet may be generated between epitaxial silicon grown from the single crystal silicon layer 730 and the buried oxide film 719. Thereby, after the selective epitaxial growth, the buried oxide film 719 is formed.
A gap is formed between both side surfaces of the substrate and the epitaxial silicon layer 713. However, since the gap functions as an insulator similarly to the buried oxide film 719, it does not hinder the function of the buried oxide film. Further, there is no possibility that a gap having a shape large enough to reach the source / drain region or the channel region is formed. Therefore, there is no hindrance in manufacturing a target field-effect transistor.

Next, as shown in FIG.
(Chemical mechanical polishing) is performed to flatten the surface of the epitaxial silicon layer 713. At this time, the epitaxial silicon layer 713 is polished by about 1.5 μm from the uppermost surface, and the polishing is terminated when the surface of the single crystal silicon layer 730 is exposed. Accordingly, the surface of single crystal silicon layer 730 and epitaxial silicon layer 713 are on the same plane, and oxide film 719 is embedded in continuous single crystal silicon layer 730 and epitaxial silicon layer 713. Single crystal silicon layer 7 above buried oxide film 719
30 becomes the active layer 712 including the channel region.

Next, as shown in FIG.
An oxide film 735, which is required as a base for forming a nitride film, is formed on the surface of the substrate 12 to a thickness of about 100 to 300 °. It is deposited uniformly with a thickness of about 1500 °. The thickness of this nitride film 736 is LOCOS
Although it is necessary to increase the thickness from the viewpoint of suppressing bird's beak which is a problem when forming the oxide film, it is necessary to reduce the thickness from the viewpoint of reducing crystal defects generated in the silicon substrate during LOCOS oxidation. After all, considering the tradeoff between the two, it is preferable to select the optimum thickness of the nitride film 736 in the range of about 500 to 3000 °. Next, by performing photolithography, a resist (not shown) is provided so that a region where a LOCOS is to be formed becomes an opening of the resist, and anisotropic nitride film etching is performed using the resist as a mask. The nitride film 736 is patterned so that the region where the LOCOS is to be formed is an opening. Next, after the resist is removed, as shown in FIG.
LOCOS oxide film 737 is formed. After that, the oxidation-resistant nitride film 736 and the oxide film 735 are completely removed. Next, dry oxidation is performed to form an injection protection oxide film 727 having a thickness of about 100 °.

Next, channel implantation (ion implantation for setting the threshold voltage of the channel region) is performed to form a P-type channel implantation region 739 (shown only in FIG. 8H). This channel injection, about the implantation energy 15keV boron ions, implantation of 1 × was injected at 10 ^{1 2} cm about ^-2, for rotating injection or step implanted at angle of about 7 degrees for preventing channeling.

Next, after removing the injection protection film 727, a gate oxide film 738 having a thickness of about 100 ° is formed as shown in FIG. As described above, when the thickness of the gate oxide film 115 is changed from the above-mentioned 100 ° to a practical lower limit of about 30 to 50 °, Cox increases, and the S factor increases based on the equation (4). Thus, high-speed operation of the transistor is enabled.

Next, as shown in FIG. 9J, polysilicon containing impurities is uniformly deposited on the gate oxide film 738 by LPCVD so as to have a thickness of about 1000 to 6000 °. Photolithography is performed to form a patterning resist (not shown) in a region where a gate electrode is to be formed. In the present embodiment, the width of the patterning resist is about 2 μm. Next, as shown in FIG. 9K, anisotropic polysilicon etching is performed only on the opening using the resist as a mask, and then the resist is removed. Thus, a gate electrode 716 was formed on the gate oxide film 738. Next, as shown in FIG. 9L, ion implantation is performed using the gate electrode 716 as a mask to form N-type LDD regions 707 and 708 in portions of the active layer 712 corresponding to both sides of the gate electrode. . In this ion implantation, arsenic ions are implanted at an implantation energy of 5 keV.
About 2 × 10 ¹⁴ cm ⁻² , and rotation or step implantation is performed at an implantation angle of about 7 ° to prevent channeling.

Next, an oxide film is uniformly deposited on the entire surface to a thickness of about 1400 ° by the LPCVD method.
As shown in (1), anisotropic etching is performed to form a sidewall oxide film 734 composed of a part of the oxide film on both sides of the gate electrode 716. Next, as shown in FIG.
Ion implantation is performed using the gate electrode 716 and the sidewall oxide film 734 as a mask, and an N-type high-concentration source / source is formed in a region of the active layer 712 corresponding to the side of the gate electrode 716.
Drain regions 707 and 708 are formed. In the ion implantation of arsenic, arsenic ions are implanted at an implantation energy of about 40 keV and an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , and rotation implantation or step implantation is performed at an implantation angle of about 7 ° to prevent channeling. Next, activation annealing is performed at a temperature of 800 ° C. for a time period of about 10 minutes to form high-concentration source / drain regions 707 and 7.
08 is activated.

Here, the implantation energy of the high-concentration source region 707 and the high-concentration drain region 708 was about 40 keV, and the implantation amount was about 5 × 10 ¹⁵ cm ^−2. The junction capacitance can be made smaller as the impurity concentration of the region becomes thinner. Also, punch-through can be suppressed as the junction depth becomes shallower. Therefore, it is possible to change the implantation energy and the implantation amount in consideration of these.

When the transistor is manufactured as described above,
A portion of the active layer 712 between the high-concentration source region 707 and the high-concentration drain region 708 is a channel region 709.
Becomes That is, a channel region 709 important for determining transistor characteristics is formed using a single crystal silicon layer 730 of an SOI wafer having good crystallinity. As a result, pseudo S in which the channel region is formed by the epitaxial silicon layer
It is possible to avoid a decrease in current driving capability due to defects such as grain boundaries during growth, which is a problem in the case of the OI type MOSFET.

After that, the well-known interlayer film forming step and wiring forming step are performed to complete the field effect transistor.

(Second Embodiment) A method of manufacturing a field effect transistor according to another embodiment will be described with reference to FIGS.

First, as shown in FIG. 11A, a resist (not shown) having an opening for forming a groove is provided on the surface 217a of the P-type silicon substrate 217 by photolithography. Is used as a mask to form an anisotropic silicon etching to form a groove 223 having a concave cross section in the silicon substrate 217. After the etching, the resist is removed. Here, the width of the groove 223 having a concave cross section is set to be larger than the target gate length by about 0.34 μm. In the present embodiment, since the target gate length is about 0.40 μm, the width of the groove 223 is set to 0.74 μm.
It is about μm. The depth of the groove 223 is 1.15 μm.
m.

Thanks to the groove 223 having a concave cross section, a buried oxide film forming step, an LDD region forming step,
A channel region forming step, a gate electrode forming step, and
All the source / drain region forming steps can be performed in a self-aligned manner. Thus, a photolithography process requiring strict alignment can be omitted, and the process can be simplified. However, as described later, L
In the DD region forming step and the source / drain region forming step, it is necessary to perform photolithography so as not to connect the diffusion regions on the source side and the drain side.

Next, as shown in FIG. 11B, the silicon substrate 217 is
An oxide film 219 serving as a buried insulator material is uniformly deposited on the entire surface. Finally, the trench 223 is completely filled with the oxide film 219 by taking a growth time until a film thickness of about 1.5 μm is deposited. Here, an oxide film will be described as an example of the material of the buried insulator, but any material that can restrict the extension of the depletion layer, such as a nitride film or an oxynitride film, may be used. Next, as shown in FIG. 11C, the surface of the oxide film 219 is flattened by performing CMP. In this case, the oxide film 2
19 is polished by about 1.5 μm from the uppermost surface, and the polishing is finished when the silicon substrate surface 217a is exposed. Subsequently, as shown in FIG. 11D, the oxide film is selectively anisotropically etched with respect to the silicon substrate to remove the surface portion of the oxide film 219 by about 1500 °.
Thus, an oxide film 219 having a flat surface is left at a thickness of about 1 μm on the bottom 223b of the groove 223.

Thus, the buried oxide film 219 is
A completely symmetrical structure can be formed in a self-aligned manner with respect to the groove 223. Further, since a photolithography process requiring strict alignment is not required, the process can be simplified. In addition, since the shape of the groove 223 is left, the LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step, which will be described later, are all formed in a self-aligned manner. Can be. In addition, thereby, in each of the steps,
Since the photolithography process can be omitted, the process can be simplified. However, as described later, in the LDD region forming step and the source / drain region forming step, it is necessary to perform photolithography in order to prevent the diffusion regions on the source and drain sides from being connected.

Next, as shown in FIGS. 12E to 12F, the surface 217a of the silicon substrate 217, the silicon sidewall 223a in the trench, and the surface 21 of the buried oxide film 219 are formed.
A single-crystal silicon layer 213 having a uniform thickness of about 700 ° is provided along 9a.

More specifically, first, as shown in FIG. 12E, a silicon substrate 217 is formed by an epitaxial growth method.
The single crystal silicon layer 241 is grown on the surface 217a of the trench and the silicon sidewall 223a in the trench, and the amorphous silicon layer 242 is grown on the surface of the buried oxide film 220 in the trench. Each layer has a thickness of about 10 to 100 °. Next, a laser or an electron beam is focused by a lens to a beam diameter of about 1 to 100 μm to enter the amorphous silicon layer 242 from the outside of the illustrated single crystal silicon layer 241, that is, from outside the transistor formation area to the transistor formation area. Scan inside. Thereby, the single crystal silicon layer 24
The crystallization proceeds in the lateral direction from 1 to form the amorphous silicon layer 24.
2 is converted into single crystal silicon.

When an electron beam is used, a combination of a plurality of capacitor-like conductive plates to which a potential is applied may be used as a lens. Further, the amorphous silicon layer 242 may be formed into single crystal silicon by irradiating the amorphous silicon layer 242 with a pulse by using a laser or an electron beam in an arbitrary beam shape with an aperture. Further, in order to effectively single-crystallize the amorphous silicon layer, a combination of at least one of a lens and an aperture may be used. At that time, scan irradiation or pulse irradiation to the amorphous silicon layer may be selected as necessary.

Next, as shown in FIG. 12 (f), a single-crystal epitaxial silicon is formed to a thickness of 400 to 49 from the single-crystal silicon layer formed by epitaxial growth.
Grow about 0 °.

As described above, along the surface 217a of the silicon substrate 217, the silicon side wall 223a in the groove and the surface 219a of the buried oxide film 219, the thickness of 700
A single-crystal silicon layer 213 is formed with a uniform thickness. The portion of the single crystal silicon layer 213 inside the groove 223 is formed to have a concave cross section reflecting the shape of the groove 223.
As a result, the oxide film 219 is buried under the groove 223 by the single crystal silicon layer 213 serving as an active layer.

Next, as shown in FIG. 12 (g), the LOCOS is formed on the surface 217a of the silicon substrate 217 corresponding to both sides of the groove 223 by a normal element isolation LOCOS forming step.
An S (local oxide film) 237 is formed.

Next, as shown in FIG.
The recess 213 of the single crystal silicon layer 213 is formed by the VD method.
An oxide film 218 containing impurities is uniformly deposited to a thickness of about 1000 ° on a, 213b and flat surface 213c. Single-crystal silicon layer 2 of impurity-containing oxide film 218
The portions deposited in the 13 recesses 213a and 213b are formed to have a concave cross section reflecting the shape of the recess. Here, as the impurity-containing oxide film 218, 1 × 10 ²⁰ phosphorus is used.
cm ^{- 3} about using doped PSG. Next, FIG.
As shown in (i), anisotropic etching is performed to remove portions of the impurity-containing oxide film 218 on the concave bottom surface 213b and the flat surface 213c of the single crystal silicon layer 213. Thereby, the concave side surface 2 of the single crystal silicon layer 213 is formed.
Side walls 218 and 218 (represented by the same reference numerals as the original oxide film for simplicity) are formed on the remaining oxide films 13a and 213a. The gap between the side walls 218, 218 constitutes a new groove 224 having a smaller width than the original groove. Since the thickness of the side wall 218 is substantially equal to the thickness of the deposited film, the width of the new groove 224 is
It is accurately controlled by the film thickness. When a gate electrode is formed so as to fill the new groove 224 in a later step, the width of the lower end of the new groove 224 becomes the gate length. In general, when a gate electrode is formed, a minimum gate length is defined by a physical limit of a minimum processing line width in a photolithography process. However, according to the present embodiment, the new groove 2
By optimizing the width / depth aspect ratio of 24, a gate length below the physical limit of the minimum processing line width of the photolithography process can be formed.

In this embodiment, the side walls 218, 2
It is planned that impurities in 18 will be diffused into the inner surface portion of single crystal silicon layer 213 in contact with the side wall to form an LDD region. In that case, it is necessary to avoid the connection between the LDD regions on the source side and the drain side on the pattern. FIG. 20A shows a plane pattern at this stage (FIGS. 11 to 14 correspond to a cross section taken along line AA in FIG. 20A, and L is a gate length). As can be seen from FIG. 20A, it is necessary to avoid connection between the LDD regions on the source side and the drain side because the side walls 218 are connected in a rectangular frame shape with the channel interposed therebetween. Therefore, as shown in FIG. 20B, photolithography is performed to cover a main part of the element region (enclosed by the LOCOS pattern 237a) except for both ends 226 in the width direction of the channel. 225 are provided. Then, as shown in FIG. 20C, anisotropic etching is performed using the resist 225 as a mask to remove both end portions of the impurity-containing oxide film 218. By doing so, when the LDD region is formed by solid layer diffusion from the side wall 218, it is possible to prevent the source side and the drain side LDD regions from being connected.

When an inversion layer is formed in the channel region during the operation of the transistor, both ends 226 in the channel width direction are formed.
The inversion layer is formed by the gate electrode extending therethrough via the gate oxide film, so that a two-stage threshold voltage may occur. In order to avoid this, ion implantation at a higher concentration than the concentration in the channel region is performed by rotation or step implantation at an implantation angle of about 45 degrees into both ends 226 in the channel width direction. Here, the implantation energy 15keV about boron ion implantation amount ¹ × 10 1 ⁴ ~5
× injected with 10 ^{1 5} cm approximately ^-2 performs rotational implantation or step implanted at angle of about 45 degrees. After that, the resist 225
Is removed.

Next, as shown in FIG. 13 (j), wet oxidation is performed at a temperature of 800 ° C. for about 21 minutes to form a groove 22
On the bottom surface 213b and the flat surface 213c of the concave portion of the single crystal silicon layer 213 exposed at the bottom of the substrate 4, an oxide film 227 serving as a channel injection protection film is formed with a thickness of about 100 °. At this time, impurities contained in sidewall oxide film 218 diffuse into the inner surface of single crystal silicon layer 213 in contact with sidewall oxide film 218, and LDD regions 207 and 208 are formed. However, since there is a step of diffusing the LDD region after this, the junction depth of the LDD region is not determined in this step.

Next, as shown in FIG. 14 (k), channel implantation is performed to remove the side wall 2 of the single crystal silicon layer 213.
18, a P-type channel region 209
To form In this channel implantation, boron ions are implanted at an implantation energy of about 15 keV and an implantation amount of about 1 × 10 ¹² cm ⁻² , and rotation implantation or step implantation is performed at an implantation angle of about 7 degrees to prevent channeling. After that, the injection protection film 227 is removed.

Next, wet oxidation is performed at a temperature of 800 ° C. for a time period of about 21 minutes, and a thickness of 100
A gate oxide film 215 of about Å is formed. At this time, the impurity contained in the sidewall oxide film 218 diffuses,
The junction depth between the LDD regions 207 and 208 is increased. However, since there is a step of diffusing the LDD region after this, the junction depth of the LDD region is not determined in this step.

Next, polysilicon containing impurities is grown thereon with good uniformity by the LPCVD method, and the trench 224 between the side wall insulators 218 is filled with polysilicon 228, and a substantially flat surface is obtained. Polysilicon 228 is deposited to a thickness of about 2000-6000 °. Next, as shown in FIG. 14 (l), anisotropic etching with a high selectivity is performed on the oxide film to etch the entire surface of the polysilicon 228, and a portion of the polysilicon is placed in the groove 224. The gate electrode 216 is left. that time,
Oxide film 215 'on epitaxial silicon layer flat surface 213c formed at the time of gate oxide film formation (FIG. 14 (k)
Is exposed, and the polysilicon 228 and the source / drain region are separated by the impurity-containing oxide film 218, so that overetching is performed until the polysilicon 228 is completely insulated. However, if the oxide film 215 'on the source / drain region is partially removed and the silicon surface of the source / drain region is etched, the surface may be roughened and the contact resistance may increase. For this reason, in the case of over-etching, it is necessary to switch to anisotropic etching having a higher selectivity to the oxide film.

In this way, the gate electrode 216 is
24 can be formed in a self-aligned manner. Thus, a photolithography step requiring strict alignment can be omitted, and the step can be simplified.

Next, as shown in FIG. 21E, the planar pattern at this stage shown in FIG. 21D is subjected to photolithography to perform injection protection for forming high-concentration source / drain regions. A resist 231 is formed. The pattern of the resist 231 has an opening (width W) inside the pattern 225 (see FIG. 20B) used when the impurity-containing oxide film 218 is etched in the above-described LDD region forming step. I do. Then, FIG.
As shown in (m), ion implantation is performed to form N-type high-concentration source / drain regions 205 and 206. In this ion implantation, arsenic ions are implanted at an implantation energy of 40 ke.
Injection is performed at an injection angle of about V and about 5 × 10 ¹⁵ cm ⁻² , and rotation injection or step injection is performed at an injection angle of about 7 ° to prevent channeling. Next, the high concentration source / drain regions 20
In order to activate 5, 206, activation annealing is performed at a temperature of 800 ° C. for about 10 minutes. At this time, the sidewall oxide film 2
The diffusion depth of the impurities contained in 18 increases the junction depth of LDD regions 207 and 208. After that, since there is no diffusion step, the junction depth of the LDD region is determined in this step. In the present embodiment, the LDD regions 207 and 20
8 has a final junction depth of about 300 ° from the contact surface with the sidewall oxide film 218. Thus, the groove 223 (FIG. 11) formed first on the surface of the silicon substrate 217 is formed.
Based on the shape of (a), the single-crystal silicon layer 21 is formed.
The LDD regions 207 and 208 can be formed in a self-aligned manner and completely symmetrically via the side walls 3 and the sidewall oxide film 218.

After that, the well-known interlayer film forming step and wiring forming step are performed to complete the field effect transistor.

As described above, the buried oxide film forming step
The LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step can all be performed in a self-aligned manner with respect to the groove 223.
A field effect transistor completely symmetrical in the source / drain direction can be manufactured.

The manufactured field-effect transistor has a symmetric structure between the source 203 and the drain 204.
The present invention can also be applied to a circuit requiring symmetry such that the source 203 and the drain 204 are interchanged and operated. Also, during operation, the active region 20 due to the potential of the gate 216
Since the extension of the depletion layer into the active regions 209 and 213 is reduced by the insulator region 219 throughout the channel direction, the component of the gate potential that extends the depletion layer into the active regions 209 and 213 decreases. Only channel region 209
The components that form the inversion layer increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, between the source side LDD region 207 and the drain side LDD region 208 and the insulator region 219,
A portion (semiconductor region) of the single crystal silicon layer 213 where impurities are not diffused remains, and the channel region 2
Since the semiconductor substrate 09 and the silicon substrate 217 are connected to each other via the semiconductor region, charges can be transferred between the active regions 209 and 213 and the silicon substrate 217. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, a higher voltage can be applied to the source region 203 and the drain region 204 correspondingly, and high-speed operation can be performed.

The manufactured field-effect transistor has a so-called groove structure in which the gate 214 is buried in the groove, and the source / drain region has the gate electrode 2.
16 are present on the left and right sides of the substrate 16 via a side wall insulator 218.
Generally, in such a field effect transistor having a groove structure, there is a problem of parasitic capacitance between a gate electrode and a source / drain region. However, in this embodiment, since the width of the side wall insulator 218 is 0.1 μm, the parasitic capacitance between the gate electrode and the source / drain region can be sufficiently reduced. Thus, high-speed operation of the transistor can be performed.

(Third Embodiment) In the manufacturing method of the second embodiment, when the gate length is short, when connecting the gate electrode and the metal (wiring) via the contact hole,
A margin for alignment (alignment) between the contact hole and the gate electrode becomes very small. For this reason, misalignment between the gate electrode and the contact hole during the formation of the metal contact causes a reduction in the connection area between the metal and the gate electrode, and as a result, the contact resistance may be increased. In order to avoid the problem, it is useful to extend the gate electrode to the silicon surface where the transistor is not formed, and to form a large-sized extraction electrode. In the present embodiment, such a manufacturing method will be described with reference to FIG. In FIG. 15, elements corresponding to the elements in FIG. 14 are represented by reference numerals increased by 100.

First, as in the second embodiment, FIG.
The process is performed up to the polysilicon CVD growth process shown in FIG. Next, as shown in FIG. 15A, photolithography is performed to provide a patterning resist 325 for forming a gate electrode in a region corresponding to the groove 224 on the surface of the polysilicon 328. At this time, while paying attention to the alignment so that the gate electrode does not short-circuit with the source / drain regions in a later step, a pattern for extracting the gate electrode from the inside of the groove 324 to the silicon surface where the transistor is not formed, and a large extraction The electrode pattern is simultaneously patterned. Next, as shown in FIG.
Anisotropic polysilicon etching is performed using the resist 325 as a mask to form a gate electrode 316 having a substantially T-shaped cross section. After that, the resist 325 is removed. In this manner, the large extraction electrode pattern allows a large margin for alignment between the contact hole and the gate electrode, and thus avoids the possibility of a semiconductor device having a high contact resistance. Thereafter, similarly to the second embodiment, N-type high-concentration source / drain regions 305 and 306 are formed on the sides of the gate electrode 316. Further, a well-known interlayer film forming step and a wiring forming step are performed to complete the field effect transistor.

According to the third embodiment, the buried oxide film forming step, the LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step are performed in the same manner as in the second embodiment. All can be performed in a self-aligned manner with respect to the groove 324, and a field effect transistor completely symmetric in the source / drain direction can be manufactured.

The manufactured field-effect transistor is the second type.
As in the embodiment, since the source 303 and the drain 304 have a symmetric structure, the source 303 and the drain 304
Can be applied to a circuit that requires symmetry to operate by replacing In operation, the extension of the depletion layer into active regions 309 and 313 due to the potential of gate 316 is limited by insulator region 319 over the entire region in the channel direction.
The components that extend the depletion layer into 9, 313 decrease, and the components that form the inversion layer of the channel region 309 increase accordingly. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. The source-side LDD region 30 in the inner surface of the single crystal silicon layer 313
7. Between the drain side LDD region 308 and the insulator region 319, a portion (semiconductor region) of the single crystal silicon layer 313 where impurities are not diffused remains, and the channel region 309 and the silicon substrate 317 Since the connection is established through the regions, the charge can be transferred between the active regions 309 and 313 and the silicon substrate 317.
Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, the source region 30
3. A high voltage can be applied to the drain region 304 correspondingly, and high-speed operation can be performed.

(Fourth Embodiment) A method of manufacturing a field-effect transistor according to another embodiment will be described step by step with reference to FIGS.

First, as shown in FIG. 16A, a resist (not shown) having an opening for forming a groove is provided on the surface 417a of the P-type silicon substrate 417 by photolithography. Anisotropic silicon etching is performed using as a mask to form a groove 423 having a concave cross section in the silicon substrate 417. After the etching, the resist is removed. Here, the width of the groove 423 having a concave cross section is set to be larger than the target gate length by about 0.20 μm. In the present embodiment, since the target gate length is set to about 0.40 μm, the width of the groove 223 is set to 0.60 μm.
It is about μm. The depth of the groove 223 is 1.23 μm.
m.

Next, on this silicon substrate 417, oxygen ions are implanted at an energy of about 180
^Implant about 4.5 × 10 ¹⁷ cm ⁻² . Thereby, the groove 4
A first oxygen ion implanted region 419 extending parallel to the bottom surface of the groove is formed at a depth level that is a predetermined distance from the bottom surface of the silicon substrate into the silicon substrate. A second oxygen ion implantation region 422 is formed at the level. Here, the injection amount of oxygen ions is
Since the implantation dose is set to be lower than 1.2 × 10 ¹⁸ cm ⁻² or more, which has been practically used in conventional SIMOX (separation by implanted oxygen) wafers, dislocations, etc. Can be avoided. Next, the temperature 130
A high-temperature anneal of about 0 ° C. is performed to restore crystallinity, and the first and second oxygen ion implanted regions 419,
By reacting the oxygen in 422 with the silicon substrate material, the first and second oxygen ion implanted regions are respectively a first and a second insulator region (for simplicity, denoted by the same reference numerals as the implanted regions) 419 , 422. The silicon substrate material on the first insulator region (buried oxide film) 419 becomes the active layer 412. Thereafter, in order to further reduce the thickness of the active layer 412, the temperature is set to about 800 to 1000 ° C. for 2 hours.
The wet oxidation is performed for about 0 to 70 minutes, and then the surface oxide film is entirely removed. As a result, the thickness t of the active layer 412 is set to about 700 ° and the thickness of the buried insulator 419 is set to 1 μm.
m. In addition, instead of the above wet oxidation, oxygen atoms are introduced into the furnace by either dry or wet simultaneously with high temperature annealing for crystallinity recovery,
The silicon surface may be oxidized.

Next, as shown in FIG. 16B, the surface side of the silicon substrate 417 is polished to leave the lower portion of the groove 423 and the silicon substrate material 421 and the second material existing in the region outside the groove 523. The insulator region 422 is removed.

In this way, the embedded insulator 419 extending below the groove 423 in parallel with the groove bottom can be formed completely symmetrically with the groove 423 of the silicon substrate 417 in a self-aligned manner. . Further, thanks to the groove 423, the LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step can be formed in a self-alignment manner. In addition, the photolithography step can be omitted in each of the steps, so that the steps can be simplified. However, as described later, an LDD region forming step,
In the source / drain region forming step, it is necessary to perform photolithography in order to prevent connection between the source and drain diffusion regions.

Next, the silicon substrate 417 corresponding to both sides of the groove 423 is formed by a normal element isolation LOCOS forming process.
LOCOS 437 is formed on the surface of.

[0120] Then, by the LPCVD method, the bottom surface of the groove 423, on the side surface and the groove 423 outside of the flat surface 417a, the oxide film (here, containing an impurity, phosphorus 1 × 10 ²⁰ cm ^- was approximately ³ doped PSG Is uniformly deposited to a thickness of about 1000 °. The portion of the impurity-containing oxide film deposited in the groove 423 is formed to have a concave cross section reflecting the shape of the concave portion. Next, as shown in FIG. 16C, anisotropic etching is performed to remove the bottom surface 423b of the groove 423 and the flat surface 41 outside the groove in the impurity-containing oxide film.
The part on 7a is removed. As a result, the side walls 418, 418 made of the remaining impurity-containing oxide film are formed on the side surfaces 413a, 413a of the groove 423. This side wall 418,
The gap between 418 constitutes a new groove 424 that is narrower than the original groove. Since the thickness of the sidewalls 418 is approximately equal to the thickness of the deposited film, the width of the new groove 424 is
It is accurately controlled by the CVD film thickness. When a gate electrode is formed so as to fill the new groove 424 in a later step, the width of the lower end of the new groove 424 becomes the gate length. In general, when a gate electrode is formed, a minimum gate length is defined by a physical limit of a minimum processing line width in a photolithography process. However, according to the present embodiment, by optimizing the aspect ratio of the width and the depth of the new groove 424, it is possible to form a gate length smaller than the physical limit of the minimum processing line width in the photolithography process.

Next, as described in the second embodiment,
In order to avoid connection between the LDD regions on the source side and the drain side, portions corresponding to both ends in the channel width direction of the side walls 418 connected in a rectangular frame shape in the plane pattern (see FIG. 20) are removed. In addition, when the channel region inversion layer is formed, at both ends in the channel width direction 226, in order to avoid formation of the inversion layer via the gate oxide film by the gate electrode extending there, both ends in the channel width direction are formed. Next, ion implantation at a higher concentration than the concentration in the channel region is performed.

Next, as shown in FIG. 17D, wet oxidation is performed at a temperature of 800 ° C. for a time of about 21 minutes to form a groove 42.
The bottom surface 413b and the flat surface 417a exposed at the bottom of
The oxide film 427 serving as a channel injection protection film is formed to a thickness of 1
It is formed about 00 °. At this time, impurities contained in side wall oxide film 418 diffuse into inner surface portions 423b and 423a of the groove in contact with side wall oxide film 418, and LDD region 4
07 and 408 are formed. However, after this, LDD
Since there is a step of diffusing the region, the junction depth of the LDD region is not determined in this step.

Next, channel injection is performed to form the active layer 41.
A P-type channel region 409 is formed in a portion corresponding to a portion between the side walls 418 of the two. In this channel implantation, boron ions are implanted at an implantation energy of about 15 keV and an implantation amount of 1 ×
Inject at about 10 ¹² cm ^{-2 and} 7 to prevent channeling
Rotational injection or step injection is performed at an injection angle of about degrees. After that, the injection protection film 427 is removed.

Next, as shown in FIG. 17E, wet oxidation is performed at a temperature of 800.degree. C. for a time of about 21 minutes to form a gate oxide film 41 having a thickness of about 100.degree.
5 is formed. At this time, the impurities contained in the sidewall oxide film 418 are diffused, so that the LDD regions 407 and 408 are diffused.
Becomes deeper. However, since there is a step of diffusing the LDD region after this, the junction depth of the LDD region is not determined in this step.

Next, polysilicon (not shown) containing impurities is grown thereon with good uniformity by the LPCVD method, and the trenches 424 between the side wall insulators 418 are filled with polysilicon and substantially flat. Polysilicon is deposited to a thickness of about 2000-6000 ° so as to obtain a surface. Next, anisotropic etching with a high selectivity is performed on the oxide film, and the polysilicon is entirely etched.
A portion of the polysilicon is placed in the trench 424 to form the gate electrode 41.
Leave as 6. At this time, since the polysilicon and the source / drain regions are separated by the impurity-containing oxide film 418, over-etching is performed until the polysilicon is completely insulated. However, when the silicon surface of the source / drain region is etched, the surface may be roughened and the contact resistance may be increased. For this reason, in the case of over-etching, it is necessary to switch to anisotropic etching having a higher selectivity to the oxide film.

In this way, the gate electrode 416 is
24 can be formed in a self-aligned manner. Thus, a photolithography step requiring strict alignment can be omitted, and the step can be simplified.

Next, as in the second embodiment, photolithography is performed to form an injection protection resist for forming high-concentration source / drain regions (see FIG. 21E). After that, ion implantation is performed to form N-type high-concentration source / drain regions 405 and 406. In this ion implantation, arsenic ions are implanted at an implantation energy of about 40 keV and an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , and rotational implantation or step implantation is performed at an implantation angle of about 7 ° to prevent channeling. Next, the high concentration source / drain regions 405,
To activate 406, an activation anneal at temperature 80
Perform at 0 ° C. for about 10 minutes. At this time, the sidewall oxide film 418
The impurities contained in the LDD region 4
07 and 408 become deeper. After that, since there is no diffusion step, the junction depth of the LDD region is determined in this step. In this embodiment, the final junction depth of the LDD regions 407 and 408 is about 300 ° from the contact surface with the sidewall oxide film 418. Thus, the silicon substrate 4
Based on the shape of the groove 423 (see FIG. 16A) first formed on the surface of the semiconductor device 17, the LDD regions 407 and 408 are completely left-right symmetrically self-aligned via the sidewall oxide film 418.
Can be formed.

After that, the well-known interlayer film forming step and wiring forming step are performed to complete the field effect transistor.

As described above, the buried oxide film forming step
The LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step can all be performed in a self-aligned manner with respect to the groove 423.
A field effect transistor completely symmetrical in the source / drain direction can be manufactured.

Since the manufactured field-effect transistor has a symmetric structure between the source 403 and the drain 404,
The present invention can also be applied to a circuit that requires symmetry such that the source 403 and the drain 404 are interchanged and operated. Also, during operation, the active region 40 due to the potential of the gate 416
9 and 412, the extension of the depletion layer in the channel direction is limited by the insulator region 419, so that the component of the gate potential that extends the depletion layer into the active regions 409 and 412 is reduced. Only channel region 409
The components that form the inversion layer increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, between the source side LDD region 407 and the drain side LDD region 408 and the insulator region 419,
A portion (semiconductor region) of the active layer 412 where impurities are not diffused remains, and the channel region 409 and the silicon substrate 417 are connected via the semiconductor region.
And the transfer of electric charge becomes possible. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, the source region 403 and the drain region 40
4, a higher voltage can be applied by that much, and high-speed operation is possible.

The manufactured field-effect transistor has a so-called groove structure in which the gate 414 is buried in the groove, and the source / drain region has the gate electrode 4.
16 are present on the left and right sides of the substrate 16 via side wall insulators 418.
Generally, in such a field effect transistor having a groove structure, there is a problem of parasitic capacitance between a gate electrode and a source / drain region. However, in this embodiment, since the width of the sidewall insulator 418 is 0.1 μm, the parasitic capacitance between the gate electrode and the source / drain region can be sufficiently reduced. Thus, high-speed operation of the transistor can be performed.

In addition, since the active regions 409 and 412 are made of the original silicon substrate material instead of the epitaxial silicon layer, the active regions 409 and 41 with few defects are formed.
2 are provided. Therefore, the current driving capability can be further improved.

(Fifth Embodiment) A method for manufacturing a field effect transistor according to another embodiment will be described step by step with reference to FIGS.

First, as shown in FIG. 18A, photolithography is performed to form a resist 525 having an opening for forming a groove on the surface 517a of the P-type silicon substrate 517.
Is formed, and anisotropic silicon etching is performed using the resist 525 as a mask to form a groove 523 having a concave cross section in the silicon substrate 517. After the etching, the resist 525 is left for the next oxygen ion implantation step. Here, the width of the groove 523 having a concave cross section is set to be larger than the target gate length by about 0.20 μm. In this embodiment, the target gate length is set to 0.40 μm.
m, the width of the groove 223 is set to about 0.60 μm. Further, the depth of the groove 223 is set to about 0.15 μm.

Next, as shown in FIG. 18B, the silicon substrate 517 is formed using the resist 525 as a mask.
Above, oxygen ions are implanted at an implantation energy of about 180 keV and an implantation amount of about 3 to 4.5 × 10 ¹⁷ cm ⁻² . As a result, an oxygen ion implanted region 519 extending parallel to the bottom surface of the groove is formed at a depth level that is within the silicon substrate by a predetermined distance from the bottom surface of the groove 523. Here, the implantation amount of oxygen ions is lower than the implantation amount of 1.2 × 10 ¹⁸ cm ⁻² or more which has been practically used in the conventional SIMOX (separation by implanted oxygen) wafer. Since the amount is set to be small, the problem that many defects such as dislocations occur can be avoided. next,
As shown in FIG. 18C, after the resist 525 is removed, high-temperature annealing at a temperature of about 1300 ° C. is performed to recover the crystallinity and the oxygen ion implanted region 519.
By reacting the oxygen inside and the silicon substrate material, each of the oxygen ion implanted regions is changed to an insulator region (for the sake of simplicity, represented by the same reference numeral as the implanted region) 519. The silicon substrate material on the insulator region (buried oxide film) 519 becomes the active layer 512. Thereafter, in order to further reduce the thickness of the active layer 512, a temperature of about 800 to 1000 ° C.
Wet oxidation is performed for about 20 to 70 minutes,
The surface oxide film is entirely removed. Thereby, the active layer 512
And the thickness of the buried insulator 519 is about 1 μm. Instead of the wet oxidation, oxygen atoms may be introduced into the furnace by a dry or wet method at the same time as high-temperature annealing for recovering crystallinity to oxidize the silicon surface.

In the fourth embodiment, the resist is not used in the oxygen ion implantation step, and polishing is performed after the implantation to remove the silicon substrate material and the second insulator region existing in the region outside the groove. Roughness of the substrate surface may occur, and in a later step, contact failure between the source / drain and the metal contact may occur. In addition, dust due to polishing may adhere to the bottom surface of the groove and cause abnormal oxidation when forming a gate oxide film. However, in this embodiment, since the buried insulator is formed without using polishing, a good contact between the source / drain and the metal can be formed, and a good gate oxide film can be formed.

In this manner, the embedded insulator 519 extending below the groove 523 and parallel to the groove bottom can be formed completely symmetrically with the groove 523 of the silicon substrate 517 in a self-aligned manner. . Further, thanks to the groove 523, the LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step can be formed in a self-alignment manner. In addition, the photolithography step can be omitted in each of the steps, so that the steps can be simplified. However, as described later, an LDD region forming step,
In the source / drain region forming step, it is necessary to perform photolithography in order to prevent connection between the source and drain diffusion regions.

Next, the silicon substrate 517 corresponding to both sides of the groove 523 is formed by a normal element isolation LOCOS forming process.
LOCOS537 is formed on the surface of.

[0139] Then, by the LPCVD method, the bottom surface of the groove 523, on the side surface and the groove 523 outside of the flat surface 517a, the oxide film (here, containing an impurity, phosphorus 1 × 10 ²⁰ cm ^- was approximately ³ doped PSG Is uniformly deposited to a thickness of about 1000 °. The portion of the impurity-containing oxide film deposited in the groove 523 has a concave cross section reflecting the shape of the concave portion. Next, as shown in FIG. 19D, anisotropic etching is performed to remove the bottom surface 523b of the groove 523 and the flat surface 51 outside the groove in the impurity-containing oxide film.
The part on 7a is removed. Thus, the side walls 518, 518 of the remaining impurity-containing oxide film are formed on the side surfaces 513a, 513a of the groove 523. This side wall 518,
The gap between 518 constitutes a new groove 524 that is narrower than the original groove. Since the thickness of the side wall 518 is approximately equal to the thickness of the deposited film, the width of the new groove 524 is
It is accurately controlled by the CVD film thickness. When a gate electrode is formed so as to fill the new groove 524 in a later step, the width of the lower end of the new groove 524 becomes the gate length. In general, when a gate electrode is formed, a minimum gate length is defined by a physical limit of a minimum processing line width in a photolithography process. However, according to the present embodiment, by optimizing the aspect ratio of the width and the depth of the new groove 524, it is possible to form a gate length smaller than the physical limit of the minimum processing line width in the photolithography process.

Next, as described in the second embodiment,
In order to avoid connection between the LDD regions on the source side and the drain side, portions corresponding to both ends in the channel width direction of the side wall 518 connected in a rectangular frame shape in the plane pattern (see FIG. 20) are removed. In addition, when the channel region inversion layer is formed, at both ends in the channel width direction 226, in order to avoid formation of the inversion layer via the gate oxide film by the gate electrode extending there, both ends in the channel width direction are formed. Next, ion implantation at a higher concentration than the concentration in the channel region is performed.

Next, as shown in FIG. 19E, wet oxidation is performed at a temperature of 800.degree.
The bottom surface 513b and the flat surface 517a exposed at the bottom of
An oxide film 527 serving as a channel injection protection film is formed to a thickness of 1
It is formed about 00 °. At this time, impurities contained in side wall oxide film 518 diffuse into inner surface portions 523b and 523a of the groove in contact with side wall oxide film 518, and LDD region 5
07 and 508 are formed. However, after this, LDD
Since there is a step of diffusing the region, the junction depth of the LDD region is not determined in this step.

Next, channel implantation is performed to form the active layer 51.
A P-type channel region 509 is formed in a portion corresponding to between the side walls 518 of 2. In this channel implantation, boron ions are implanted at an implantation energy of about 15 keV and an implantation amount of 1 ×
Inject at about 10 ¹² cm ^{-2 and} 7 to prevent channeling
Rotational injection or step injection is performed at an injection angle of about degrees. After that, the injection protection film 527 is removed.

Next, as shown in FIG. 19 (f), wet oxidation is performed at a temperature of 800 ° C. for a time of about 21 minutes to form a gate oxide film 51 having a thickness of about 100 ° on the channel region 509.
5 is formed. At this time, the impurities contained in the side wall oxide film 518 are diffused, so that the LDD regions 507 and 508 are diffused.
Becomes deeper. However, since there is a step of diffusing the LDD region after this, the junction depth of the LDD region is not determined in this step. As described above, in this embodiment, since the buried insulator is formed without using polishing, a favorable gate oxide film can be formed.

Next, polysilicon (not shown) containing impurities is grown thereon with a uniform thickness by the LPCVD method, and the trench 524 between the side wall insulators 518 is filled with the polysilicon and substantially flat. Polysilicon is deposited to a thickness of about 2000-6000 ° so as to obtain a surface. Next, anisotropic etching with a high selectivity is performed on the oxide film, and the polysilicon is entirely etched.
A part of the polysilicon is placed in the trench 524 by the gate electrode 51.
Leave as 6. At this time, since the polysilicon and the source / drain regions are separated by the impurity-containing oxide film 518, over-etching is performed until the polysilicon is completely insulated. However, when the silicon surface of the source / drain region is etched, the surface may be roughened and the contact resistance may be increased. For this reason, in the case of over-etching, it is necessary to switch to anisotropic etching having a higher selectivity to the oxide film.

In this way, the gate electrode 516 is
24 can be formed in a self-aligned manner. Thus, a photolithography step requiring strict alignment can be omitted, and the step can be simplified.

Next, as in the second embodiment, photolithography is performed to form an injection protection resist for forming high-concentration source / drain regions (see FIG. 21E). Thereafter, ion implantation is performed to form N-type high-concentration source / drain regions 505 and 506. In this ion implantation, arsenic ions are implanted at an implantation energy of about 40 keV and an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , and rotational implantation or step implantation is performed at an implantation angle of about 7 ° to prevent channeling. Next, a high concentration source / drain region 505,
To activate 506, the activation anneal is performed at a temperature of 80.
Perform at 0 ° C. for about 10 minutes. At this time, the side wall oxide film 518
Is diffused, so that the LDD region 5
07 and 508 are deepened. After that, since there is no diffusion step, the junction depth of the LDD region is determined in this step. In this embodiment, the final junction depth of the LDD regions 507 and 508 is about 300 ° from the contact surface with the sidewall oxide film 518. Thus, the silicon substrate 5
Based on the shape of the first groove 523 (see FIG. 18A) formed on the surface of the semiconductor device 17, the LDD regions 507 and 508 are completely aligned bilaterally in a self-aligned manner via the sidewall oxide film 518.
Can be formed.

After that, the well-known interlayer film forming step and wiring forming step are performed to complete the field effect transistor.

As described above, the buried oxide film forming step
The LDD region forming step, the channel region forming step, the gate electrode forming step, and the source / drain region forming step can all be performed in a self-aligned manner with respect to the trench 523.
A field effect transistor completely symmetrical in the source / drain direction can be manufactured.

The manufactured field-effect transistor has a symmetric structure between the source 503 and the drain 504.
The present invention can be applied to a circuit that requires symmetry such that the source 503 and the drain 504 are interchanged and operated. Also, during operation, the active region 50 due to the potential of the gate 516
Since the extension of the depletion layer into the active regions 509 and 512 is limited by the insulator region 519 throughout the channel direction, the component of the gate potential that extends the depletion layer into the active regions 509 and 512 is reduced. Only channel region 509
The components that form the inversion layer increase. Therefore, the S factor of the transistor can be improved, the sub-threshold characteristic that determines the switching characteristic can be improved, and high driving capability can be realized. Further, between the source side LDD region 507 and the drain side LDD region 508 and the insulator region 519,
Since a portion (semiconductor region) of the active layer 512 where impurities are not diffused remains, and the channel region 509 and the silicon substrate 517 are connected via the semiconductor region, the active regions 509 and 512 and the silicon substrate 517 are connected.
And the transfer of electric charge becomes possible. Therefore, a high drain withstand voltage can be realized without the substrate floating effect. As a result, the source region 503 and the drain region 50
4, a higher voltage can be applied by that much, and high-speed operation is possible.

The manufactured field-effect transistor has a so-called groove structure in which the gate 514 is embedded in the groove, and the source / drain region has the gate electrode 5.
16 are provided on the left and right sides of the substrate 16 via a side wall insulator 518.
Generally, in such a field effect transistor having a groove structure, there is a problem of parasitic capacitance between a gate electrode and a source / drain region. However, in this embodiment, since the width of the sidewall insulator 518 is 0.1 μm, the parasitic capacitance between the gate electrode and the source / drain region can be sufficiently reduced. Thus, high-speed operation of the transistor can be performed.

Moreover, since the active regions 509 and 512 are made of the original silicon substrate material instead of the epitaxial silicon layer, the active regions 509 and 51 having few defects are formed.
2 are provided. Therefore, the current driving capability can be further improved.

In the above embodiment, mainly N
Although the case of the MOS transistor has been described, it is needless to say that the present invention is not limited to this. The present invention provides a PMO
The same applies to S transistors and CMOS transistors.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a field-effect transistor according to one embodiment of the present invention.

FIG. 2 is a diagram showing a modification of the field-effect transistor of FIG.

FIG. 3 is a diagram showing a modification of the field-effect transistor of FIG.

FIG. 4 is a diagram showing a modification of the field-effect transistor of FIG.

FIG. 5 is a diagram showing an example in which the field effect transistors of FIGS. 3 and 4 are provided on the same substrate.

FIG. 6 is a process chart showing a method for manufacturing a field-effect transistor according to one embodiment of the present invention.

FIG. 7 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 8 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 9 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 10 is a process chart showing a method for manufacturing the field-effect transistor.

FIG. 11 is a process chart showing a method for manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 12 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 13 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 14 is a process chart showing a method for manufacturing the field-effect transistor.

FIG. 15 is a process chart showing a method for manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 16 is a process chart showing a method for manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 17 is a process chart illustrating a method for manufacturing the field effect transistor.

FIG. 18 is a process chart showing a method for manufacturing a field-effect transistor according to another embodiment of the present invention.

FIG. 19 is a process chart showing a method for manufacturing the field effect transistor.

FIG. 20 is a diagram illustrating pattern processing at both ends in the channel width direction in the manufacturing method according to the embodiment of the present invention.

FIG. 21 is a diagram illustrating pattern processing before source / drain implantation in a manufacturing method according to an embodiment of the present invention.

FIG. 22 is a diagram showing a cross-sectional structure of a conventional SOI type MOSFET.

FIG. 23 is a diagram showing a cross-sectional structure of a conventional MOSFET having an insulator region below the center of a channel region.

FIG. 24 is a process chart showing a method for manufacturing a conventional pseudo SOI MOSFET.

[Explanation of symbols]

101, 217, 317, 417, 517, 717 Silicon substrate 102, 219, 319, 419, 519, 719 Buried oxide film 103, 203, 303, 403, 503, 703 Source region 104, 204, 304, 404, 504, 704 Drain regions 105, 205, 305, 405, 505, 705 High-concentration source regions 106, 206, 306, 406, 506, 706 High-concentration drain regions 107, 207, 307, 407, 507, 707 Source-side LDD regions 108, 208, 308, 408, 508, 708 Drain side LDD regions 109, 209, 309, 409, 509, 709 Channel regions 112, 412, 512, 712 Active layers 213, 313 Epitaxial silicon layers 114, 214, 414, 514 Over preparative 115,215,315,415,515,738 gate insulating film 116,216,316,416,516,716 gate electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takayuki Ogura 2-31-19 Shiba, Minato-ku, Tokyo Inside (72) Inventor Ikuo Fujiwara 2-31-19 Shiba, Minato-ku, Tokyo Communication and Broadcasting Organization (72) Inventor Tetsuro Endo 2-31-19 Shiba, Minato-ku, Tokyo Communication and Broadcasting Corporation Inside (72) Inventor Fujio Masuka 2-31-19 Shiba, Minato-ku, Tokyo Communication and Broadcasting Corporation F-term (reference) 5F040 DA00 DA01 DA18 DA21 DB03 DC01 EB12 EC07 EC20 EF02 EK05 EM01 EM02 EM03 FC00 FC06 FC11 FC15 FC21 FC28 5F110 AA13 CC02 DD01 GG02 GG12

Claims (9)

[Claims] 1. A field effect transistor comprising: a source region and a drain region provided separately from each other on a semiconductor substrate or a well region; and a gate covering a channel region between the source region and the drain region. An insulating region extending from a position below the source region to a position below the drain region from below the source region to below the drain region, on the semiconductor substrate or the well region; A semiconductor region having the same conductivity type as that of the channel region is provided between the insulator region and the channel region, and the channel region and the semiconductor substrate or the well region are connected via the semiconductor region. Characteristic field effect transistor. 2. The field effect transistor according to claim 1, wherein the second and third insulating layers are located at positions separated from an insulator region passing below the channel region and in contact with lower portions of the source region and the drain region, respectively. A field-effect transistor having a body region. 3. The field effect transistor according to claim 1, wherein a depletion layer reaches a lower insulator region from the gate electrode side according to a potential of the gate electrode. Field-effect transistor. 4. The high-concentration field-effect transistor according to claim 1, wherein said source region and said drain region have a certain junction depth and are provided at respective sides of said gate. And an LDD region having a junction depth shallower than the high-concentration region and extending from a gate-side end of the high-concentration region to a position immediately below the gate. An electric field effect wherein both ends are stopped below the source side LDD region and the drain side LDD region, respectively, and the level of the upper surface of the insulator region is at a level shallower than the junction depth of each of the high concentration regions. Transistor. 5. A method for manufacturing a field-effect transistor according to claim 1, wherein the SOI wafer has a base silicon substrate, an insulator layer, and a single-crystal silicon layer in this order. Forming a plurality of grooves at predetermined intervals from the single crystal silicon layer to the base silicon substrate in the SOI wafer at predetermined intervals to separate the insulator layer into a plurality of insulator regions; Performing a step of filling each groove with epitaxial silicon, and polishing the surface of the SOI wafer so that the surface of the single-crystal silicon layer and the surface of epitaxial silicon in the groove are flush with each other. Flattening step, on the single crystal silicon layer present on each of the insulator layers, via a gate insulating film Forming a over gate electrode, the impurities on the surface of the monocrystalline silicon layer using the gate electrode as a mask annealed with ion implantation,
Forming a source region and a drain region extending from a side of the gate electrode to a position directly below the gate electrode and above the insulator layer. 6. The method according to claim 5, wherein in the step of forming the plurality of grooves and separating the insulator layer into a plurality of insulator regions, the insulating layer passes below the channel region. The distance between the grooves is set so as to form a body region and second and third insulator regions that are separated from the insulator region and that are to be disposed below the source region and the drain region, respectively. A method for manufacturing a field effect transistor, comprising: 7. A step of depositing an insulator over the entire surface of a semiconductor substrate having a groove with a concave cross section on the surface and embedding the groove with an insulator; and polishing the front surface of the semiconductor substrate to form the semiconductor substrate. Flattening the surface of the insulator so as to be flush with the surface of the insulator in the groove; and selectively etching the surface side portion of the insulator with respect to the semiconductor substrate to form a bottom portion of the groove. A step of leaving an insulator having a flat surface, and performing epitaxial growth to grow a single-crystal silicon layer having a substantially uniform thickness and a concave cross section at least along the insulator surface and the silicon sidewall in the groove. A step of depositing an insulator containing impurities in a substantially uniform thickness in a concave cross section along at least the inner surface of the recess formed by the single crystal silicon layer; and anisotropically etching the insulator, Insulator with concave cross section Removing the bottom and exposing the single crystal silicon layer in the gap between the remaining insulator side walls; and performing oxidation to form a gate oxide film on the surface of the single crystal silicon layer exposed in the gap. Forming at least a part of a source region and a drain region by diffusing an impurity in the insulator side wall into an inner surface portion of the single crystal silicon layer in contact with the insulator side wall; A method for manufacturing a field effect transistor, comprising a step of forming a gate electrode so as to fill a gap between body side walls. 8. A semiconductor substrate having a groove having a concave cross section on its surface is implanted with oxygen ions at a predetermined implantation energy, and the depth of the groove is reduced to a depth level which is a predetermined distance from the bottom of the groove into the semiconductor substrate. Forming a first oxygen ion implanted region extending parallel to the bottom surface, and forming a second oxygen ion implanted region at a depth level outside the groove and above a lower portion of the groove; Perform the first, the oxygen in the second oxygen ion implantation region and react with the semiconductor substrate material, the first,
A step of changing each of the second oxygen ion implanted regions into a first and a second insulator region, and polishing the surface side of the semiconductor substrate to remove the second insulator region while leaving a lower portion of the groove. Removing; depositing an insulator containing impurities in a concave cross section with a substantially uniform thickness along at least the inner surface of the remaining groove; anisotropically etching the insulator to form the cross section Removing the bottom of the concave insulator and exposing the bottom surface of the groove in the gap between the remaining insulator side walls; and performing oxidation to form a gate oxide film on the bottom surface of the groove exposed in the gap. Forming a source region and a drain region by diffusing an impurity in the insulator side wall into an inner surface portion of the groove in contact with the insulator side wall; To fill the gap between Method of manufacturing a field effect transistor comprising a step of forming a gate electrode. 9. A step of forming a resist pattern having an opening corresponding to the groove by performing photolithography on a semiconductor substrate having a groove having a concave cross section on the surface; and forming a resist pattern on the surface of the semiconductor substrate using the resist pattern as a mask. Implanting oxygen ions at a predetermined implantation energy to form an oxygen ion implanted region extending in parallel with the bottom surface of the groove at a depth level that enters the semiconductor substrate by a predetermined distance from the bottom surface of the groove; Annealing to react oxygen in the oxygen ion implanted region with the semiconductor substrate material to change the oxygen ion implanted region into an insulator region; and, after removing the resist pattern, at least the inner surface of the groove. A step of depositing an insulator containing impurities in a concave shape with a substantially uniform thickness along the line, and anisotropically etching the insulator to form the cross section. Removing the bottom of the insulator in the shape of a groove and exposing the bottom surface of the groove in the gap between the sidewalls made of the remaining insulator; and performing oxidation to form a gate oxide film on the bottom surface of the groove exposed in the gap. Forming a source region and a drain region by diffusing an impurity in the insulator side wall into an inner surface portion of the groove in contact with the insulator side wall; Forming a gate electrode so as to fill a gap therebetween.