JP2002009179A - Non-volatile semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance charge injection efficiency by improving retention characteristics and charge retention characteristics. SOLUTION: A non-volatile semiconductor storage device has a semiconductor layer supported on a semiconductor board or a board, an insulation layer formed on the surface area CH and including in the inside a charge accumulation layer FG in which charge is injected from a board side, and a control electrode on the insulation film. It has a bottom insulation film BTM including an area different in nitrogen concentration in the film thickness direction between the semiconductor surface area CH of the board side and the charge accumulation layer FG. The nitrogen concentration distribution in the film thickness direction has the maximum value, and the peak is unevenly distributed on the board side from the film thickness center of the bottom insulation film BTM. Furthermore, nitrogen concentration is low in the neighborhood of an interface with the semiconductor surface area CH, and increases toward the inside of the bottom insulation film. The nitrogen concentration distribution of the bottom insulation film BTM exposes the semiconductor surface area CH to plasma containing nitrogen atoms, and is obtained by nitriding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and programmable memory (EEPROM) such as a flash memory.
mable Read Only Memory), a nonvolatile semiconductor memory device having an improved bottom insulating film functioning as an energy barrier interposed between the semiconductor surface region on the substrate side and the charge storage layer, It relates to the manufacturing method.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory is expected as a large-capacity and small-sized information recording medium. The nonvolatile memory transistor as the storage element has a structure in which an insulating film (a gate insulating film) including a charge storage layer and a gate electrode are stacked on a semiconductor surface region (a channel forming region) on a substrate side. Examples of the charge storage layer include a floating gate made of a single polysilicon, and a nitride film capable of increasing a trap density at an interface with an oxide film to form a large number of carrier traps.

In a nonvolatile semiconductor memory, a high electric field of the order of 10 MeV / cm or more is applied to a lowermost film (hereinafter, referred to as a bottom insulating film) of a gate insulating film for a high-speed writing operation or erasing operation, thereby causing a charge. The charge (electrons or holes) are injected and released into the storage layer. When the charge is stored in the charge storage layer, the threshold voltage of the memory transistor changes, thereby recording information. At the time of erasing, the charge is extracted to the substrate side, or a charge of the opposite polarity is injected into the charge storage layer. On the other hand, at the time of reading information, the change in threshold voltage is converted into a change in drain conductivity due to a difference in channel conductivity or a change in drain potential due to ON / OFF of the channel.

In the non-volatile memory transistor operating as described above, the material, thickness, film quality, and formation method of the bottom insulating film interposed between the charge injection layer and the substrate side for injecting / ejecting the charge are written and written. This is important because it greatly affects the erasing characteristics or the charge retention characteristics. Conventionally,
The bottom insulating film is formed by thermally oxidizing a Si substrate in order to minimize the interface density between the conduction channel and the insulating film and to enable practically usable writing / erasing of about 1,000,000 times. SiO ₂ films have been used.

[0005]

In a conventional flash memory or EEPROM, when rewriting and erasing operations are repeated many times, electrons or holes are trapped in a thermally oxidized silicon film (bottom insulating film) and a threshold voltage is reduced. It has been known that voltage fluctuations occur. In this regard, for example, (Endo, Masukaoka, IEICE C-III, vol.J79-C-II, N
o.7 p.333).

[0006] The damage in the tunnel oxide film and the resulting increase in the number of traps thus caused not only cause the threshold voltage fluctuation after repetitive operation, that is, the deterioration of the retention characteristic, but also the bottom insulation. Increase the leakage current through the film. As a result, it is known that the charge retention characteristic of the memory transistor deteriorates (for example, S. Sato et al., Proc. IEEE 1995 Int.
Conference on Microelectronic Test Structures, 8,
97 (1995)).

On the other hand, in order to improve the charge retention characteristics, it is generally sufficient to increase the thickness of the bottom insulating film. However, this lowers the charge injection efficiency and makes low-voltage operation difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the charge injection efficiency while keeping the fluctuation of the threshold voltage and the deterioration of the charge retention characteristics after repeating the write / erase operation, or maintaining the energy barrier necessary for the charge retention. And a method of manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device formed on a semiconductor substrate or a semiconductor layer supported by the substrate and a surface region of the semiconductor substrate or the semiconductor layer. A non-volatile semiconductor memory device having an insulating film including a charge storage layer into which electric charges are injected from a substrate side, and a control electrode on the insulating film, wherein the semiconductor surface region on the substrate side and the electric charge A bottom insulating film including a region having a different nitrogen concentration in the film thickness direction is provided between the storage layer and the storage layer. The bottom insulating film is made of, for example, silicon nitride SiN.
_{One of x} (x> 0) and silicon oxynitride SiO _x N _y (x, y> 0) is formed as a main constituent material.

[0010] Preferably, the nitrogen concentration distribution of the bottom insulating film has the following characteristics. First, it has a maximum value in the thickness direction of the bottom insulating film. For example, the bottom insulating film tends to have a single maximum value from the lower surface on the substrate side to the upper surface in contact with the charge storage layer. Second, the center of the nitrogen concentration distribution in the thickness direction of the bottom insulating film is unevenly distributed on the substrate side. In particular, when it has the single maximum value, its peak is unevenly distributed on the substrate side from the center of the thickness of the bottom insulating film. Third, the nitrogen concentration sharply increases from near the interface with the semiconductor surface region on the substrate side toward the inside of the bottom insulating film.

In this nonvolatile semiconductor memory device, at the time of writing and erasing, for example, channel hot electron injection, electron injection by direct tunneling, injection of hot electrons or hot holes using an inter-band tunnel current, and channel injection using FN tunneling Electron injection from the entire surface is used. In the nonvolatile semiconductor memory device of the present invention, since the bottom insulating film of the memory element through which electric charges pass during the operation has the nitrogen concentration distribution having the above characteristics, the characteristics and reliability are improved as follows.

That is, as related to the first and second features, the energy barrier on the substrate side is reduced while maintaining the energy barrier on the charge storage layer side. This is because as the nitrogen concentration increases, the energy barrier decreases. Therefore, the charge injection efficiency can be increased without lowering the charge retention characteristics. In addition, the required charge injection efficiency can be ensured even if the bottom insulating film is thickened, so that the charge retention characteristics are improved accordingly.

On the other hand, the present inventors have experimentally confirmed that such a nitrogen concentration distribution significantly reduces the leak current. This is because when the bottom insulating film is a silicon nitride film or a silicon oxynitride film, it contains a silicon-nitrogen bonding group having excellent current stress resistance. Therefore,
Compared with the conventional case in which the nitrogen concentration distribution is substantially uniform in the thickness direction of the bottom insulating film, a significant improvement in the leakage current is achieved. In addition, retention characteristics relating to threshold voltage fluctuation after repeated writing and erasing are improved.

[0014] In connection with the first and third features, since nitrogen atoms are scarcely present near the interface with the substrate, the substrate interface state and the occurrence of nitrogen atom scattering at the interface are suppressed to a low level. I have. This causes a small change in the transconductance of the memory element and a small change in the threshold voltage, in addition to the leakage reduction.

It is to be noted that the nonvolatile semiconductor memory device according to the present invention uses a silicon nitride-based insulating film such as a so-called MONOS type or MNOS type as a charge storage layer, or a non-silicon nitride-based insulating film containing many charge traps. A charge storage layer, such as a so-called FG type, a single layer of polycrystalline silicon as a charge storage layer, a fine polycrystalline silicon, such as a so-called nanocrystalline type, or metal particles embedded in an insulating material. The present invention can be applied to any device having a charge storage layer.

In particular, in a nonvolatile semiconductor memory device using a silicon nitride-based or other insulating film as a charge storage layer, a non-volatile semiconductor memory device is provided in a region in the insulating film centered on the charge storage layer and in a surface facing the surface of the semiconductor region. In addition, charge traps are distributed as storage means for storing the storage charge discretized in the film thickness direction.
The charge storage layer is formed of an insulating film having Frenkel-Pool conduction characteristics, for example, silicon nitride SiN _x (x> 0), silicon oxynitride SiO _x N _y (x, y> 0), and aluminum oxide AlO _x (x
> 0) and tantalum oxide TaO _x (x> 0). In particular, when the charge storage layer is made of silicon nitride SiN _x (x> 0), it preferably contains a silicon-hydrogen bonding group having a higher density in the upper region on the control electrode side than in the lower region on the substrate side. This is because it is preferable that the center of the charge trap is far from the substrate for holding the charge.

A method of manufacturing a nonvolatile semiconductor memory device according to a second aspect of the present invention includes a charge storage layer into which charges are injected from the substrate, on a semiconductor substrate or a semiconductor layer supported by the substrate. An insulating film, a method for manufacturing a nonvolatile semiconductor memory device by laminating a control electrode on the insulating film, when forming the insulating film on the semiconductor substrate or semiconductor layer, the first bottom insulating film, The surface of the semiconductor substrate or the semiconductor layer is exposed to plasma containing nitrogen atoms, and the semiconductor surface is directly nitrided.

In forming the silicon nitride film as the bottom insulating film, it is preferable to use nitrogen N ₂ or ammonia NH _3.
The semiconductor substrate or the semiconductor layer is exposed to the plasma while introducing the raw material gas. In forming a silicon oxynitride film as the bottom insulating film, it is preferable to use nitrogen N _2.
Or ammonia NH ₃ and nitric oxide NO or N ₂ O
The semiconductor substrate or the semiconductor layer is exposed to the plasma while introducing a mixed gas of the above as a source gas.

In forming these bottom insulating films, the plasma is preferably generated in an AC electromagnetic field within a frequency range from 5 MHz to 5 GHz, and the semiconductor substrate or the semiconductor layer is exposed to the plasma in the AC electromagnetic field. At this time, in the present invention, preferably, plasma is generated, and the generated plasma is guided to a spatially distant place, and the semiconductor substrate or the semiconductor layer is exposed to plasma in which the number of charged ions is reduced by the induction. Good. This method is a so-called remote plasma method, in which the number of charged ions in the plasma flow reaching the wafer forming the nonvolatile semiconductor memory device is reduced, so that damage to the substrate is reduced. As another method of providing the same effect, the semiconductor substrate or the semiconductor layer may be exposed to plasma in which the number of charged ions is reduced by the transmission of the grid electrode after the generation of the plasma.

On the other hand, when forming a silicon nitride film as the above-mentioned charge storage layer on the formed bottom insulating film, it is preferable to start forming the silicon nitride film under a condition that silicon-hydrogen bonding groups are relatively reduced. Then, it is preferable to switch to a condition in which the number of silicon-hydrogen bonding groups is relatively increased during the formation. For example,
In the switching of the film forming conditions, the mixing ratio of the plurality of source gases is changed. Alternatively, the film forming conditions are switched by changing the type of the source gas to be mixed.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a bottom insulating film having the above-described nitrogen concentration distribution can be easily formed. Further, the charge traps in the charge storage layer are densely formed on the upper side, and the charge retention characteristics are improved.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking as an example the case where an n-channel type memory transistor is used as a storage element. Note that a p-channel memory transistor is realized by reversing the impurity conductivity type in the following description.

First Embodiment This embodiment relates to a nonvolatile semiconductor memory device having a so-called FG (Floating Gate) type memory transistor. FIG. 1 shows a cross-sectional structure of the nonvolatile memory transistor according to the first embodiment.

This memory transistor is, for example, a semiconductor substrate such as a p-type silicon wafer, a p-well formed on the inner surface of the semiconductor substrate, or a p-type SOI substrate isolation structure.
It is formed on a mold silicon layer (hereinafter, simply referred to as a substrate SUB). If necessary, a LOCOS (Local Oxidation of Silicon) method or an S
An element isolation insulating layer ISO formed by a TI (Shallow Trench Isolation) method or the like is formed. The surface portion of the substrate where the element isolation insulating layer ISO is not formed becomes an active region in which an active element including the memory transistor is formed.

On the active region, a so-called gate insulating film (for convenience, referred to as a bottom insulating film BTM), a floating gate FG, an inter-gate insulating film INTG, and a gate laminated film structure including a control gate CG are formed. I have. The control gate CG itself or an upper wiring layer connected to the control gate CG forms a word line of the memory cell array.

The bottom insulating layer BTM has a thickness of, for example, 1 nm to
Silicon nitride SiN having a thickness of about 20 nm_x (x> 0)
Or silicon oxynitride SiO_x N_y (x, y> 0).
The formation of the bottom insulating film BTM will be described later in detail,
Nitrogen N_Two Or ammonia NH_Three Or an acid
Nitrogen N_Two Ionized gas (P) added with O or NO
Exposing the Si active region to the
It is formed by directly nitriding or oxynitriding the region surface. charge
The floating gate FG as a storage layer is a p-type or
Is a polycrystalline silicon film made conductive by introducing n-type impurities.
It becomes. The inter-gate insulating film INTG is, for example, ONO (O
xide-Nitride-Oxide) film or single-layer silicon oxide film
And the film thickness is about 3 nm to 20 nm. Conte
The roll gate CG is formed by a CVD method and is not highly concentrated.
Pure doped polycrystalline silicon or polycrystalline silicon
Element and WSi on it_2,TiN, TaSi _2,TiSi_2,T
It is composed of a laminated film of i, W, Cu, Al, Au and the like.

Two source / drain impurity regions S / D having a so-called LDD (Lightly Doped Drain) structure are formed apart from each other on the inner surface of the silicon active region on both sides of the gate laminated structure. Depending on the direction of voltage application during operation,
One of the two source / drain impurity regions S / D functions as a source, and the other functions as a drain. On both sides of the gate laminated film structure, so-called sidewall SW
Is formed. An active region located immediately below the sidewall SW, by n-type impurity is introduced shallow at relatively low concentrations, n of the source and drain impurity regions S / D ^- impurity region (LDD region) is formed. Further, by using the sidewall SW as a self-aligned mask and introducing n-type impurities deeply at a relatively high concentration on both outer sides thereof, an n ⁺ impurity region which is a main component of the source / drain impurity region S / D is formed. ing. Note that an active region portion between the two source / drain impurity regions S / D is a channel formation region CH of the memory transistor.

The memory transistor according to the present embodiment is characterized by the nitrogen concentration distribution of the bottom insulating film BTM. FIG. 2 is a graph showing a nitrogen concentration distribution in the direction perpendicular to the substrate with the bottom insulating film BTM at the center. Bottom insulating film BTM in this illustrated example, has a single maximum value of the nitrogen concentration C _N in the film thickness direction. That is, the nitrogen concentration on the interface side with the channel formation region is extremely low, the nitrogen concentration rapidly increases toward the inside of the bottom insulating film BTM, and reaches the peak point P. Decrease. Such a nitrogen concentration distribution strongly depends on the film formation method.

Hereinafter, a method of manufacturing a memory transistor including the method of forming the bottom insulating film will be described with reference to the drawings. Here, FIGS. 3 to 6 are cross-sectional views of the memory transistor according to the first embodiment in the process of being manufactured. As shown in FIG. 3, an element isolation insulating layer ISO is formed on a substrate SUB by a LOCOS method or an STI method. Further, if necessary, impurity doping for adjusting the threshold voltage of the memory transistor is performed by, for example, an ion implantation method.

As shown in FIG. 4, a bottom insulating film BTM is formed on at least the Si active region. In the formation of the bottom insulating film BTM, the surface of the Si active region is
Alternatively, the surface of the Si active region is directly nitrided or oxynitrided by exposure to a plasma containing both oxygen atoms and nitrogen atoms. At this time, any plasma damage is introduced into the Si active region. This plasma damage can be recovered by annealing later, but it is desirable to suppress the introduction of plasma damage during film formation as much as possible.

To form the bottom insulating film BTM while suppressing the introduction of plasma damage as described above, for example, E
A plasma generation chamber for generating plasma in an AC electromagnetic field (5 MHz to 5 GHz) by CR (Electron Cyclotron Resonance) is spatially separated from a processing chamber for processing a wafer.
It is preferable to use a method in which the plasma flow from the plasma generation chamber is guided to the processing chamber by electromagnetic induction and irradiated onto the wafer. This method is called a remote plasma method, in which charged ions N ⁺ and O ⁺ contained in a large amount of plasma at the time of generation are reduced during the induction process, and the ratio of neutral active atoms N and O is increased when the ions reach the wafer. . Therefore, in this method, substrate damage due to atoms having extremely high irradiation energy can be effectively suppressed.

As another method of forming the bottom insulating film BTM while suppressing the introduction of plasma damage, a method in which generated plasma is transmitted through an electrode grid to neutralize charged ions to some extent and then used for wafer processing. There is. Also in this method, atoms with extremely high irradiation energy are reduced, and the damage to the substrate due to this is effectively suppressed.

When a oxynitride film or a nitride film is formed on a silicon substrate by the remote plasma method, it is already known that a nitrogen concentration distribution having a maximum value can be obtained in the film (E. Ploura et al., Ap
plied Physics Letters, 49,97 (1996)). Such a nitrogen concentration distribution occurs because the diffusion coefficient of nitrogen in Si is
It is thought that this is due to a decrease with increasing nitrogen concentration in the atmosphere.

The inventor of the present invention has found that when a nitride film or an oxynitride film having such a nitrogen concentration distribution is applied to a bottom insulating film in which charges are tunneled in a memory transistor, characteristics and quality (lifetime) can be greatly improved. Found by experiment. In this experiment, (100) of a p-type silicon wafer (impurity concentration 1.5 × 10 ¹⁶ cm ⁻³ ) was used.
The surface was treated with an ECR plasma device. At this time, N ₂ O was introduced as a gas to be introduced into the processing chamber (chamber) at a flow rate of 50 sccm, and the pressure in the chamber was set at 0.8 mTorr. And a frequency of 2.45 GHz and a power of 300 W
A plasma containing nitrogen atoms and oxygen atoms was generated in an alternating current electromagnetic field, and a silicon wafer kept at a substrate temperature of 150 ° C. was exposed to this plasma to form a silicon oxynitride film.

After forming the silicon oxynitride film, a memory transistor having the structure shown in FIG. 1 was formed, and the current-voltage characteristics were measured. Fowler-Nord obtained from the current-voltage characteristics results
The heim (FN) plot is shown in FIG. The vertical axis of FIG.
og (J / E ² ), and the horizontal axis is -1 / E. Here, J represents the current density, and E represents the electric field strength in the thermal silicon oxide film or the silicon oxynitride film. Here, the silicon oxynitride film thickness was determined to be 3.5 nm by a spectroscopic ellipsometry method. FIG. 7 shows the current of a silicon dioxide film (thickness: 6.7 mm) produced by thermally oxidizing (normal pressure, substrate temperature: 850 ° C.) a substrate surface similar to the substrate used for forming the above-described oxynitride film. The FN plot of the voltage characteristics is also shown. From FIG. 7, it can be seen that the current flowing through the silicon oxynitride film at the same electric field is about 1/10 of the current flowing through the silicon dioxide film even though the silicon oxynitride film is thinner. Further, various experiments including this experiment revealed that the reduction of the leak current had a strong correlation with the nitrogen concentration distribution having the maximum value as shown in FIG.

[0036] Given this experimental result, as one preferred embodiment in FIG. 4, by a remote plasma method, a nitrogen oxide nitride, N ₂ O, alternating electromagnetic field (13.56 MHz) with a gas NO or N ₂ Within 1 nm thickness
It is formed to a thickness of about 20 nm. In a conventional FG type memory transistor using a thermally oxidized silicon film as a tunnel film, the tunnel film thickness is 8 n
Although the limit is about m, the present embodiment has an advantage that the bottom insulating film BTM can be made thinner than 8 nm.

Next, as shown in FIG. 5, a conductive layer serving as a floating gate FG, an inter-gate insulating film INTG and a conductive layer serving as a control gate CG are sequentially formed on the bottom insulating film BTM. In the formation of the conductive layer (polycrystalline silicon) to be the floating gate FG, monosilane (SiH ₄ ) and dichlorosilane (SiCl ₂ H) are used.
₂ ), a CVD method using a gas containing silicon atoms such as tetrachlorosilane (SiCl ₄ ) as a raw material, or a sputtering method using a polycrystalline silicon target (PC
D) is used. Here, the CV with a substrate temperature of 650 ° C.
D to make polycrystalline silicon, for example, 50 nm to 200 nm.
Deposit about nm. Impurities are introduced into the polycrystalline silicon by the ion implantation after the film formation process or after the film formation to make the polysilicon conductive. Next, an inter-gate insulating film INTG of 3 nm to
A silicon dioxide film having a thickness of about 20 nm was deposited on polycrystalline silicon to be a floating gate FG. This deposition is performed at a substrate temperature of 600 ° C. using a gas containing silicon atoms such as SiH ₄ , SiCl ₂ H ₂ , trichlorosilane (SiCl ₃ H), and SiCl ₄ and a gas containing nitrogen oxide N ₂ O and oxygen O _2. An 800 ° C. CVD method is used. Then, a polycrystalline silicon film and a metal thereon, a high melting point metal,
A laminated film with a low-resistance layer made of an alloy containing the metal silicide is formed. Examples of the material of the low resistance layer include copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), tungsten silicide (WSi ₂ ), tantalum silicide (TaSi ₂ ),
Titanium nitride (TiN) or the like is used. The conductive film serving as the control gate CG is formed by CVD or P
It is formed to a thickness of about 50 nm to 200 nm by the VD method.

Although not particularly shown, dry etching resistance
Insulating film (eg, SiO 2 _Two ) By CVD
Then, the insulating film is processed into a gate electrode pattern.
Using this insulating film as a mask, anisotropic etching and
For example, RIE (Reactive IonEtching) is performed, and FIG.
As shown, the control gate CG, the gate insulating film
INTG, floating gate FG, bottom insulating film B
A gate laminated film made of TM is formed. Next, the gate
Using the laminated film as a self-aligned mask,
An n-type impurity is implanted at a low concentration on the surface of the exposed Si active region.
ON injection, n^- Impurity region (LDD region, n in the figure)^- 
) Are formed. In this ion implantation, for example,
Elementary ion (As⁺ ) Is 1-5 × 10¹³cm^-2About do
Ping.

Thereafter, an SiO ₂ film is deposited on the entire surface by CVD to a thickness of about 100 to 200 nm, and this is etched back by anisotropic etching such as RIE. Thereby, as shown in FIG. 1, the sidewall SW is formed on the side surface of the gate stacked film. In this state, high-concentration n-type impurities are ion-implanted into the Si active region outside the sidewall SW to form source / drain impurity regions S / D. In this ion implantation, for example, As is self-aligned using the gate laminated film and the sidewall SW as a mask.
⁺ Is doped about 1 to 5 × 10 ¹⁵ cm ⁻² . After that, an interlayer insulating film and a wiring layer are formed to complete the memory transistor.

The present invention is not limited to the memory cell array system. FIGS. 8 and 9 are circuit diagrams showing examples of connection between cells in a memory cell array of memory transistors. FIG. 8 shows a basic configuration of a so-called NOR type memory cell array. Although only two memory transistors are shown here, a row direction (lateral direction in the figure) not shown
The gate electrodes (control gates CG) of the memory transistors arranged in a row are commonly connected in the row direction by word lines WLi-1, WLi or WLi + 1. Further, the source S in the source / drain impurity region S / D
Are commonly connected in the column direction (vertical direction in the drawing) by a source line SL, and one of them that functions as a drain D is commonly connected in the column direction by a bit line BL. As a memory cell array based on such transistor connection, a NOR type in which a source line is provided for each column is best known. In addition, an element isolation insulating layer in which a HiCR (high capacity coupling) type in which a source line is shared between two columns, and an impurity diffusion layer to be switched and used as a source line or a bit line is alternately arranged in a row direction with a channel forming region. VG (virtual ground) type, AND type in which source lines and bit lines are hierarchized for each of a predetermined number of cells in the column direction, and a lower wiring is connected to an upper wiring via a selection transistor, only a bit line Is a hierarchical D
There is an INOR (split NOR) type.

FIG. 9 shows a basic configuration of a so-called NAND type memory cell array. Here one NA
Although only ND columns are shown, the gate electrodes (control gates CG) of the memory transistors are connected to word lines WL1,..., WLn-2, among a plurality of NAND columns arranged in a row direction (vertical direction in the figure). WLn-1 and WLn are commonly connected in the row direction. The memory transistors in the NAND string are connected in series, and one end of the drain D is connected to the bit line BL via a select transistor (not shown). The source S at the other end of the NAND string is connected to a source line SL via a select transistor not shown.

Next, the operation of the memory transistor will be described. In the present invention, the writing method, the reading method, and the erasing method of the memory transistor are not limited. Here, first, as a first operation example, F
Writing and reading by N tunneling implantation and erasing by FN tunneling on the entire channel will be described on the premise of a NOR type memory cell array (FIG. 8).

At the time of writing, the source S and the drain D are all set to 0 V with respect to the substrate potential, and a positive potential, for example, 18 V is applied to the gate G. By this gate voltage application, minority carriers (electrons) are induced on the surface of the channel formation region, and an inversion layer (channel) is formed. Some of the electrons are conducted through the bottom insulating film BTM by the tunnel effect, and when they reach the charge storage layer (floating gate FG), they lose energy due to phonon scattering and are stored. As a result, the threshold voltage of the memory transistor rises, for example, to the write state “1”. For a memory transistor that maintains the write state “0”, that is, the erase state, a predetermined positive voltage is applied to the sources S and D or a gate voltage of 10 V is not applied, so that a channel is not formed and tunnel injection is performed. Does not happen.

At the time of reading, 0 V is applied to the source and 1.5 V is applied to the drain D with reference to the substrate potential. Further, a positive voltage, for example, 2 V, is applied to the gate so that the memory transistor in the write state "0" is sufficiently turned on under the condition of the drain voltage or a channel conductivity close to the on state is obtained. On the other hand, since the memory transistor in the write state “1” has a high threshold voltage, the channel conductivity does not increase until effective under the same bias voltage condition. In any case, under these conditions,
There is almost no charge movement through the bottom insulating film BTM, and the number of electrons in the charge storage layer is not effectively changed. The difference in the change in the channel conductivity becomes the difference in the read current, and the potential change occurs in the drain voltage D. This potential change is amplified by a detection circuit (sense amplifier) to store the stored information “1” and “0”.
Is read.

At the time of erasing, the source and the drain are all set to 0 V with respect to the substrate potential, and a negative potential, for example, -15 V is applied to the gate G. At this time, in the memory transistor in the write state “1”, the electrons accumulated in the floating gate FG are returned to the Si active region (channel formation region) by tunneling through the bottom insulating film BTM. Therefore, all the memory transistors are aligned in the erased state (written state “0”).

Next, as a second operation example, a case where writing is performed by injection of channel hot electrons (CHE) and erasing is performed by injection of hot holes caused by a band-to-band tunnel current will be described.

At the time of writing, the source S is set to 0 V, the drain D is set to 5 V, and a positive voltage, for example, 10 V, is applied to the gate G based on the substrate potential. Under this bias condition, the drain voltage is 5 V, which is higher than in the first operation example, and electrons are accelerated in the channel to become high-energy electrons (hot electrons) at the drain end. If some of the hot electrons have higher energy than the energy barrier of the bottom insulating layer BTM, those electrons cross the energy barrier of the bottom insulating film BTM by a scattering process and are injected into the floating gate FG, where they are scattered by phonon scattering. Loses energy and accumulates. Such a CHE injection does not occur in the memory transistor that maintains the erased state (written state “0”) because the drain voltage 5 V or the gate voltage 10 V is not applied.

Reading is performed in the same manner as in the first operation example.

The erasing can be performed in the same manner as in the first operation example, but here, the erasing is performed with reference to the substrate potential.
0V for source S, 5V for drain D, -5V for gate G
A high electric field is applied only between the drain end and the gate. As a result, the surface of the drain end becomes deeply depleted, and electrons flow toward the substrate, thereby generating holes. The generated holes drift to the channel forming region side, are accelerated by the gate voltage, and part of the holes become hot holes. Hot holes generated by the band-to-band tunneling are injected into the floating gate FG and accumulated. Thereby, the floating gate F
The potential of G increases, the threshold voltages of all the memory transistors decrease, and the memory transistor enters an erased state.

In the NAND type shown in FIG. 9, writing and erasing are usually performed by tunnel injection over the entire channel on the same principle as in the first operation example.

Second Embodiment The second embodiment relates to a MONOS type memory transistor.

FIG. 10 shows a sectional structure of the MONOS type memory transistor. This memory transistor is
As the charge storage layer, a silicon nitride SiN _x film is used instead of the floating gate FG of the first embodiment. The charge trap formed in the region centered on the charge storage layer functions as a discrete charge storage means.
As the top insulating film TOP, a silicon oxide film having a thickness of about 3.5 to 5 nm is used. In the MONOS type, since the charge storage layer is an insulating film, as shown in FIG. 10, the charge storage layer SIN and the bottom insulating film BTM under the charge storage layer SIN should not be collectively patterned with the gate voltage G and should be left on the entire surface. Can be. Of course, patterning may be performed in the same shape as in the first embodiment.

In the formation of this memory transistor, the first
The steps up to the formation of the bottom insulating film BTM are performed in the same manner as in the embodiment. However, since the charge storage layer of the MONOS type memory transistor is discretized and has extremely low conductivity, the charge storage layer has excellent charge retention characteristics. As a result, the bottom insulating film BTM has
It can be thinner than the FG type of the embodiment.

In forming the charge storage layer SIN, a gas containing Si such as monosilane (SiH ₄ ), dichlorosilane (SiCl ₂ H ₂ ), trichlorosilane (SiCl ₃ H), tetrachlorosilane (SiCl ₄ ), and N ₂ Alternatively, SiN _x is deposited to a thickness of 1 to 20 nm by a CVD method using a gas containing a nitrogen atom such as NH ₃ as a raw material.

At the time of this SiN _x film formation, for example, a layer close to the substrate is subjected to CVD under the condition that the partial pressure ratio of NH ₃ / SiCl ₂ H ₂ is small, and then under the condition that the partial pressure ratio of NH ₃ / SiCl ₂ H ₂ is large. It is desirable to perform CVD. Thus, the Si—H bond density can be kept low in a region near the channel formation region CH, and the Si—H bond density can be increased on the side of the top insulating film TOP far from the channel formation region CH. Since the Si—H bond forms a Si dangling bond when hydrogen is replaced, its density contributes to the distribution of charge traps. Therefore, in the SiN _x thus formed, a high-density charge trap is likely to be formed on the side far from the channel formation region CH after the formation of the top insulating film TOP. Therefore, the charge once captured by the charge trap is difficult to return to the substrate side, and the charge retention characteristics are improved accordingly.

To obtain the same effect, another desirable C
As a method of switching VD conditions, at the time of SiN _x film formation,
The layer close to the substrate is treated with a mixed gas of NH ₃ / SiCl ₄
VD, and then CVD is performed by switching to a mixed gas of NH ₃ / SiCl ₂ H ₂ . Also according to this method, the number of Si—H bonds is small in a region near the channel formation region CH,
The number of Si—H bonds increases in a region far from the channel formation region CH, and as a result, charge retention characteristics are improved.

The subsequent steps for forming the memory transistor are as follows:
As in the first embodiment, the top insulating film TOP is formed using the gate electrode G as a mask and the
After the etching by E, the charge storage layer SIN and the bottom insulating film BTM are not etched.

The memory cell array system to which the memory transistor structure can be applied is not limited, and the various memory cell array systems described with reference to FIGS. 8 and 9 can be employed as in the first embodiment. Further, the first and second operation examples described in the first embodiment are also applicable in the present embodiment.

Hereinafter, the charge storage means (charge trap) represented by the present embodiment is peculiar to a discrete memory transistor, and two-bit information can be effectively written by writing two-bit information in one memory transistor without multileveling. A method for reading data will be described. Note that this method uses the N
It can be implemented with an OR type memory cell array. This method uses C
Injecting charges from the drain end side of the charge storage layer SIN by HE injection is common to the above-described second operation example. However, in this embodiment, since the charge storage means is discretized, the conductivity in the lateral direction is extremely low.
The injected charges are locally stored at the drain end of the charge storage layer SIN. By utilizing this fact, when the second charge injection is performed by reversing the method of applying the drain voltage, charges can be locally accumulated at the source terminal at the time of the first charge injection. Also,
Since the threshold voltage at the time of reading is governed by the amount of charge stored on the source side, the data is independently written to both ends of the charge storage layer SIN by two read operations in which the application direction of the read drain voltage is changed. The information can be read independently.

Specifically, at the time of writing the first binary information, for example, the source line SL is set with reference to the substrate potential.
(Source S) is set to 0 V, bit line BL (drain D) is set to 4.5 V, and a positive voltage, for example, 9 V is applied to gate G. At this time, electrons supplied from the source line SL are accelerated in the formed channel to become hot electrons, and a part of the electrons is supplied from the drain D to the charge storage layer SIN.
Captured within and accumulated locally. When reading the first binary information, the bit line B
0 V is applied to L (indicated by D in the figure, this is actually the source), and, for example, 1.5 V is applied to the source line SL (indicated by S in the figure, but is actually the drain) Then, for example, 2 V is applied to the gate electrode G. The threshold voltage of a memory transistor changes mainly in accordance with the presence or absence of stored charge on the source side. Therefore, the read current flows or the read current amount is determined according to the presence or absence of the charge at the source side end indicated by D in FIG.
A potential change occurs in the source line SL. By amplifying the potential change of the source line by a sense amplifier or the like, the first binary information can be read.

On the other hand, writing and reading of the second binary information can be performed by exchanging the voltages applied to the source line and the bit line in the case of the first binary information. That is, at the time of writing the second binary information, for example, the bit line SL (the drain D shown in the figure) is set to 0 V, the source line SL (the source S shown in the figure) is set to 4.5 V, and the gate is set with reference to the substrate potential. G has a positive voltage, for example 9
V is applied. At this time, electrons supplied from the bit line side are accelerated in the formed channel to become hot electrons, and a part thereof is captured in the charge storage layer SIN from the drain side indicated by S in FIG. Is done.
At the time of reading the second binary information, 0 V is applied to the source line SL (source S) and the bit line BL
For example, 1.5 V is applied to (drain D), and 2 V is applied to gate electrode G, for example. The threshold voltage of a memory transistor changes mainly in accordance with the presence or absence of stored charge on the source side. Therefore, the read current flows or the read current amount is determined according to the presence or absence of the charge at the source S side end, or the amount of accumulated charge, and a potential change occurs in the bit line BL. By amplifying the potential change of the bit line by a sense amplifier or the like, the second binary information can be read.

At the time of erasing, as in the second operation example, the source and the drain are all set to 0 V with respect to the potential, and a negative voltage, for example, -10 V is applied to the gate G. At this time, the electrons stored in the charge storage layer SIN are transferred to the bottom insulating film BTM.
Is returned to the channel forming region CH.

Third Embodiment In the first and second embodiments, when forming the bottom insulating layer BTM, N ₂ O, NO, NH ₃ or N _{2 is set} to 5 MHz.
A silicon oxynitride film or a silicon nitride film has been formed by exposing the Si active region to an ionized gas ionized by an AC electromagnetic field of up to 5 GHz (for example, 13.56 MHz). On the other hand, in the third embodiment, the substrate heated to about 1000 ° C. is exposed to the source gas without ionizing the source gas. At this time, nitrogen tends to be segregated on the Si / nitride film interface side because nitrogen atoms are hardly diffused in a region where the nitrogen concentration in Si is high. Therefore, the bottom insulating film BTM having the same nitrogen concentration distribution as in the first and second embodiments can be formed.

[0064] In the formation of the bottom insulating film BTM in the fourth embodiment The fourth embodiment,
First, the surface of the Si active region including the channel forming region CH is thermally oxidized to form a silicon oxide film. Then, the formed silicon oxide film is exposed to an ionizing gas by the same method as in the first and second embodiments to form a silicon oxynitride film or a silicon nitride film. Alternatively, as in the third embodiment, the substrate on which a silicon oxide film is formed by thermal oxidation is added to each raw material gas without ionizing the raw material gas.
By heating and exposing to about ° C., a silicon oxynitride film or a silicon nitride film is formed as the bottom insulating film BTM.

Fifth Embodiment In this embodiment, when a silicon oxynitride film is formed as the bottom insulating film BTM, monosilane (SiH ₄ ), dichlorosilane (SiCl ₂ H ₂ ), trichlorosilane (Si
Cl ₃ H), tetrachlorosilane (SiCl ₄ ), etc.
A silicon oxynitride film is formed on a Si active region by CVD using a gas containing i and a gas containing atoms containing an oxygen-nitrogen bond such as NO and N ₂ O as raw materials. Alternatively, CVD is performed using the above-mentioned gas containing Si and a mixed gas of a gas containing oxygen and a gas containing nitrogen such as NO and N ₂ or O ₂ and N ₂ as raw materials, so that oxynitride A silicon film is formed. During the CVD, SiH ₄ , Si
Cl ₂ H ₂ , SiCl ₃ H, SiCl ₄ and NO, N ₂
By changing the gas flow ratio with O, a nitrogen concentration distribution as shown in FIG. 2 is obtained.

Modifications Embodiments of the present invention are not limited to the above-described first to fifth embodiments, and various modifications are possible. First, in the present invention, the MO
Instead of the charge storage layer SIN of the NOS type, a film made of an insulating material containing a charge trap such as aluminum oxide AlO _x or tantalum oxide TaO _x can be used.

The AlO _x film is made of, for example, AlCl ₃ , C
It is formed by a CVD method using a source gas containing O ₂ and H ₂ . Alternatively, aluminum alksides (Al
(C ₂ H ₅ O) _3, Al (C ₃ H ₇ O) ₃ , Al (C ₄ H ₉
O) ₃ ) by pyrolysis
An AlO _x film is formed. Further, the TaO _x film is formed, for example, by using a C gas using TaCl ₅ , CO ₂ and H ₂ as source gases.
It is formed by the VD method. Alternatively, TaCl ₂ (OC ₂
H ₅₎ by a method of depositing by thermal decomposition, such as ₂ C ₅ H ₇ O ₂ or _{Ta (OC 2 H 5) 5} , to form a TaO _x film.

Further, the charge storage means may be composed of a conductor having a small particle diameter made of polycrystalline silicon or metal. In this case, the charge storage layer is composed of, for example, a small-diameter conductor dispersed and formed on the bottom insulating film BTM, and an insulating film that fills a space between the small-diameter conductors. In this case, a top insulating film such as a MONOS type is not required. Further, a so-called M in which a MONOS type top insulating film is omitted and a nitride film is thickly deposited.
The present invention can be applied to the NOS type.

For example, Si _x Ge is used as a conductor having a small particle diameter.
_When forming _1-x microcrystals, monosilane (SiH
₄ ), dichlorosilane (SiCl ₂ H ₂ ), trichlorosilane (SiCl ₃ H), tetrachlorosilane (SiC
To add Ge to a gas containing Si such as l ₄ ), a gas obtained by adding germane (GeH ₄ ) is used as a raw material gas.
For example, CVD is performed at a substrate temperature of 650 ° C. And
When CVD is stopped during the island-like growth process that occurs in the initial growth process, countless Si _x Ge _1-x microcrystals can be dispersed and formed on the bottom insulating film BTM. Thereafter, for example, a silicon oxide film is deposited by CVD.

Also, polycrystalline silicon is deposited, and this film is
A fine polysilicon tod may be formed by using a fine processing technique such as B drawing, and this may be embedded with a silicon oxide film and used as a charge storage layer including a discretized small-diameter conductor.

In the embodiment of the present invention described above, since the bottom insulating film BTM has a nitrogen concentration distribution as shown in FIG. 2, for example, the leakage current characteristic in the bottom insulating film BTM is low. Significantly improved, thereby improving charge retention characteristics.

Further, as shown in the graph of FIG. 2, the center of the nitrogen concentration distribution is unevenly distributed in the channel forming region CH from the center of the thickness of the bottom insulating film BTM. Therefore, the bottom insulating film B
In TM, the energy barrier on the substrate side is reduced while maintaining the energy barrier on the charge storage layer side. This is because as the nitrogen concentration increases, the energy barrier decreases. Therefore, the charge injection efficiency can be increased without lowering the charge retention characteristics. In addition, the required charge injection efficiency can be ensured even if the bottom insulating film is made thicker, so that the charge retention characteristics are improved accordingly.

Further, the nitrogen concentration of the bottom insulating film BTM is extremely low on the substrate side, and the nitrogen concentration sharply increases from near the interface with the channel formation region CH toward the inside of the bottom insulating film. In such a nitrogen concentration distribution, since nitrogen atoms are scarcely present near the interface with the substrate, the occurrence of nitrogen atom scattering at the substrate interface level and at the interface is suppressed to a low level. This causes a small change in the transconductance of the memory element and a small change in the threshold voltage, in addition to the leakage reduction. As a result, the retention characteristic with respect to the threshold voltage variation after repeated writing and erasing was improved.

[0074]

According to the present invention, by improving the nitrogen concentration distribution of the bottom insulating film, the film quality can be improved in a direction preferable as the bottom insulating film of the nonvolatile memory transistor.
As a result, the data retention characteristics and the threshold voltage fluctuation (retention characteristics) after repeated rewriting were improved, and the writing and erasing efficiency was further improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a memory transistor according to a first embodiment.

FIG. 2 shows a memory transistor according to an embodiment;
5 is a graph showing a nitrogen concentration distribution in a direction perpendicular to the substrate centering on a bottom insulating film.

FIG. 3 is a cross-sectional view after the formation of an element isolation insulating layer in the manufacture of the memory transistor according to the first embodiment.

FIG. 4 is a cross-sectional view after a bottom insulating film is formed in the manufacture of the memory transistor according to the first embodiment.

FIG. 5 is a cross-sectional view after formation of a conductive film serving as a control gate in the manufacture of the memory transistor according to the first embodiment.

FIG. 6 is a cross-sectional view after the formation of the LDD region in the manufacture of the memory transistor according to the first embodiment.

FIG. 7 is a graph showing current-current obtained from an experiment on which the present invention is based.
It is a graph which shows the FN plot of a voltage characteristic.

FIG. 8 is a circuit diagram showing a first connection relationship of a memory transistor in a memory cell array according to the embodiment.

FIG. 9 is a circuit diagram showing a second connection relationship in the memory cell array of the memory transistor according to the embodiment.

FIG. 10 is a sectional view of a memory transistor according to a second embodiment.

[Explanation of symbols]

SUB: semiconductor substrate, well or semiconductor layer, ISO ...
Element isolation insulating layer, S / D: source / drain impurity region, CH: channel forming region, BTM: bottom insulating film,
FG: floating gate (charge storage layer), SIN:
Charge storage layer, INTG: inter-gate insulating film, TOP: top insulating film, CG: control gate, SW: sidewall, S: source, D: drain, G: gate, WL
... word line, BL ... bit line, SL ... source line.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ichiro Fujiwara F-term (reference) in Sony Corporation 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo 5F001 AA04 AA11 AA12 AA13 AA43 AC01 AC03 AD70 AF25 AG23 5F083 EP02 EP07 EP17 EP18 EP44 EP45 EP63 EP76 EP77 EP78 EP79 ER03 ER04 ER22 GA06 GA21 HA02 JA04 JA05 JA35 JA36 JA37 JA38 JA39 JA40 NA01 PR15 PR21 PR22 PR36

Claims (24)

[Claims] A semiconductor substrate or a semiconductor layer supported by the substrate; an insulating film formed on a surface region of the semiconductor substrate or the semiconductor layer and including a charge storage layer into which charges are injected from the substrate side; A non-volatile semiconductor storage device having a control electrode on the insulating film, wherein a bottom insulating film includes a region having a different nitrogen concentration in a film thickness direction between the semiconductor surface region on the substrate side and the charge storage layer. A nonvolatile semiconductor memory device having a film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said bottom insulating film has a maximum nitrogen concentration distribution in a thickness direction thereof. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said bottom insulating film has a nitrogen concentration distribution that tends to have a single maximum value from a lower surface on the substrate side to an upper surface in contact with the charge storage layer. 4. The non-volatile semiconductor memory device according to claim 3, wherein a peak of a single maximum value of the nitrogen concentration distribution is unevenly distributed on the substrate side from the center of the thickness of the bottom insulating film. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said bottom insulating film has a nitrogen concentration distribution center in a film thickness direction unevenly distributed on a substrate side. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said bottom insulating film has a nitrogen concentration distribution in which the nitrogen concentration increases from near an interface with the semiconductor surface region on the substrate side toward the inside of the bottom insulating film. . 7. The method according to claim 1, wherein the bottom insulating film is formed of silicon nitride SiN _x (x
> 0), silicon oxynitride _{SiO x N y (x, y} > 0) a non-volatile semiconductor memory device according to claim 1 wherein the main constituent of either. 8. A charge trap is distributed in a region inside the insulating film centered on the charge storage layer as storage means for storing storage charges discrete in a plane facing the surface of the semiconductor region and in a film thickness direction. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 9. The nonvolatile semiconductor memory device according to claim 8, wherein said charge storage layer includes an insulating film exhibiting Frenkel-Pool conduction characteristics. 10. The semiconductor device according to claim 1, wherein the charge storage layer is formed of silicon nitride SiN _x (x
> 0), silicon oxynitride _{SiO x N y (x, y} > 0), aluminum oxide AlO _x (x> 0), according to claim 9, further comprising a film made of any of tantalum oxide TaO _x (x> 0) Nonvolatile semiconductor memory device. 11. The semiconductor device according to claim 11, wherein said charge storage layer is formed of silicon nitride SiN _x (x>
11. The nonvolatile semiconductor memory device according to claim 10, wherein the upper region on the control electrode side contains a silicon-hydrogen bonding group having a higher density than the lower region on the substrate side. 12. The nonvolatile semiconductor memory device according to claim 8, wherein the insulating film between the semiconductor region and the control electrode comprises the bottom insulating film, the charge storage layer, and a top insulating film on the charge storage layer. . 13. The small-diameter conductor into which electric charges are injected during operation, and the charge storage layer is buried between the small-diameter conductors. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device is made of an insulating material. 14. The nonvolatile semiconductor memory device according to claim 13, wherein said small-diameter conductor is made of fine particles of polycrystalline silicon. 15. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage layer is a single conductive layer made of polycrystalline silicon. 16. A non-volatile semiconductor device comprising: a semiconductor substrate or a semiconductor layer supported by the substrate; and an insulating film including a charge storage layer into which charges are injected from the substrate side, and a control electrode on the insulating film. A method for manufacturing a semiconductor storage device, comprising: exposing a surface of the semiconductor substrate or the semiconductor layer to a plasma containing nitrogen atoms, when the insulating film is formed on the semiconductor substrate or the semiconductor layer, A method for manufacturing a nonvolatile semiconductor memory device in which the semiconductor surface is directly formed by nitriding. 17. The non-volatile semiconductor device according to claim 16, wherein said semiconductor substrate or semiconductor layer is exposed to said plasma while introducing a source gas of nitrogen N ₂ or ammonia NH ₃ when forming a silicon nitride film as said bottom insulating film. A method for manufacturing a semiconductor storage device. 18. When forming the silicon oxynitride film as the bottom insulating film, nitrogen N ₂ or ammonia NH ₃
17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein the semiconductor substrate or the semiconductor layer is exposed to the plasma while introducing a mixed gas of nitrogen and nitrogen oxide NO or N ₂ O as a source gas. 19. The nonvolatile semiconductor memory device according to claim 16, wherein said plasma is generated in an AC electromagnetic field within a frequency range of 5 MHz to 5 GHz, and said semiconductor substrate or semiconductor layer is exposed to said plasma in said AC electromagnetic field. Production method. 20. The non-volatile memory according to claim 16, wherein a plasma is generated, the generated plasma is guided to a spatially separated place, and the semiconductor substrate or the semiconductor layer is exposed to the plasma in which the number of charged ions is reduced by the induction. Of manufacturing a nonvolatile semiconductor memory device. 21. The non-volatile semiconductor memory device according to claim 16, wherein the plasma is transmitted through a grid electrode after the generation of the plasma, and the semiconductor substrate or the semiconductor layer is exposed to plasma in which the number of charged ions is reduced by the transmission through the grid electrode. Manufacturing method. 22. When forming a silicon nitride film as the charge storage layer on the formed bottom insulating film, start forming the silicon nitride film under the condition of relatively reducing the number of silicon-hydrogen bonding groups. 17. The method for manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein the condition is switched to a condition in which the number of silicon-hydrogen bonding groups is relatively increased in the middle. 23. The method for manufacturing a nonvolatile semiconductor memory device according to claim 22, wherein the switching of the film forming conditions changes a mixing ratio of a plurality of source gases. 24. The method for manufacturing a nonvolatile semiconductor memory device according to claim 22, wherein the switching of the film forming conditions changes the kind of the source gas to be mixed.