JP2011210777A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device having a non-volatile memory.SOLUTION: A memory cell of the non-volatile memory includes a control gate electrode CG formed on a p-type well PW via an insulating film 3, a memory gate electrode MG which is formed on the p-type well PW and is adjacent to the control gate electrode CG, and an insulating film 5 which is formed between the memory gate electrode MG and the p-type well PW and between the control gate electrode CG and the memory gate electrode MG and has a charge accumulating part inside. The memory gate electrode MG is formed of a laminated film including a non-doped silicon film 6a and a silicon film 6b to which impurity is introduced. Concentration of impurity of the silicon film 6b is increased. Thus, resistance of the memory gate electrode MG is lowered and operation speed of the non-volatile memory is increased. A data retention characteristic of the non-volatile memory can be improved by lowering the concentration of the impurity in the silicon film 6a.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technology effective when applied to a semiconductor device having a nonvolatile memory and a method for manufacturing the same.

  EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a nonvolatile semiconductor memory device that can be electrically written and erased. These storage devices (memory) typified by currently used flash memory have a conductive floating gate electrode and a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. The charge accumulation state in the floating gate and the trapping insulating film is stored information and is read as the threshold value of the transistor. This trapping insulating film refers to an insulating film capable of accumulating charges, and examples thereof include a silicon nitride film. The threshold value of the MISFET is shifted by such charge injection / release to / from the charge storage region to operate as a memory element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, by using a silicon nitride film as a charge storage region, it is superior in data retention reliability because it accumulates charges discretely compared to a conductive floating gate film, and also in data retention reliability. Therefore, the oxide films above and below the silicon nitride film can be made thinner, and the voltage of the write / erase operation can be lowered.

  In Japanese Patent Laid-Open No. 2008-294088 (Patent Document 1), a first memory gate electrode made of a polycrystalline silicon film is provided on the gap portion side between the selection gate electrode and the memory gate electrode, and the first region is provided on the source region side. A technique for providing a second memory gate electrode made of a polycrystalline silicon film having a higher impurity concentration than the polycrystalline silicon film constituting the memory gate electrode is described.

  Japanese Patent Laid-Open No. 9-97850 (Patent Document 2) describes a technique in which a polysilicon layer forming a floating gate is formed of a non-doped polysilicon layer / a phosphorus-doped polysilicon layer / a non-doped polysilicon layer. .

  Japanese Patent Laying-Open No. 2006-19373 (Patent Document 3) discloses that in a MONOS nonvolatile memory, a memory gate is made of a doped polycrystalline silicon film, and a polycrystalline silicon film is formed by ion implantation of impurities into an undoped silicon film. A technique for lowering the sheet resistance than the control gate made of is described.

  In Japanese Patent Application Laid-Open No. 2004-186252 (Patent Document 4), in a MONOS nonvolatile memory, after forming a selection gate electrode, a polycrystalline silicon film doped with an n-type impurity is deposited, and in this state, a semiconductor substrate is deposited. A p-type impurity is ion-implanted therein, and then a polycrystalline silicon film doped with an n-type impurity is further deposited, and the two deposited n-type impurities are anisotropically etched to form a memory gate. The technology is described.

JP 2008-294088 A Japanese Patent Laid-Open No. 9-97850 JP 2006-19373 A JP 2004-186252 A

  A memory gate electrode of a conventional split gate type nonvolatile memory is formed of, for example, a doped polysilicon film in which impurities are introduced to have a low resistivity. In recent years, it has been desired to maintain or improve the operation speed of the nonvolatile memory and further improve the data retention characteristics of the nonvolatile memory. In addition, it is desired to improve the reliability of the semiconductor device while improving the performance of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the performance of a semiconductor device and improving the reliability of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a semiconductor device according to a typical embodiment, a memory gate electrode of a nonvolatile memory is formed by a laminated film of a first silicon film and a second silicon film having a higher impurity concentration.

  In addition, in the method of manufacturing a semiconductor device according to a typical embodiment, a memory gate electrode of a nonvolatile memory is formed by a laminated film of a first silicon film and a second silicon film having a higher impurity concentration. is there.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

  Further, as another effect of the present invention, the reliability of the semiconductor device can be improved.

  As another effect of the present invention, the performance of the semiconductor device can be improved and the reliability of the semiconductor device can be improved.

1 is a fragmentary cross-sectional view (memory cell region) of a semiconductor device according to an embodiment of the present invention; 1 is a fragmentary cross-sectional view (memory gate shunt region) of a semiconductor device according to an embodiment of the present invention; It is principal part sectional drawing (capacitor formation area) of the semiconductor device which is one embodiment of this invention. It is the elements on larger scale which expanded a part of FIG. It is an equivalent circuit diagram of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. It is a process flow figure showing a part of manufacturing process of a semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing (memory cell area | region) in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 9 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 8 during the manufacturing process; FIG. 10 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 9 during the manufacturing process; FIG. 9 is a fragmentary cross-sectional view (memory cell region) of the semiconductor device during the manufacturing step following that of FIG. 8; FIG. 12 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 11 during the manufacturing process; FIG. 12 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 11 during the manufacturing process; FIG. 12 is an essential part cross sectional view (memory cell region) of the semiconductor device during a manufacturing step following FIG. 11; FIG. 15 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 14 during the manufacturing process; FIG. 15 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 14 during the manufacturing process; FIG. 15 is a fragmentary cross-sectional view (memory cell region) of the semiconductor device during a manufacturing step following that of FIG. 14; FIG. 18 is an essential part cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 17 during the manufacturing process; FIG. 18 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 17 during the manufacturing process; It is a partial expanded sectional view of FIG. It is a partial expanded sectional view of FIG. FIG. 18 is a fragmentary cross-sectional view (memory cell region) of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 23 is an essential part cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 22 during the manufacturing process; FIG. 23 is a fragmentary cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 22 during the manufacturing process; FIG. 23 is a fragmentary cross-sectional view (memory cell region) of the semiconductor device during a manufacturing step following that of FIG. 22; FIG. 26 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 25 during the manufacturing process; FIG. 26 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 25 during the manufacturing process; FIG. 26 is an essential part cross sectional view (memory cell region) of the semiconductor device during a manufacturing step following FIG. 25; FIG. 29 is an essential part cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 28 during the manufacturing process; FIG. 29 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 28 during the manufacturing process; FIG. 29 is an essential part cross sectional view (memory cell region) of the semiconductor device during a manufacturing step following FIG. 28; FIG. 32 is an essential part cross sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 31 during the manufacturing step; FIG. 32 is an essential part cross sectional view of the semiconductor device during the manufacturing step following FIG. 31 (memory cell region); FIG. 34 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 33 during the manufacturing step; FIG. 34 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 33 during the manufacturing process; FIG. 34 is a main-portion cross-sectional view (memory cell region) of the semiconductor device during the manufacturing process following FIG. 33; FIG. 37 is a fragmentary cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 36 during the manufacturing process; FIG. 37 is a fragmentary cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 36 during the manufacturing process; FIG. 37 is a fragmentary cross-sectional view (memory cell region) of the semiconductor device during the manufacturing step following that of FIG. 36; FIG. 40 is a main-portion cross-sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 39 during the manufacturing process; FIG. 40 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 39 during the manufacturing process; FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39 (memory cell region); FIG. 44 is an essential part cross sectional view (memory gate shunt region) of the same semiconductor device as in FIG. 42 during the manufacturing process; FIG. 44 is an essential part cross-sectional view (capacitor formation region) of the same semiconductor device as in FIG. 42 during the manufacturing process; It is principal part sectional drawing of the semiconductor device of a 1st comparative example. It is principal part sectional drawing of the semiconductor device of a 1st comparative example. It is principal part sectional drawing of the semiconductor device of the 2nd comparative example. It is principal part sectional drawing of the semiconductor device of the 2nd comparative example. It is a table | surface which shows the conductivity type of a silicon film. It is principal part sectional drawing (memory cell area | region) of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing (memory gate shunt area | region) of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing (memory gate shunt area | region) of the semiconductor device which is other embodiment of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The present invention is a semiconductor device including a non-volatile memory (non-volatile memory element, flash memory, non-volatile semiconductor memory device), and the non-volatile memory mainly has a trapping insulating film (charge can be accumulated in a charge accumulation portion). Insulating film) is used. In the following embodiments, the nonvolatile memory will be described based on a memory cell using an n-channel MISFET (MISFET: Metal Insulator Semiconductor Field Effect Transistor) as a basis and using a trapping insulating film. The polarities (polarity of applied voltage and carrier polarity at the time of writing / erasing / reading) in the following embodiments are for explaining the operation in the case of a memory cell based on an n-channel MISFET. In the case of using a p-channel type MISFET as a basis, the same operation can be obtained in principle by inverting all the polarities such as applied potential and carrier conductivity type.

  The semiconductor device of the present embodiment will be described with reference to the drawings.

  1 to 3 are main part cross-sectional views of the semiconductor device of the present embodiment. FIG. 1 shows a main part cross-sectional view of the memory cell region 1A of the nonvolatile memory, and FIG. A cross-sectional view of the main part of the gate shunt region 1B is shown, and a cross-sectional view of the main part of the capacitor forming region 1C is shown in FIG. FIG. 4 is a partial enlarged cross-sectional view (partial cross-sectional view) of the memory cell MC in the semiconductor device of the present embodiment, and shows a part of FIG. 1 (a part of the memory cell region 1A) enlarged. . 4 shows the control gate electrode CG, the memory gate electrode MG and the insulating films 3 and 5 and the substrate region (p-type well PW immediately below them) in the structure of FIG. Only a part of the semiconductor substrate 1 is shown.

  The semiconductor device of the present embodiment is a semiconductor device provided with a nonvolatile memory. FIGS. 1 to 3 show the main parts of the memory cell region 1A, the memory gate shunt region 1B, and the capacitor forming region 1C of the nonvolatile memory. Cross-sectional views are shown respectively. The memory cell region 1A is a region where a memory cell MC of a nonvolatile memory is formed. The memory gate shunt region 1B is a region used for pulling up the memory gate electrode MG to the wiring M1, that is, a region where the memory gate electrode MG (the contact portion MGa thereof) is connected to the wiring M1 through the plug PG. The capacitor forming region 1C is a region where a PIP type capacitive element CP is formed. Memory cell region 1 </ b> A, memory gate shunt region 1 </ b> B, and capacitor formation region 1 </ b> C correspond to different regions on the main surface of the same semiconductor substrate 1. 1 and 2 show a cross section perpendicular to the extending direction of the control gate electrode CG and the memory gate electrode MG (direction perpendicular to the paper surface of FIGS. 1 and 2), and is shown in FIG. The control gate electrode CG and the control gate electrode CG shown in FIG. 2 are integrally formed, and the memory gate electrode MG shown in FIG. 1 and the contact portion electrode MGa (shown in FIG. The contact portion MGa of the memory gate electrode MG is integrally formed. 1 to 3, the memory cell region 1 </ b> A, the memory gate shunt region 1 </ b> B, and the capacitor formation region 1 </ b> C are shown in different cross-sectional views, but these are formed on the same semiconductor substrate 1. The capacitive element CP formed in the capacitor formation region 1C is used in a peripheral circuit or the like. Here, the peripheral circuits are, for example, a processor such as a CPU, a control circuit, a sense amplifier, a column decoder, a row decoder, an input / output circuit, and the like.

  As shown in FIGS. 1 to 3, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, has an element isolation region 2 for isolating elements. The p-type well PW is formed in the active region isolated (defined) by the element isolation region 2. The p-type well PW is mainly formed in the memory cell region 1A. Since the element isolation region 2 is formed in the memory gate shunt region 1B and the capacitor formation region 1C, the p-type well PW is not formed. .

  In the p-type well PW of the memory cell region 1A, a memory cell MC of a nonvolatile memory including a memory transistor and a control transistor (selection transistor) as shown in FIG. 1 is formed. In the memory cell region 1A, a plurality of memory cells MC are actually formed in an array, but the memory cell region 1A in FIG. 1 shows a cross section of one of the memory cells MC. The memory cell region 1A is electrically isolated from other regions by the element isolation region 2.

  As shown in FIGS. 1 and 4, the memory cell MC of the nonvolatile memory in the semiconductor device of the present embodiment is a split gate type memory cell and has a control gate electrode (selection gate electrode) CG. Two MISFETs of a (selection transistor) and a memory transistor having a memory gate electrode (memory gate electrode) MG are connected.

  Here, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) including a gate insulating film including a charge storage portion (charge storage layer) and a memory gate electrode MG is referred to as a memory transistor (memory transistor). The MISFET including the gate electrode CG is referred to as a control transistor (selection transistor, memory cell selection transistor). Therefore, the memory gate electrode MG is a gate electrode of the memory transistor, the control gate electrode CG is a gate electrode of the control transistor, and the control gate electrode CG and the memory gate electrode MG are nonvolatile memories (memory cells thereof). It is the gate electrode which comprises.

  Hereinafter, the configuration of the memory cell MC will be specifically described.

  As shown in FIGS. 1 and 4, a memory cell MC of a nonvolatile memory includes n-type semiconductor regions MS and MD for source and drain formed in a p-type well PW of a semiconductor substrate 1, and a semiconductor substrate. A control gate electrode (first gate electrode) CG formed on the top of 1 (p-type well PW), and a memory gate electrode formed on the top of the semiconductor substrate 1 (p-type well PW) and adjacent to the control gate electrode CG (Second gate electrode) MG. The memory cell MC of the nonvolatile memory further includes an insulating film 3 formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW), a memory gate electrode MG, and the semiconductor substrate 1 (p-type well PW). ) And an insulating film 5 formed between the memory gate electrode MG and the control gate electrode CG.

  The control gate electrode CG and the memory gate electrode MG extend along the main surface of the semiconductor substrate 1 and are arranged side by side with the insulating film 5 interposed between the opposing side surfaces (side walls). The extending direction of the control gate electrode CG and the memory gate electrode MG is a direction perpendicular to the paper surface of FIGS. The control gate electrode CG and the memory gate electrode MG are formed above the semiconductor substrate 1 (p-type well PW) between the semiconductor region MD and the semiconductor region MS via the insulating films 3 and 5 (however, the control gate electrode CG is an insulating film). 3, the memory gate electrode MG is formed via the insulating film 5), the memory gate electrode MG is located on the semiconductor region MS side, and the control gate electrode CG is located on the semiconductor region MD side.

  The control gate electrode CG and the memory gate electrode MG are adjacent to each other with the insulating film 5 interposed therebetween, and the memory gate electrode MG is disposed on the side wall of the control gate electrode CG via the insulating film 5 via the sidewall spacer. It is formed in a shape. The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW) and the region between the memory gate electrode MG and the control gate electrode CG. .

  The insulating film 3 (that is, the insulating film 3 under the control gate electrode CG) formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW) functions as a gate insulating film of the control transistor, and is a memory gate. The insulating film 5 between the electrode MG and the semiconductor substrate 1 (p-type well PW) (that is, the insulating film 5 under the memory gate electrode MG) is a gate insulating film of the memory transistor (a gate insulating film having a charge storage portion inside). ).

  The insulating film 3 can be formed of, for example, a silicon oxide film or a silicon oxynitride film. The insulating film 3 is a metal oxide having a dielectric constant higher than that of the silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, in addition to the above-described silicon oxide film or silicon oxynitride film. A membrane may be used.

  The insulating film 5 includes a silicon oxide film (oxide film) 5a, a silicon nitride film (nitride film, charge storage layer) 5b on the silicon oxide film 5a, and a silicon oxide film (oxide film) 5c on the silicon nitride film 5b. It consists of a laminated film having

  In FIG. 1 to FIG. 3, in order to make the drawings easy to see, the laminated film of the silicon oxide film 5 a, the silicon nitride film 5 b, and the silicon oxide film 5 c is simply illustrated as the insulating film 5. As shown in FIG. 4, the insulating film 5 is composed of a laminated film of a silicon oxide film 5a, a silicon nitride film 5b on the silicon oxide film 5a, and a silicon oxide film 5c on the silicon nitride film 5b.

  Since the insulating film 5 has a stacked structure of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c, the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW) and the memory gate The insulating film 5 extending to the region between the electrode MG and the control gate electrode CG can also be regarded as a laminated gate insulating film (a gate insulating film having a laminated structure). However, the insulating film 5 between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW) functions as a gate insulating film of the memory transistor, but the insulation between the memory gate electrode MG and the control gate electrode CG. The film 5 functions as an insulating film for insulating (electrically separating) the memory gate electrode MG and the control gate electrode CG.

  Of the insulating film 5, the silicon nitride film 5b is an insulating film for accumulating charges and functions as a charge accumulating layer (charge accumulating portion). That is, the silicon nitride film 5 b is a trapping insulating film formed in the insulating film 5. Therefore, the insulating film 5 can be regarded as an insulating film having a charge storage portion (charge storage layer, here, the silicon nitride film 5b) inside.

  The silicon oxide film 5c and the silicon oxide film 5a located above and below the silicon nitride film 5b can function as a charge block layer (charge block film, charge confinement layer). With the structure in which the silicon nitride film 5b is sandwiched between the silicon oxide film 5c and the silicon oxide film 5a, charge can be accumulated in the silicon nitride film 5b. The silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c can also be regarded as ONO (oxide-nitride-oxide) films.

The semiconductor region MS is a semiconductor region that functions as one of a source region or a drain region, and the semiconductor region MD is a semiconductor region that functions as the other of a source region or a drain region. Here, the semiconductor region MS is a semiconductor region functioning as a source region, and the semiconductor region MD is a semiconductor region functioning as a drain region. The semiconductor regions MS and MD are each composed of a semiconductor region (n-type impurity diffusion layer) into which n-type impurities are introduced, and each has an LDD (lightly doped drain) structure. That is, the source semiconductor region MS includes an n ⁻ type semiconductor region 7a and an n ⁺ type semiconductor region 8a having an impurity concentration higher than that of the n ⁻ type semiconductor region 7a. It has an n ⁻ type semiconductor region 7b and an n ⁺ type semiconductor region 8b having an impurity concentration higher than that of the n ⁻ type semiconductor region 7b. The n ⁺ type semiconductor region 8a has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7a, and the n ⁺ type semiconductor region 8b has a deeper junction depth than the n ⁻ type semiconductor region 7b. And the impurity concentration is high.

  On the side walls (side walls that are not adjacent to each other) of the memory gate electrode MG and the control gate electrode CG, side wall insulating films (side walls, side walls) made of an insulator (silicon oxide film, insulating film) such as silicon oxide. Spacer) SW is formed. That is, the side (side surface) of the memory gate electrode MG opposite to the side adjacent to the control gate electrode CG via the insulating film 5 and the side adjacent to the memory gate electrode MG via the insulating film 5 are opposite. A sidewall insulating film SW is formed on the sidewall (side surface) of the control gate electrode CG on the side.

The n ⁻ type semiconductor region 7a of the source part is formed in a self-aligned manner with respect to the side wall of the memory gate electrode MG, and the n ⁺ type semiconductor region 8a is a side surface (memory gate) of the side wall insulating film SW on the side wall of the memory gate electrode MG. It is formed in a self-aligned manner with respect to the side surface opposite to the side in contact with the electrode MG. Therefore, the low concentration n ⁻ type semiconductor region 7a is formed under the sidewall insulating film SW on the sidewall of the memory gate electrode MG, and the high concentration n ⁺ type semiconductor region 8a is a low concentration n ⁻ type semiconductor region 7a. It is formed outside. Accordingly, the low concentration n ⁻ type semiconductor region 7a is formed adjacent to the channel region of the memory transistor, and the high concentration n ⁺ type semiconductor region 8a is in contact with the low concentration n ⁻ type semiconductor region 7a, and The n ⁻ type semiconductor region 7a is formed so as to be separated from the channel region.

The n ⁻ type semiconductor region 7b in the drain part is formed in a self-aligned manner with respect to the side wall of the control gate electrode CG, and the n ⁺ type semiconductor region 8b is a side surface (control gate) of the side wall insulating film SW on the side wall of the control gate electrode CG. It is formed in a self-aligned manner with respect to the side opposite to the side in contact with the electrode CG. For this reason, the low concentration n ⁻ type semiconductor region 7b is formed under the sidewall insulating film SW on the side wall of the control gate electrode CG, and the high concentration n ⁺ type semiconductor region 8b is a low concentration n ⁻ type semiconductor region 7b. It is formed outside. Therefore, the low concentration n ⁻ type semiconductor region 7b is formed adjacent to the channel region of the control transistor, the high concentration n ⁺ type semiconductor region 8b is in contact with the low concentration n ⁻ type semiconductor region 7b, and the control transistor The n ⁻ type semiconductor region 7b is formed so as to be separated from the channel region.

  A channel region of the memory transistor is formed under the insulating film 5 under the memory gate electrode MG, and a channel region of the control transistor is formed under the insulating film 3 under the control gate electrode CG. In the channel formation region of the control transistor under the insulating film 3 under the control gate electrode CG, a semiconductor region (p-type semiconductor region or n-type semiconductor region) for adjusting the threshold value of the control transistor is formed as necessary. In the channel formation region of the memory transistor under the insulating film 5 under the memory gate electrode MG, a semiconductor region for adjusting the threshold value of the memory transistor (p-type semiconductor region or n-type semiconductor region) is formed as necessary. Has been.

  The control gate electrode CG is made of a conductor (conductor film), but is preferably made of a silicon film 4 such as an n-type polysilicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). The silicon film 4 is an n-type silicon film and has a low resistivity by introducing n-type impurities. Specifically, the control gate electrode CG is made of a patterned silicon film 4.

  The memory gate electrode MG is composed of a laminated film of a silicon film 6a and a silicon film 6b on the silicon film 6a. Among these, the silicon film 6a is made of a non-doped (undoped) silicon film, and the silicon film 6b is made of a silicon film into which impurities are introduced (doped).

  Here, the non-doped (undoped) silicon film means a silicon film into which impurities are not intentionally introduced (added or doped). For this reason, the term “non-doped (undoped) silicon film” does not exclude the case where an unintended trace amount of impurities is included. On the other hand, the silicon film into which impurities are introduced (doped) means a silicon film into which impurities are intentionally introduced (added or doped).

  Accordingly, the silicon film 6a is made of a silicon film to which impurities are not intentionally introduced (added or doped), and the silicon film 6b is made of a silicon film to which impurities are intentionally introduced (added or doped). The silicon film 6a is preferably made of a non-doped (undoped) polysilicon (polycrystalline silicon) film, and the silicon film 6b is preferably a polysilicon (polycrystalline silicon) film into which impurities are introduced (doped), that is, a doped film. It consists of a topolysilicon film. Since the impurity introduced into the silicon film 6b is preferably an n-type impurity (for example, arsenic (As) or phosphorus (P)), the silicon film 6b is more preferably an n-type polysilicon film (n-type doped film). Polysilicon film).

  Since the silicon film 6a is made of a non-doped silicon film and the silicon film 6b is made of a silicon film into which impurities are introduced, the impurity concentration of the silicon film 6b is higher than the impurity concentration of the silicon film 6a, and the resistance of the silicon film 6b. The rate (specific resistance) is lower than the resistivity (specific resistance) of the silicon film 6a.

The upper portion (upper surface) of the memory gate electrode MG, the upper portion (upper surface) of the control gate electrode CG, and the upper surfaces (front surfaces) of the n ⁺ type semiconductor regions 8a and 8b are made of metal silicide by a salicide (Salicide: Self Aligned Silicide) technique or the like. A layer (metal silicide film) 11 is formed. The metal silicide layer 11 is made of, for example, a cobalt silicide layer or a nickel silicide layer. The metal silicide layer 11 can reduce diffusion resistance and contact resistance. In addition, from the viewpoint of preventing a short circuit between the memory gate electrode MG and the control gate electrode CG as much as possible, the metal silicide layer 11 may not be formed on one or both of the memory gate electrode MG and the control gate electrode CG. obtain.

  Further, as shown in FIG. 2, among the contact hole CNT and the plug PG filling the contact hole CNT, the contact hole CNT1 for connecting to the memory gate electrode MG and the plug PG1 filling the contact hole CNT are arranged in the memory gate shunt region 1B. It is formed above the contact portion MGa of the gate electrode MG. The contact portion MGa is formed integrally with the memory gate electrode MG formed in the shape of a side wall spacer on the side wall of the control gate electrode CG via the insulating film 5. That is, a portion of the memory gate electrode MG other than the contact portion MGa is formed in a sidewall spacer shape on one side wall of the control gate electrode CG via the insulating film 5, and formed in this sidewall spacer shape. The contacted part and the contact part MGa are integrally formed. Therefore, the contact portion MGa can be regarded as a part of the memory gate electrode MG, but the contact portion MGa is a portion that does not function as the gate electrode of the memory transistor of the memory cell MC of the nonvolatile memory. Therefore, the contact portion MGa is preferably provided in a region other than the memory cell region 1A in which a plurality of memory cells MC are arranged in an array (for example, the memory gate shunt region 1B disposed in the vicinity of the memory cell region 1A). It is preferable to arrange on the element isolation region 2.

  The contact portion MGa extends from a position adjacent to one side wall (side wall on which the memory gate electrode MG is formed) of the control gate electrode CG via the insulating film 5 away from the adjacent control gate electrode CG. It is extended. Since part of the contact part MGa rides on the control gate electrode CG, the contact part MGa has a part located on the control gate electrode CG. That is, the contact portion MGa extends from the control gate electrode CG to the element isolation region 2. However, the insulating film 5 is interposed between the contact portion MGa of the memory gate electrode MG and the side wall of the control gate electrode CG. The side wall insulating film SW is also formed on the side surface (side wall) of the contact portion MGa. The metal silicide layer 11 is also formed on the upper portion (upper surface) of the contact portion MGa in a region not covered with the sidewall insulating film SW.

  Similar to the side wall spacer-like memory gate electrode MG, the contact portion MGa is also formed of a laminated film of a silicon film 6a and a silicon film 6b on the silicon film 6a.

  As will be described later, the memory gate electrode MG etches back (anisotropic etching) a laminated film of silicon films 6a and 6b formed on the semiconductor substrate 1 so as to cover the control gate electrode CG. The laminated film (laminated film of silicon films 6a and 6b) is left on the side wall via the insulating film 5 in the form of a side wall spacer. For this reason, the memory gate electrode MG in a portion other than the contact portion MGa is formed of a stacked film (that is, a stacked film of silicon films 6a and 6b) remaining in a sidewall spacer shape. Although details will be described later, a resist pattern (corresponding to a photoresist pattern RP1a described later) is formed on the silicon film 6b in the etch back step of the stacked film (laminated film of the silicon films 6a and 6b). By leaving this laminated film (a laminated film of silicon films 6a and 6b) under the pattern, the contact portion MGa of the memory gate electrode MG is formed.

  Further, as shown in FIG. 3, a capacitive element CP is formed on the same semiconductor substrate 1 as that on which the memory cells MC of the nonvolatile memory are formed. The capacitance element CP in the capacitor formation region 1C will be specifically described.

  As shown in FIG. 3, the element isolation region 2 is formed on the semiconductor substrate 1 in the entire capacitor formation region 1 </ b> C. As shown in FIG. 3, a lower electrode (first electrode) LE of the capacitive element CP is formed on the upper part of the semiconductor substrate 1 in the capacitor forming region 1 </ b> C, that is, on the element isolation region 2. The lower electrode LE in the capacitor formation region 1C is formed of a conductor film in the same layer as the control gate electrode CG in the memory cell region 1A and the memory gate shunt region 1B. That is, both the control gate electrode CG and the lower electrode LE are formed by the silicon film 4 (patterned silicon film 4). The silicon film 4 constituting the control gate electrode CG and the lower electrode LE has a low resistivity by introducing n-type impurities.

  After the silicon film 4 is formed on the main surface of the semiconductor substrate 1 including the memory cell region 1A, the memory gate shunt region 1B, and the capacitor forming region 1C, the silicon film 4 is formed using a photolithography method, a dry etching method, or the like. By patterning, the control gate electrode CG is formed in the memory cell region 1A and the memory gate shunt region 1B, and the lower electrode LE is formed in the capacitor formation region 1C.

  On the lower electrode LE, an upper electrode (second electrode) UE is formed via a capacitive insulating film DE. The capacitor insulating film DE is formed of an insulating film in the same layer as the insulating film 5 in the memory cell region 1A and the memory gate shunt region 1B. That is, the capacitive insulating film DE of the capacitive element CP is formed by the insulating film 5 in the same layer as the gate insulating film (memory gate insulating film, here, the insulating film 5) of the memory transistor of the memory cell MC. In other words, both the capacitive insulating film DE of the capacitive element CP and the gate insulating film (memory gate insulating film) of the memory transistor of the memory cell MC are formed by the insulating film 5. For this reason, the capacitive insulating film DE of the capacitive element CP is a laminated film (that is, an insulating film) including the silicon oxide film 5a, the silicon nitride film 5b on the silicon oxide film 5a, and the silicon oxide film 5c on the silicon nitride film 5b. In FIG. 3, the laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c is simply shown as a capacitive insulating film DE in order to make the drawing easy to see.

  The capacitive insulating film DE and the upper electrode UE are patterned as a laminated pattern, and are formed so as to cover at least a part of the lower electrode LE.

  The upper electrode UE of the capacitor formation region 1C is formed of a conductor film in the same layer as the memory gate electrode MG of the memory cell region 1A and the memory gate shunt region 1B. That is, the upper electrode UE of the capacitor formation region 1C includes a silicon film (6a) that is the same layer as the silicon film 6a that forms the memory gate electrode MG, and the silicon film 6b that is formed on the silicon film 6b and forms the memory gate electrode MG. It is formed of a laminated film with the same silicon film (6b). That is, the memory gate electrode MG and the upper electrode UE are both formed of a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a. As described above, the silicon film 6a constituting the memory gate electrode MG and the upper electrode UE is made of a non-doped (undoped) silicon film into which impurities are not intentionally introduced, and the memory gate electrode MG and the upper electrode UE The constituent silicon film 6b is made of a silicon film into which impurities are intentionally introduced.

  The memory gate electrode MG and the upper electrode UE are formed on the main surface of the semiconductor substrate 1 including the memory cell region 1A, the memory gate shunt region 1B, and the capacitor formation region 1C so as to cover the control gate electrode CG and the lower electrode LE. , 6b is formed, and then the laminated film is anisotropically etched. At this time, the upper electrode UE forms a resist pattern (corresponding to a photoresist pattern RP1 described later) on the laminated film (that is, the laminated film of the silicon films 6a and 6b) before this anisotropic etching, It is formed by leaving a laminated film (that is, a laminated film of silicon films 6a and 6b) under this resist pattern. For this reason, the upper electrode UE is formed of a patterned laminated film (that is, a laminated film of the silicon films 6a and 6b).

  A capacitive element (PIP type capacitive element) CP is formed by the lower electrode LE, the capacitive insulating film DE, and the upper electrode UE. The lower electrode LE functions as one electrode (first electrode) of the capacitive element CP, the upper electrode UE functions as the other electrode (second electrode) of the capacitive element CP, and the capacitive insulating film DE functions as a dielectric of the capacitive element CP. Functions as a body membrane. The sidewall insulating film SW is also formed on the side surface of the upper electrode UE and on the side surface of the lower electrode LE in a region not covered with the stacked pattern of the capacitive insulating film DE and the upper electrode UE. The metal silicide layer 11 includes an upper portion (upper surface) of the upper electrode UE in a region not covered with the sidewall insulating film SW and a lower electrode LE in a region not covered with the stacked pattern of the capacitor insulating film DE and the upper electrode UE. It is also formed on the upper part (upper surface).

  Note that the laminated pattern of the capacitive insulating film DE and the upper electrode UE does not cover the entire surface of the lower electrode LE, but in a cross section different from that of FIG. The electrode UE is not covered with the laminated pattern. This is because a later-described plug PG can be connected to the lower electrode LE in a region not covered with the laminated pattern of the capacitive insulating film DE and the upper electrode UE.

  The capacitive element CP is a so-called PIP (Polysilicon Insulator Polysilicon) type capacitive element. Here, the PIP type capacitive element is a capacitive element comprising two polysilicon layers (here, lower electrode LE and upper electrode UE) and an insulating film (here, capacitive insulating film DE) sandwiched between them. (Polysilicon capacitor).

  On the semiconductor substrate 1, an insulating film 12 is formed as an interlayer insulating film so as to cover the control gate electrode CG, the memory gate electrode MG, the lower electrode LE, the upper electrode UE, and the sidewall insulating film SW. The insulating film 12 is made of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film formed thicker than the silicon nitride film on the silicon nitride film. The upper surface of the insulating film 12 is planarized.

  A contact hole (opening, through-hole) CNT is formed in the insulating film 12, and a conductive plug PG is embedded as a conductor portion (connecting conductor portion) in the contact hole CNT.

  The plug PG is formed of a thin barrier conductor film 13a formed on the bottom and side walls of the contact hole CNT, and a main conductor film 13b formed so as to bury the contact hole CNT on the barrier conductor film 13a. The barrier conductor film 13a can be, for example, a titanium film, a titanium nitride film, or a laminated film thereof, and the main conductor film 13b can be a tungsten film.

The contact hole CNT and the plug PG embedded therein are formed on the n ⁺ type semiconductor regions 8a and 8b, the control gate electrode CG, the memory gate electrode MG, the lower electrode LE, and the upper electrode UE. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor regions 8a and 8b (the metal silicide layer 11 on the surface thereof), a metal on the surface of the control gate electrode CG (the surface on the surface). Part of the silicide layer 11), part of the contact portion MGa (the metal silicide layer 11 on the surface thereof) of the memory gate electrode MG, part of the lower electrode LE (the metal silicide layer 11 on the surface thereof), the upper electrode UE A part of (metal silicide layer 11 on the surface) is exposed. The plug PG is connected to the exposed portion (exposed portion at the bottom of the contact hole CNT).

In FIG. 1, a part of the n ⁺ -type semiconductor region 8b (the metal silicide layer 11 on the surface thereof) is exposed at the bottom of the contact hole CNT and electrically connected to the plug PG filling the contact hole CNT. Connected cross sections are shown. In FIG. 2, the contact portion MGa (the metal silicide layer 11 on the surface thereof) of the memory gate electrode MG is exposed at the bottom of the contact hole CNT (this contact hole CNT is referred to as a contact hole CNT1). A cross section electrically connected to a plug PG filling the contact hole CNT1 (this plug PG is referred to as a plug PG1) is shown. Further, in FIG. 3, a part of the upper electrode UE (the metal silicide layer 11 on the surface thereof) is exposed at the bottom of the contact hole CNT and electrically connected to the plug PG filling the contact hole CNT. A cross section is shown.

  As shown in FIG. 2, in the contact portion MGa, a contact hole CNT1 of the contact holes CNT is formed above the flat portion located on the element isolation region 2, and is buried in the contact hole CNT1. The plug PG1 is electrically connected to the contact part MGa. Plug PG1 is electrically connected in contact with contact portion MGa of memory gate electrode MG at the bottom of contact hole CNT1. When the metal silicide layer 11 is formed on the memory gate electrode MG, as shown in FIG. 2, the plug PG1 embedded in the contact hole CNT1 is a metal on the contact portion MGa at the bottom of the contact hole CNT1. It is in contact with and electrically connected to the silicide layer 11, thereby being electrically connected to the memory gate electrode MG (contact portion MGa thereof).

  A wiring (wiring layer) M1 is formed on the insulating film 12 in which the plug PG is embedded. The wiring M1 is, for example, a damascene wiring (embedded wiring), and is embedded in a wiring groove provided in the insulating film 14 formed on the insulating film 12. The wiring M1 is connected via a plug PG to the source region (semiconductor region MS) of the memory transistor, the drain region (semiconductor region MD) of the control transistor, the control gate electrode CG, the memory gate electrode MG, the upper electrode UE, the lower electrode LE, and the like. And electrically connected. In FIG. 1, as an example of the wiring M1, a wiring M1a electrically connected to the drain region (semiconductor region MD) of the control transistor via the plug PG is shown. In FIG. 2, the memory gate electrode MG is shown. A wiring M1b electrically connected to the (contact portion MGa) via the plug PG1 is shown. In FIG. 3, a wiring M1c electrically connected to the upper electrode UE via the plug PG is shown. Yes. Further, upper wirings and insulating films are also formed, but their illustration and description are omitted here. Further, the wiring M1 and the wiring above it are not limited to damascene wiring (embedded wiring), and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring. You can also.

  FIG. 5 is an equivalent circuit diagram of the memory cell MC. FIG. 6 is a table showing an example of voltage application conditions to each portion of the selected memory cell at the time of “write”, “erase”, and “read” in the present embodiment. The table in FIG. 6 shows the voltage applied to the memory gate electrode MG of the memory cell (selected memory cell) as shown in FIGS. 1 and 4 at the time of “write”, “erase”, and “read”. Vmg, voltage Vs applied to the source region (semiconductor region MS), voltage Vcg applied to the control gate electrode CG, voltage Vd applied to the drain region (semiconductor region MD), and voltage Vb applied to the p-type well PW. Are listed. The table shown in the table of FIG. 6 is a preferred example of the voltage application conditions, and is not limited to this, and various changes can be made as necessary. In the present embodiment, the electron injection into the silicon nitride film 5b which is the charge storage layer (charge storage portion) in the insulating film 5 of the memory transistor is “writing”, and the hole is injected. Is defined as “erase”.

  As the writing method, hot electron writing called a so-called SSI (Source Side Injection) method can be used. For example, a voltage as shown in the “write” column of FIG. 6 is applied to each part of the selected memory cell to be written, and electrons (electrons) are contained in the silicon nitride film 5b in the insulating film 5 of the selected memory cell. Inject. Hot electrons are generated in the channel region (between the source and drain) between the two gate electrodes (memory gate electrode MG and control gate electrode CG), and the charge storage layer in the insulating film 5 below the memory gate electrode MG. Hot electrons are injected into the silicon nitride film 5b which is a (charge storage portion). The injected hot electrons (electrons) are captured by the trap level in the silicon nitride film 5b in the insulating film 5, and as a result, the threshold voltage of the memory transistor rises.

  As an erasing method, a BTBT (Band-To-Band Tunneling) hot hole injection erasing method can be used. That is, erasing is performed by injecting holes generated by BTBT (interband tunneling phenomenon) into the charge storage portion (silicon nitride film 5b in the insulating film 5). For example, a voltage as shown in the “erase” column of FIG. 6 is applied to each part of a selected memory cell to be erased, and a hole (hole) is generated by a BTBT (Band-To-Band Tunneling) phenomenon to generate an electric field. By accelerating, holes are injected into the silicon nitride film 5b in the insulating film 5 of the selected memory cell, thereby lowering the threshold voltage of the memory transistor.

  At the time of reading, for example, a voltage as shown in the “read” column in FIG. 6 is applied to each part of the selected memory cell to be read. By setting the voltage Vmg applied to the memory gate electrode MG at the time of reading to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage of the memory transistor in the erasing state, the writing state and the erasing state Can be discriminated.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described.

  FIG. 7 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the present embodiment. 8 to 44 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. 8 to 10 correspond to the same process steps, FIGS. 11 to 13 correspond to the same process steps, FIGS. 14 to 16 correspond to the same process steps, and FIGS. Corresponds to the same process step, FIGS. 22 to 24 correspond to the same process step, and FIGS. 25 to 27 correspond to the same process step. 28 to 30 correspond to the same process steps, FIGS. 31 and 32 correspond to the same process steps, FIGS. 33 to 35 correspond to the same process steps, and FIGS. 39 to 41 correspond to the same process step, and FIGS. 42 to 44 correspond to the same process step. 8 to 44, FIGS. 8, 11, 14, 17, 17, 22, 25, 28, 31, 33, 36, 39, and 42 are the same as those shown in FIG. 1 is shown (a cross-sectional view of the main part of the memory cell region 1A). 8 to 44, FIG. 9, FIG. 12, FIG. 15, FIG. 18, FIG. 23, FIG. 26, FIG. 29, FIG. 2 is shown (a cross-sectional view of the main part of the memory gate shunt region 1B). 8 to 44, FIGS. 10, 13, 16, 19, 24, 27, 30, 30, 35, 38, 41 and 44 correspond to FIG. 3 above. A cross-sectional area (a cross-sectional view of the main part of the capacitor forming area 1C) is shown. 20 is a partially enlarged cross-sectional view of FIG. 17, and FIG. 21 is a partially enlarged cross-sectional view of FIG.

  As shown in FIGS. 8 to 10, first, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, is prepared (prepared) (step of FIG. 7). S1). Then, an element isolation region (inter-element isolation insulating region) 2 that defines (defines) an active region is formed on the main surface of the semiconductor substrate 1 (step S2 in FIG. 7). The element isolation region 2 is made of an insulator such as silicon oxide, and can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 may be formed by forming an element isolation groove in the main surface of the semiconductor substrate 1 and then embedding an insulating film made of, for example, silicon oxide in the element isolation groove. it can. In the memory gate shunt region 1B and the capacitor formation region 1C, the element isolation region 2 is formed over the entire main surface of the semiconductor substrate 1.

  Next, a p-type well PW is formed in the memory cell region 1A of the semiconductor substrate 1 (step S3 in FIG. 7). The p-type well PW can be formed, for example, by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate 1. The p-type well PW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth.

  Next, in order to adjust the threshold voltage of a control transistor formed later in the memory cell region 1A, a channel is formed with respect to the surface portion (surface layer portion) of the p-type well PW in the memory cell region 1A as necessary. Dope ion implantation is performed.

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type well PW) by dilute hydrofluoric acid cleaning or the like, as shown in FIGS. 11 to 13, the main surface of the semiconductor substrate 1 (surface of the p-type well PW) ), An insulating film 3 for the gate insulating film (for the gate insulating film of the control transistor) is formed (step S4 in FIG. 7). The insulating film 3 can be formed of, for example, a thin silicon oxide film or a silicon oxynitride film. The film thickness (formed film thickness) of the insulating film 3 can be set to, for example, about 2 to 3 nm. When the insulating film 3 is formed by the thermal oxidation method, the insulating film 3 is not formed on the element isolation region 2.

  Next, on the entire main surface of the semiconductor substrate 1, that is, on the insulating film 3 in the memory cell region 1A and on the element isolation region 2 in the memory gate shunt region 1B and capacitor forming region 1C, A silicon film 4 is formed (deposited) as a conductor film that also serves to form the lower electrode LE (step S5 in FIG. 7).

  The silicon film 4 is made of a polycrystalline silicon film and can be formed using a CVD (Chemical Vapor Deposition) method or the like. The film thickness (deposited film thickness) of the silicon film 4 can be set to about 100 to 200 nm, for example. At the time of film formation, the silicon film 4 can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  The silicon film 4 has a low resistivity by introducing n-type impurities (for example, arsenic (As) or phosphorus (P)). The n-type impurity may be introduced into the silicon film 4 during or after the formation of the silicon film 4. In the case of introducing an n-type impurity during the formation of the silicon film, the n-type impurity is introduced by including a doping gas (a gas for adding an n-type impurity) in the gas for forming the silicon film 4. A silicon film 4 can be formed. On the other hand, when an n-type impurity is introduced after the formation of the silicon film, the silicon film is intentionally formed without introducing the impurity, and then the n-type impurity is introduced into the silicon film by an ion implantation method or the like. As a result, the silicon film 4 into which the n-type impurity is introduced can be formed. In any case, the silicon film 4 into which n-type impurities are introduced is formed in the memory cell region 1A, the memory gate shunt region 1B, and the capacitor formation region 1C.

  Next, as shown in FIGS. 14 to 16, the silicon film 4 in the memory cell region 1 </ b> A, the memory gate shunt region 1 </ b> B, and the capacitor formation region 1 </ b> C is patterned by patterning using a photolithography technique and a dry etching technique. A gate electrode CG and a lower electrode LE are formed (step S6 in FIG. 7). The patterning process in step S6 can be performed as follows, for example.

  That is, a photoresist pattern is formed on the silicon film 4 using a photolithography method (although not shown here, this photoresist pattern is formed in the control gate electrode CG formation planned region and the lower electrode LE formation planned region). Then, using this photoresist pattern as an etching mask, the silicon film 4 is patterned by etching (dry etching). Thereafter, the photoresist pattern is removed.

  In this way, the silicon film 4 is patterned in step S6, and as shown in FIGS. 14 and 15, the control gate electrode CG made of the patterned silicon film 4 is formed in the memory cell region 1A and the memory gate shunt region 1B. As shown in FIG. 16, the lower electrode LE made of the patterned silicon film 4 is formed in the capacitor forming region 1C. The control gate electrode CG and the lower electrode LE are made of the same silicon film 4 but are separated from each other. In the memory cell region 1A, the insulating film 3 remaining under the control gate electrode CG becomes a gate insulating film of the control transistor. Therefore, the control gate electrode CG made of the silicon film 4 is formed on the semiconductor substrate 1 (p-type well PW) via the insulating film 3 as a gate insulating film. In the memory gate shunt region 1B, the control gate electrode CG is formed on the element distribution region 2.

  The insulating film 3 other than the portion covered with the control gate electrode CG (that is, the insulating film 3 other than the portion serving as the gate insulating film) is subjected to dry etching performed in the patterning process of step S6 or wet etching after the dry etching. Can be removed.

  Next, in order to adjust the threshold voltage of a memory transistor to be formed later in the memory cell region 1A, a channel is formed with respect to the surface portion (surface layer portion) of the p-type well PW in the memory cell region 1A as necessary. Dope ion implantation is performed.

  Next, after performing a cleaning process to clean the main surface of the semiconductor substrate 1, as shown in FIGS. 17 to 21, the main surface of the semiconductor substrate 1 and the surface of the control gate electrode CG (upper surface and side surface). ) And the surface (upper surface and side surface) of the lower electrode LE, the insulating film 5 serving as both the gate insulating film of the memory transistor and the capacitive insulating film of the capacitive element is formed (step S7 in FIG. 7). 20 and FIG. 21 are partially enlarged cross-sectional views in which a part of FIG. 17 and FIG. 19 is enlarged, respectively, and FIG. 20 shows a part of the memory cell region 1A in an enlarged manner. In FIG. 2, a part of the capacitor formation region 1C is enlarged.

  As described above, the insulating film 5 is an insulating film having a charge storage portion (charge storage layer) inside, and as the insulating film, the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film formed in order from the bottom. In order to make the drawings easy to see, in FIG. 17 to FIG. 19, the stacked film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c is simply shown as the insulating film 5. . Therefore, actually, as shown in FIGS. 20 and 21, the insulating film 5 includes a silicon oxide film (oxide film) 5a, a silicon nitride film (nitride film) 5b on the silicon oxide film 5a, and silicon nitride. It consists of a laminated film with a silicon oxide film (oxide film) 5c on the film 5b. In step S7, as shown in FIGS. 17 to 21, the insulating film 5 includes the main surface (surface) of the semiconductor substrate 1 (including the p-type well PW and the element isolation region 2) and the surface of the control gate electrode CG (surface). (Side surface and upper surface) and the surface (side surface and upper surface) of the lower electrode LE (however, the insulating film 5 is not formed on the lower portion of the control gate electrode CG and the lower portion of the lower electrode LE). In general, the insulating film 5 is also formed on the element isolation region 2 in the film forming process, but the insulating film 5 may not be formed on the element isolation region 2.

  Of the insulating film 5, the silicon oxide films 5a and 5c can be formed by, for example, an oxidation process (thermal oxidation process), a CVD method, or a combination thereof. It is possible to use ISSG (In Situ Steam Generation) oxidation for the oxidation treatment (thermal oxidation treatment) at this time. Of the insulating film 5, the silicon nitride film 5b can be formed by, for example, a CVD method.

  In the present embodiment, the silicon nitride film 5b is formed as an insulating film (charge storage layer) having a trap level. However, a silicon nitride film is preferable in terms of reliability. The charge storage layer (charge storage portion) is not limited to a silicon film, and a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, such as an aluminum oxide film (alumina), a hafnium oxide film, or a tantalum oxide film, is used. It can also be used. In addition, a charge storage layer (charge storage portion) can be formed using silicon nanodots.

  In order to form the insulating film 5, for example, first, on the surface of the semiconductor substrate 1 (p-type well PW), on the surface (side surface and upper surface) of the control gate electrode CG, and on the surface (side surface and upper surface) of the lower electrode LE. After the silicon oxide film 5a is formed by a thermal oxidation method (preferably ISSG oxidation), a silicon nitride film 5b is deposited on the silicon oxide film 5a by a CVD method, and a silicon oxide film 5c is further formed on the silicon nitride film 5b. It is formed by CVD or thermal oxidation or both. Thereby, the insulating film 5 composed of a laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c can be formed.

  The thickness of the silicon oxide film 5a can be, for example, about 3 to 6 nm, the thickness of the silicon nitride film 5b can be, for example, about 5 to 10 nm, and the thickness of the silicon oxide film 5c can be, for example, 4 to 7 nm. Can be about. The last oxide film (the uppermost silicon oxide film 5c of the insulating film 5) is formed, for example, by oxidizing the upper layer portion of the nitride film (the intermediate silicon nitride film 5b of the insulating film 5). A high breakdown voltage film can also be formed.

  The insulating film 5 formed in the memory cell region 1A functions as a gate insulating film of a memory gate electrode MG to be formed later, has a charge holding (charge storage) function, and is formed in the capacitor forming region 1C. The insulating film 5 functions as a capacitive insulating film (dielectric film) of the capacitive element CP.

  Therefore, the insulating film 5 has a laminated structure of at least three layers so that it can function as a gate insulating film having a charge holding (charge accumulation) function of the memory transistor, and the outer layers (silicon oxide films 5a and 5c). The potential barrier height of the inner layer (silicon nitride film 5b) is lower than the potential barrier height. This is because, as in the present embodiment, the insulating film 5 includes a silicon oxide film 5a, a stacked film including a silicon nitride film 5b on the silicon oxide film 5a, and a silicon oxide film 5c on the silicon nitride film 5b. This can be achieved.

  Next, as shown in FIGS. 22 to 24, the memory cell region 1 </ b> A and the memory gate shunt region 1 </ b> B cover the control gate electrode CG on the entire main surface of the semiconductor substrate 1, that is, on the insulating film 5. In addition, the silicon film 6a is formed (deposited) so as to cover the lower electrode LE in the capacitor formation region 1C (step S8 in FIG. 7). Then, as shown in FIGS. 25 to 27, a silicon film 6b is formed (deposited) on the entire main surface of the semiconductor substrate 1, that is, on the silicon film 6a (step S9 in FIG. 7). 22 to 27 and subsequent FIGS. 28 to 44, as in FIGS. 17 to 19, the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c are stacked in order to make the drawings easy to see. The film is shown simply as an insulating film 5.

  The silicon film 6a is made of a polycrystalline silicon film and can be formed using a CVD method or the like. The thickness (deposited film thickness) t1 of the silicon film 6a is preferably about 10 to 30 nm. At the time of film formation, the silicon film 6a can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  The silicon film 6b is made of a polycrystalline silicon film and can be formed using a CVD method or the like. The thickness (deposited film thickness) t2 of the silicon film 6b is preferably about 20 to 40 nm. At the time of film formation, the silicon film 6b can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment. Although the reason will be described later, it is preferable to make the thickness (deposited film thickness) t2 of the silicon film 6b thicker (that is, t1 <t2) than the thickness (deposited film thickness) t1 of the silicon film 6a.

  The laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a is a conductor film that serves both for forming the memory gate electrode MG and for forming the upper electrode UE. Here, a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a is referred to as a laminated film 6.

  The silicon film 6a formed in step S8 is a non-doped (undoped) silicon film, and no impurity is intentionally introduced (added or doped) into the silicon film 6a when the silicon film 6a is formed. For this reason, in the formation (deposition) process of the silicon film 6a in step S8, the gas for forming the silicon film 6a does not include a doping gas (impurity addition gas). Further, in various ion implantation processes (for example, ion implantation processes in steps S13 and S15 described later) performed after the formation (deposition) process of the silicon film 6a in step S8, impurity ions are introduced (implanted) into the silicon film 6a as much as possible. It is preferable not to do so.

  On the other hand, the silicon film 6b formed in step S9 is a silicon film into which impurities are introduced (doped), and impurities are intentionally introduced (added or doped) into the silicon film 6b to have a low resistivity. ing. As a method for introducing impurities into the silicon film 6b, it is preferable to introduce impurities into the silicon film 6b when the silicon film 6b is formed (that is, depositing the silicon film 6b into which impurities are introduced in step S9). In this case, a doping gas (impurity addition gas) may be included in the gas for forming the silicon film 6b. Thereby, a laminated film of the non-doped silicon film 6a and the silicon film 6b doped with impurities can be obtained. Since the impurity introduced into the silicon film 6b is preferably an n-type impurity (for example, arsenic (As) or phosphorus (P)), the silicon film 6b is preferably an n-type polysilicon film (n-type doped poly-silicon). Silicon film).

  In this manner, the laminated film 6 of the silicon films 6a and 6b is formed on the main surface of the semiconductor substrate 1 including the memory cell region 1A, the memory gate shunt region 1B, and the capacitor forming region 1C. At the stage where the silicon films 6a and 6b are formed, the silicon film 6a is formed as a non-doped silicon film, whereas the silicon film 6b is formed as a silicon film into which an n-type impurity is introduced. Therefore, the impurity concentration of the silicon film 6b is higher than the impurity concentration of the silicon film 6a, and the resistivity (specific resistance) of the silicon film 6b is lower than the resistivity (specific resistance) of the silicon film 6a.

  Next, using the photolithography method, on the silicon film 6b in the region where the contact portion MGa of the memory gate electrode MG is to be formed in the memory gate shunt region 1B, and on the silicon film 6b in the region where the upper electrode UE is to be formed in the capacitor formation region 1C At the same time, a photoresist pattern RP1 is formed as a resist pattern. Here, as shown in FIG. 26, in the memory gate shunt region 1B, the photoresist pattern RP1 formed in the region where the contact portion MGa is to be formed of the memory gate electrode MG is denoted by a reference numeral RP1a and is referred to as a photoresist pattern RP1a. I will do it. Further, as shown in FIG. 27, the photoresist pattern RP1 formed in the upper electrode UE formation scheduled region in the capacitor forming region 1C is referred to as a photoresist pattern RP1b with reference numeral RP1b. Accordingly, the photoresist pattern RP1a and the photoresist pattern RP1b are composed of the same layer of the photoresist pattern RP1 formed in the same process (that is, the same photolithography process), but are separated from each other.

  Next, as shown in FIGS. 28 to 30, the silicon film 6b and the silicon film 6a are etched back (etching, dry etching, anisotropic etching) by anisotropic etching technique (step S10 in FIG. 7). After the etch back process in step S10, the photoresist pattern RP1 (that is, the photoresist patterns RP1a and RP1b) is removed. 28 to 30 show a stage before the removal of the photoresist pattern RP1.

  In the etch back process of step S10, both the control gate electrodes CG are obtained by anisotropically etching (etching back) the laminated film 6 (that is, the silicon film 6b and the silicon film 6a) by the amount of the deposited film thickness of the laminated film 6. The laminated film 6 is left in the shape of a sidewall spacer on the side wall of the insulating film 5, the laminated film 6 is left under the photoresist pattern RP 1, and the laminated film in other regions is removed. As a result, as shown in FIG. 28, in the memory cell region 1A, the stacked film 6 remaining in the sidewall spacer via the insulating film 5 on one of the sidewalls of the control gate electrode CG, A memory gate electrode MG is formed, and a silicon spacer SP1 is formed by the laminated film 6 remaining in the shape of a side wall spacer on the other side wall via the insulating film 5. The silicon spacer SP1 can be regarded as a sidewall spacer made of silicon. The memory gate electrode MG and the silicon spacer SP1 are formed on the side walls opposite to each other of the control gate electrode CG, and have a substantially symmetrical structure with the control gate electrode CG interposed therebetween.

  Further, in the etch back process of step S10, the photoresist pattern RP1 (that is, the photoresist patterns RP1a and RP1b) functions as an etching mask. Therefore, as shown in FIG. (1 resist pattern) The upper electrode UE is formed by the laminated film 6 that remains without being etched under the RP1b. Therefore, the upper electrode UE is formed by the laminated film 6 of the silicon film 6a and the silicon film 6b on the silicon film 6a. Further, as shown in FIG. 29, in the memory gate shunt region 1B, the contact portion MGa is formed by the laminated film 6 that remains without being etched under the photoresist pattern RP1a. Since the etch back process of step S10 is anisotropic etching, the formed contact portion MGa has the same pattern shape (planar shape) as the photoresist pattern RP1a, and the formed upper electrode UE is It has the same pattern shape (planar shape) as the photoresist pattern RP1b.

  An insulating film 5 is interposed between the memory gate electrode MG formed in step S10 and the semiconductor substrate 1 (p-type well PW) and between the memory gate electrode MG and the control gate electrode CG. The electrode MG is formed of a silicon film 6a that is in contact with the insulating film 5 and a silicon film 6b that is separated from the insulating film 5 via the silicon film 6a.

  In the stage where the etch-back process of step S10 is performed, the insulating film 5 in a region not covered with the memory gate electrode MG (including the contact portion MGa), the silicon spacer SP1, and the upper electrode UE is exposed. The insulating film 5 under the memory gate electrode MG in the memory cell region 1A becomes a gate insulating film of the memory transistor. The memory gate length (the gate length of the memory gate electrode MG) is determined by the deposited film thickness of the laminated film 6 (that is, the sum of the deposited film thickness of the silicon film 6a and the deposited film thickness of the silicon film 6b). The memory gate length can be adjusted by adjusting the total deposited film thickness (ie, t1 + t2) of the silicon films 6a and 6b deposited in (1).

  Next, using a photolithography technique, a photoresist pattern (not shown) that covers the memory gate electrode MG (including the contact portion MGa) and the upper electrode UE and exposes the silicon spacer SP1 is formed on the semiconductor substrate 1. After the formation, the silicon spacer SP1 is removed by dry etching using the photoresist pattern as an etching mask (step S11 in FIG. 7). Thereafter, the photoresist pattern is removed. FIG. 31 and FIG. 32 show this stage.

  As shown in FIGS. 31 and 32, the silicon spacer SP1 is removed by the etching process of step S11, but the memory gate electrode MG (including the contact portion MGa) and the upper electrode UE are covered with a photoresist pattern. Therefore, it remains without being etched.

  Next, as shown in FIG. 33 to FIG. 35, the insulating film 5 is etched (for example, wet etching) in the portion exposed without being covered with the memory gate electrode MG (including the contact portion MGa) and the upper electrode UE. (Step S12 in FIG. 7). At this time, in the memory cell region 1A and the memory gate shunt region 1B, the insulating film 5 located under the memory gate electrode MG and between the memory gate electrode MG and the control gate electrode CG remains without being removed, thereby forming a capacitor. In the region 1C, the insulating film 5 located under the upper electrode UE remains without being removed, and the insulating film 5 in other regions is removed. In the capacitor formation region 1C, the insulating film 5 remaining under the upper electrode UE becomes the capacitive insulating film DE of the capacitive element CP.

Next, an n-type impurity such as arsenic (As) or phosphorus (P) is used by using an ion implantation method or the like, and the semiconductor substrate 1 (p) using the control gate electrode CG and the memory gate electrode MG as an ion implantation blocking mask. By introducing (doping) into the type well PW), n ⁻ type semiconductor regions (impurity diffusion layers) 7a and 7b are formed (step S13 in FIG. 7).

At this time, the n ⁻ type semiconductor region 7a is self-aligned with the side wall of the memory gate electrode MG (side wall opposite to the side adjacent to the control gate electrode CG via the insulating film 5) in the memory cell region 1A. The n ⁻ type semiconductor region 7b formed is self-aligned with the side wall of the control gate electrode CG (the side wall opposite to the side adjacent to the memory gate electrode MG via the insulating film 5) in the memory cell region 1A. It is formed. The n ⁻ type semiconductor region 7a and the n ⁻ type semiconductor region 7b can function as a part of the source / drain region of the memory cell formed in the memory cell region 1A. The n ⁻ type semiconductor region 7a and the n ⁻ type semiconductor region 7b can be formed by the same ion implantation step, but can also be formed by different ion implantation steps.

  Next, as shown in FIGS. 36 to 38, on the side walls of the control gate electrode CG and the memory gate electrode MG (on the side opposite to the side adjacent to each other through the insulating film 5), for example, silicon oxide or the like Sidewall insulating films (sidewalls, sidewall spacers) SW made of this insulator are formed (step S14 in FIG. 7). For example, an insulating film such as a silicon oxide film is deposited on the entire main surface of the semiconductor substrate 1, and the insulating film is anisotropically etched (etched back) to thereby form the sidewalls of the control gate electrode CG and the memory gate electrode MG. The sidewall insulating film SW can be formed by selectively leaving the insulating film. As shown in FIG. 38, the sidewall insulating film SW can also be formed on the sidewall (side surface) of the upper electrode UE.

Next, an ion implantation method or the like is used to ionize n-type impurities such as arsenic (As) or phosphorus (P) to control gate electrode CG and memory gate electrode MG and side wall insulating film SW on the side walls. By introducing (doping) into the semiconductor substrate 1 (p-type well PW) using it as an implantation blocking mask, high impurity concentration n ⁺ -type semiconductor regions (impurity diffusion layers) 8a and 8b are formed (step S15 in FIG. 7). ).

At this time, the n ⁺ type semiconductor region 8a is formed in the memory cell region 1A in self-alignment with the sidewall insulating film SW on the side wall of the memory gate electrode MG, and the n ⁺ type semiconductor region 8b is formed in the memory cell region 1A. The self-alignment is formed on the sidewall insulating film SW on the sidewall of the control gate electrode CG. Thereby, an LDD structure is formed. The n ⁺ type semiconductor region 8a and the n ⁺ type semiconductor region 8b can be formed by the same ion implantation process, but can also be formed by different ion implantation processes.

n ^- the type semiconductor region 7a and the impurity concentration higher than that n ⁺ -type semiconductor regions 8a, n-type semiconductor region MS functioning as a source region of the memory transistor is formed, n ^- -type semiconductor regions 7b and than The n ⁺ type semiconductor region 8b having a high impurity concentration forms an n type semiconductor region MD that functions as a drain region of the control transistor (select transistor).

Next, activation is heat treatment for activating the impurities introduced into the n-type semiconductor regions MS and MD (n ⁻ -type semiconductor regions 7a and 7b and n ⁺ -type semiconductor regions 8a and 8b) for the source and drain. Annealing is performed (step S16 in FIG. 7).

  In this way, the memory cell MC of the nonvolatile memory is formed in the memory cell region 1A.

Next, etching (for example, wet etching using dilute hydrofluoric acid) is performed as necessary, and the upper surfaces (surfaces) of the n ⁺ -type semiconductor regions 8a and 8b, the upper surface of the control gate electrode CG, and the memory gate electrode MG. The upper surface (portion not covered with the sidewall insulating film SW), the upper surface of the upper electrode UE (portion not covered with the sidewall insulating film SW), and the upper surface of the lower electrode LE (covered with the capacitor insulating film DE and the upper electrode UE). (Excluded part) and clean (expose). The etching at this time can be light enough to remove the natural oxide film.

Next, as shown in FIGS. 39 to 41, the salicide technique is used to control the control gate electrode CG, the memory gate electrode MG, the n ⁺ type semiconductor regions 8a and 8b, and the upper portion of the upper electrode UE (upper surface, surface, upper layer). The metal silicide layer (metal silicide film) 11 is formed on each of the portions (step S17 in FIG. 7). By forming the metal silicide layer 11, diffusion resistance, contact resistance, and the like can be reduced. The metal silicide layer 11 can be formed as follows.

First, the control gate electrode CG, the memory gate electrode, over the entire main surface of the semiconductor substrate 1 including the control gate electrode CG, the memory gate electrode MG, the upper electrode UE, and the upper surfaces (surfaces) of the n ⁺ -type semiconductor regions 8a, 8b. A metal film (not shown) is formed (deposited) so as to cover MG, upper electrode UE, and sidewall insulating film SW. This metal film is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like. Then, by subjecting the semiconductor substrate 1 to heat treatment, the control gate electrode CG, the memory gate electrode MG, the upper electrode UE, and the upper layer portions (surface layer portions) of the n ⁺ type semiconductor regions 8a and 8b are reacted with the metal film. . As a result, the metal silicide layers 11 are formed on the control gate electrode CG, the memory gate electrode MG, the upper electrode UE, and the upper portions (upper surface, surface, upper layer portion) of the n ⁺ type semiconductor regions 8a and 8b, respectively. The metal silicide layer 11 can be, for example, a cobalt silicide layer (when the metal film is a cobalt film) or a nickel silicide layer (when the metal film is a nickel film). Thereafter, the unreacted metal film is removed. 39 to 41 show cross-sectional views at this stage. Further, although not shown in the cross-sectional view of FIG. 41, the metal silicide layer 11 can be formed in a region of the upper surface of the lower electrode LE that is not covered with the stacked pattern of the upper electrode UE and the capacitive insulating film DE.

  Next, as shown in FIGS. 42 to 44, the control gate electrode CG, the memory gate electrode MG, the lower electrode LE, the upper electrode UE, and the sidewall insulating film SW are covered over the entire main surface of the semiconductor substrate 1. An insulating film (interlayer insulating film) 12 is formed (deposited) as an interlayer insulating film. The insulating film 12 is composed of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film formed thicker than the silicon nitride film on the silicon nitride film. Can be formed. After the formation of the insulating film 12, the upper surface of the insulating film 12 is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary.

  Next, the insulating film 12 is dry-etched using a photoresist pattern (not shown) formed on the insulating film 12 by a photolithography method as an etching mask, whereby a contact hole (opening, penetrating through the insulating film 12). Hole) CNT is formed.

  Next, a conductive plug PG made of tungsten (W) or the like is formed in the contact hole CNT as a conductor portion (connection conductor portion).

  In order to form the plug PG, for example, the barrier conductor film 13a is formed on the insulating film 12 including the inside (on the bottom and side walls) of the contact hole CNT. The barrier conductor film 13a can be, for example, a titanium film, a titanium nitride film, or a laminated film thereof. Then, a main conductor film 13b made of a tungsten film or the like is formed on the barrier conductor film 13a so as to fill the contact holes CNT. By removing by a back method or the like, the plug PG can be formed.

The contact hole CNT and the plug PG embedded therein are formed on the n ⁺ type semiconductor regions 8a and 8b, the control gate electrode CG, the memory gate electrode MG, the lower electrode LE, and the upper electrode UE. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor regions 8a and 8b (the metal silicide layer 11 on the surface thereof), a metal on the surface of the control gate electrode CG (the surface on the surface). Part of the silicide layer 11), part of the memory gate electrode MG (metal silicide layer 11 on the surface thereof), part of the lower electrode LE (metal silicide layer 11 on the surface thereof), and on the surface of the upper electrode UE (on the surface) A part of the metal silicide layer 11) is exposed.

In FIG. 42, a part of the n ⁺ type semiconductor region 8b (the metal silicide layer 11 on the surface thereof) is exposed at the bottom of the contact hole CNT and electrically connected to the plug PG filling the contact hole CNT. Connected cross sections are shown. In FIG. 43, the contact portion MGa (the metal silicide layer 11 on the surface) of the memory gate electrode MG is exposed at the bottom of the contact hole CNT (this contact hole CNT is referred to as a contact hole CNT1). A cross section electrically connected to a plug PG filling the contact hole CNT1 (this plug PG is referred to as a plug PG1) is shown. In FIG. 44, a part of the upper electrode UE (the metal silicide layer 11 on the surface thereof) is exposed at the bottom of the contact hole CNT and electrically connected to the plug PG filling the contact hole CNT. A cross section is shown.

  Next, as shown in FIGS. 1 to 3, a wiring (wiring layer) M1 is formed on the insulating film 12 in which the plug PG is embedded. A case where the wiring M1 is formed using a damascene technique (here, a single damascene technique) will be described.

  First, as shown in FIGS. 1 to 3, an insulating film (interlayer insulating film) 14 is formed on the insulating film 12 in which the plug PG is embedded, and then the photolithography technique and the dry film are formed on the insulating film 14. A wiring trench (a trench in which the wiring M1 is embedded in the insulating film 14) is formed using an etching technique. Then, a barrier conductor film (for example, a titanium nitride film, a tantalum film, or a tantalum nitride film) is formed on the main surface of the semiconductor substrate 1 (that is, on the insulating film 14 including the bottom and side walls of the wiring trench). A copper seed layer is formed on the barrier conductor film by CVD or sputtering, and a copper plating film is further formed on the seed layer by electrolytic plating or the like, and the inside of the wiring trench is filled with the copper plating film. Thereafter, the copper plating film, the seed layer, and the barrier metal film in a region other than the inside of the wiring trench are removed by CMP to form a first layer wiring M1 using copper as a main conductive material. The wiring M1 is embedded in the wiring groove of the insulating film 14. For simplification of the drawings, in FIGS. 1 to 3, the copper plating film, the seed layer, and the barrier conductor film constituting the wiring M1 are shown in an integrated manner.

  The wiring M1 is connected via a plug PG to the source region (semiconductor region MS) of the memory transistor, the drain region (semiconductor region MD) of the control transistor, the control gate electrode CG, the memory gate electrode MG (contact portion MGa thereof), and the upper electrode. It is electrically connected to the UE or the lower electrode LE.

  Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here. Further, the wiring M1 and the wiring above it are not limited to damascene wiring (embedded wiring), and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring. You can also.

  Next, features and effects of the present embodiment will be described in more detail.

  First, the semiconductor device of the first comparative example will be described. 45 and 46 are main part cross-sectional views of the semiconductor device of the first comparative example, and correspond to FIGS. 1 and 2 of the present embodiment, respectively.

The semiconductor device of the first comparative example shown in FIG. 45 and FIG. 46 is a semiconductor device having a memory cell of a nonvolatile memory, and constitutes a nonvolatile memory cell above the p-type well PW101 of the semiconductor substrate 101. Control gate electrode CG101 and memory gate electrode MG101 are formed adjacent to each other. An insulating film 103 as a gate insulating film is formed between the control gate electrode CG101 and the p-type well PW101. Further, an insulating film 105 made of a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is provided between the memory gate electrode MG101 and the p-type well PW101 and between the control gate electrode CG101 and the memory gate electrode MG101. Is formed. The control gate electrode CG101 is formed of a single film of the n-type polysilicon film 104 in which an n-type impurity is introduced to make the resistivity low. The memory gate electrode MG101 is formed of a single film of the polysilicon film 106. In the p-type well PW101, a semiconductor region functioning as a source region is formed by an n ⁻ -type semiconductor region 107a and an n ⁺ -type semiconductor region 108a having a higher impurity concentration than that, and a semiconductor region functioning as a drain region is formed The n ⁻ type semiconductor region 107b and the n ⁺ type semiconductor region 108b having a higher impurity concentration than that are formed. A side wall insulating film SW101 is formed on the side wall of the control gate electrode CG101 and the memory gate electrode MG101 opposite to the side adjacent to each other. A metal silicide layer 111 is formed on the n ⁺ type semiconductor regions 108a and 108b, the control gate electrode CG101, and the memory gate electrode MG101.

  The semiconductor device of the first comparative example having such a structure has the following problems.

  The memory gate electrode MG101 is formed of a single film of the polysilicon film 106. However, the memory gate electrode MG101 has a long wiring (memory gate electrode) when forming a memory cell array (a plurality of memory cells arranged in an array). It is desirable that the resistivity be low. From this viewpoint, it is preferable that the polysilicon film 106 constituting the memory gate electrode MG101 is an n-type doped polysilicon film having a low resistivity by introducing an n-type impurity.

  However, from the viewpoint of a memory element, it is desirable to reduce the impurity concentration of the polysilicon film 106 constituting the memory gate electrode MG101. This is because, when the impurity concentration of the memory gate electrode MG101 is lower, the electric field in the memory gate electrode MG101 in the vicinity of the insulating film 105 during charge retention is reduced due to depletion of the memory gate electrode MG101 adjacent to the insulating film 105. Accordingly, the memory from the charge storage layer (corresponding to the silicon nitride film in the insulating film 105 in the case of the semiconductor device of the first comparative example and corresponding to the silicon nitride film 5b in the case of the semiconductor device of the present embodiment). This is because charges are less likely to move to the gate electrode MG101 and the phenomenon of data inversion can be suppressed, which is advantageous in terms of data retention characteristics.

  Therefore, if a non-doped polysilicon film is used for the polysilicon film 106 constituting the memory gate electrode MG101, the data retention characteristics of the nonvolatile memory can be improved. However, if the memory gate electrode MG101 is formed with a single film of the non-doped polysilicon film 106, the entire memory gate electrode MG101 has a high resistivity, which deteriorates the performance of the semiconductor device having a nonvolatile memory. there is a possibility.

  In addition, it is conceivable to reduce the resistance of the memory gate electrode MG101 by forming the metal silicide layer 111 on the upper portion of the memory gate electrode MG101 by using the salicide technique. However, as shown in FIG. 46, the contact portion MG101a of the memory gate electrode MG101 (the portion corresponding to the contact portion MGa in the present embodiment) has a step, and therefore on the side wall (side surface) of the step of the contact portion MG101a. A sidewall insulating film SW101 (this sidewall insulating film SW101 is referred to as a sidewall insulating film SW101a) is formed. Therefore, even if the metal silicide layer 111 is formed on the memory gate electrode MG101 by the salicide technique, the metal silicide layer 111 formed on the contact portion MG101a is divided by the sidewall insulating film SW101a, and the level difference of the contact portion MG101a. The metal layer 111 is not formed on the side wall of the semiconductor device and on the lower side of the side wall insulating film SW101a. For this reason, when the polysilicon film 106 constituting the memory gate electrode MG101 is formed of a non-doped polysilicon film, even if the metal silicide layer 111 is formed by the salicide technique, the metal silicide layer 111 is not formed and the low thickness is reduced. A high resistance region RG101 in which it is difficult to obtain the effect of resistance is generated in the contact portion MG101a.

  The high resistance region RG101 is generated in a region adjacent to the control gate electrode CG101 through the insulating film 105. The memory gate electrode MG101 in a region other than the contact portion MG101a is formed in a sidewall spacer shape on the side wall of the control gate electrode CG via the insulating film 5. The sidewall spacer-shaped memory gate electrode MG101 is Since the contact portion MG101a is integrally connected to the high resistance region RG101, the presence of the high resistance region RG101 in the contact portion MG101a increases the resistance of the memory gate electrode MG. This may reduce the performance of the semiconductor device having a nonvolatile memory.

  On the other hand, in the present embodiment, as shown in FIGS. 1, 2 and 4, the memory gate electrode MG is formed of a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a. is doing. Therefore, in the memory gate electrode MG, the silicon film 6a and the silicon film 6b can be regarded as silicon regions (first silicon region and second silicon region), respectively. In the memory gate electrode MG, a region adjacent to the insulating film 5 (first silicon region) is configured by the silicon film 6a, and the memory gate electrode MG is insulated via the region (region configured by the silicon film 6a, first silicon region). A region (second silicon region) separated from the film 5 is in a state constituted by the silicon film 6b. Therefore, in the memory gate electrode MG, the silicon film 6a can be regarded as a region (first silicon region) adjacent to the insulating film 5, and the silicon film 6b is the region composed of the silicon film 6a (first silicon region). It can be regarded as a region (second silicon region) that is separated from the insulating film 5 via a region).

  Specifically, the positions of the silicon films 6a and 6b will be described. Between the silicon film 6b (second silicon region) of the memory gate electrode MG and the semiconductor substrate 1 (the p-type well PW), the insulating film 5 and the memory gate are provided. The silicon film 6a (first silicon region) of the electrode MG is interposed, and the insulating film 5 and the memory gate electrode MG are interposed between the silicon film 6b (second silicon region) of the memory gate electrode MG and the control gate electrode CG. The silicon film 6a (first silicon region) is interposed. The silicon film 6 b (second silicon region) of the memory gate electrode MG is not in contact with the insulating film 5.

  In this embodiment, the silicon film 6a is formed of a non-doped silicon film, and the silicon film 6b is formed of a silicon film into which impurities are introduced (doped). Since the region (first silicon region) adjacent to the insulating film 5 in the memory gate electrode MG is formed of the non-doped silicon film 6a, the region adjacent to the memory gate insulating film (here, the insulating film 5) (that is, the silicon film) 6a) has a low impurity concentration. For this reason, since the impurity concentration in the region adjacent to the memory gate insulating film (here, the insulating film 5) (ie, the silicon film 6a) is low, the memory in the vicinity of the memory gate insulating film (here, the insulating film 5) at the time of charge retention. The electric field in the gate electrode MG is relaxed, and it becomes difficult for charges to move from the charge storage layer (here, the silicon nitride film 5b) to the memory gate electrode MG, so that the data retention characteristics of the nonvolatile memory can be improved.

  Further, in the present embodiment, in the memory gate electrode MG, impurities are introduced into a region (second silicon region) separated from the insulating film 5 via a region (first silicon region) formed of the silicon film 6a ( Since the doped silicon film 6b is formed, the impurity concentration is high and the resistivity is low. For this reason, the resistance of the memory gate electrode MG can be reduced, and the operation speed of the nonvolatile memory can be improved. The memory gate electrode MG is formed of a long wiring (a plurality of memory cells arranged in the extending direction of the memory gate electrode MG) when forming a memory cell array (a plurality of memory cells arranged in an array). Although the wiring can also be reduced in resistance, the operation speed of the nonvolatile memory can be improved. Therefore, the performance of the nonvolatile memory can be improved.

  Further, by forming the metal silicide layer 11 on the memory gate electrode MG using the salicide technique, the resistance of the memory gate electrode MG can be reduced. In this case, as shown in FIG. Since there is a step in the contact part MGa of the gate electrode MG, a side wall insulating film SW (this side wall insulating film SW is referred to as a side wall insulating film SWa) is formed on the side wall (side surface) of the step of the contact part MGa. For this reason, even if the metal silicide layer 11 is formed on the memory gate electrode MG by the salicide technique, the metal silicide layer 11 formed on the contact portion MGa is divided by the sidewall insulating film SWa, and the level difference of the contact portion MGa. The metal silicide layer 11 is not formed on the side wall of the semiconductor device and on the lower side of the side wall insulating film SWa. However, in this embodiment, since the silicon film 6b is a silicon film into which impurities are introduced (doped), the silicon film 6b can have a low resistivity. Therefore, in the present embodiment, even if the metal silicide layer 11 is not formed on the side wall of the step of the contact portion MGa and the lower portion of the side wall insulating film SWa, the silicon film 6b has a low resistivity. Generation of the high resistance region RG101 as in the semiconductor device of the first comparative example of FIG. 46 can be suppressed or prevented. Accordingly, it is possible to suppress or prevent the generation of the high resistance portion in the memory gate electrode MG, and it is possible to improve the operation speed of the nonvolatile memory and improve the performance of the semiconductor device having the nonvolatile memory.

  As described above, in the present embodiment, the memory gate electrode MG is formed of a stacked film of the silicon film 6a and the silicon film 6b on the silicon film 6a, and the silicon film 6a is a non-doped silicon film, so that the nonvolatile memory is formed. The resistance of the memory gate electrode MG is lowered by improving the data retention characteristics of the memory and making the silicon film 6b a silicon film doped with impurities. Thereby, the performance of the semiconductor device having a nonvolatile memory can be improved.

  Further, from the viewpoint of improving the data retention characteristics by suppressing the phenomenon that charges (electrons or holes) stored in the charge storage layer (here, the silicon nitride film 5b) move to the memory gate electrode MG to invert data, The thickness (deposited film thickness) t1 of the silicon film 6a shown in FIGS. 22 to 24 is preferably 10 nm or more. By setting the thickness t1 of the silicon film 6a to 10 nm or more (that is, t1 ≧ 10 nm), it is possible to accurately suppress the above phenomenon and improve the data retention characteristics. The thickness t1 is the gate length of the memory gate electrode MG of the silicon film 6a formed between the control gate electrode CG and the silicon film 6b in FIG. 1 showing the nonvolatile memory cell of the present embodiment after manufacture. It corresponds to the thickness (film thickness) in the direction. From the viewpoint of reducing the resistance of the memory gate electrode MG, the thickness (deposited film thickness) t2 of the silicon film 6b shown in FIGS. 25 to 27 is 20 nm or more (that is, t2 ≧ 20 nm). preferable. The thickness t2 is the thickness in the gate length direction of the memory gate electrode MG in the region in contact with the silicon film 6a on the lower surface of the silicon film 6b in FIG. Thickness).

  Further, since the memory gate length (gate length of the memory gate electrode MG) is determined by the sum of the thickness t1 of the silicon film 6a and the thickness t2 of the silicon film 6b, the total thickness of the silicon film 6a and the silicon film 6b. (I.e., t1 + t2) is designed to have a dimension capable of obtaining an optimum memory gate length. When the total thickness corresponding to the optimum memory gate length (ie, t1 + t2) is distributed between the thickness t1 of the silicon film 6a and the thickness t2 of the silicon film 6b, more than half of the total thickness of the silicon film 6b is used. It is preferable to distribute to the thickness t2 and distribute the remainder to the thickness t1 of the silicon film 6a. That is, it is preferable to make the thickness (deposited film thickness) t2 of the silicon film 6b thicker (that is, t1 <t2) than the thickness (deposited film thickness) t1 of the silicon film 6a. Since the larger the ratio of the thickness t2 of the silicon film 6b to the total thickness of the silicon film 6a and the silicon film 6b (ie, t1 + t2), the more advantageous it is to reduce the resistance of the gate electrode MG, the silicon film 6a By making the thickness (deposited film thickness) t2 of the silicon film 6b thicker (that is, t1 <t2) than the thickness (deposited film thickness) t1, the gate electrode MG can be efficiently reduced in resistance. . Even if the thickness t1 of the silicon film 6a is smaller than the thickness t2 of the silicon film 6b (ie, t1 <t2), the thickness t1 of the silicon film 6a is 10 nm or more (ie, t1 ≧ 10 nm) as described above. If so, the effect of improving the data retention characteristics can be obtained accurately. For this reason, in FIG. 1 which shows the non-volatile memory cell of this Embodiment after manufacture, it is preferable that the relationship of t1 <t2 is satisfied.

  In the present embodiment, a non-volatile memory (memory cell MC thereof) and a capacitor element CP are formed (mixed) on the same semiconductor substrate 1. The lower electrode LE of the capacitive element CP is formed of the silicon film 4 in the same layer as the control gate electrode CG. The capacitive insulating film DE of the capacitive element CP is formed of the same insulating film 5 as the memory gate insulating film (insulating film 5 in the memory cell region 1A) of the memory transistor. The upper electrode UE of the capacitive element CP is formed of silicon films 6a and 6b in the same layer as the memory gate electrode MG. That is, both the memory gate electrode MG and the upper electrode UE are formed by a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a. In other words, the laminated film 6 (a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a) is used for the memory gate MG of the memory transistor and the upper electrode UE of the capacitive element CP. However, the laminated film 6 constituting the memory gate MG and the laminated film 6 constituting the upper electrode UE are integrated at the stage where the silicon films 6a and 6b are formed in the steps S8 and S9. Since it is separated in S10, it is separated in the manufactured semiconductor device.

  Unlike the present embodiment, when the memory gate electrode MG101 is formed of a single film of the polysilicon film 106 as in the semiconductor device of the first comparative example shown in FIGS. The electrode (corresponding to the upper electrode UE) is also formed by a single film of the polysilicon film 106. Since the electrode of the capacitor element preferably has a low resistance, if the polysilicon film 106 constituting the upper electrode of the capacitor element is made to be a doped polysilicon film having a high impurity concentration, the polysilicon constituting the memory gate electrode MG101 will be described. The film 106 is also a high impurity concentration polysilicon film, which is disadvantageous in terms of data retention characteristics.

  On the other hand, in the present embodiment, the upper electrode UE of the capacitive element CP is formed of a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a as shown in FIG. . Among these, the silicon film 6a is made of a non-doped silicon film, and the silicon film 6b is made of a silicon film into which impurities are introduced (doped). The lower layer portion (lower layer region) of the upper electrode UE is composed of a non-doped silicon film 6a. However, the upper layer portion (upper layer region) of the upper electrode UE is doped (doped) with low resistivity. By configuring with the film 6b, the resistance of the upper electrode UE can be reduced. Thereby, the performance of the semiconductor device having the capacitive element CP together with the nonvolatile memory can be improved.

  Further, the resistance of the upper electrode UE can be reduced by forming the metal silicide layer 11 on the upper electrode UE using the salicide technique. In this case, as shown in FIG. Since the upper electrode UE has a step reflecting the electrode LE, a sidewall insulating film SW (this sidewall insulating film SW is referred to as a sidewall insulating film SWb) is formed on the sidewall (side surface) of the step of the upper electrode UE. . For this reason, even if the metal silicide layer 11 is formed on the upper electrode UE by the salicide technique, the metal silicide layer 11 formed on the upper electrode UE is divided by the sidewall insulating film SWb, and the level difference of the upper electrode UE is reduced. The metal silicide layer 11 is not formed on the sidewall and below the sidewall insulating film SWb. However, in this embodiment, since the silicon film 6b is a silicon film into which impurities are introduced (doped), the silicon film 6b can have a low resistivity. Therefore, in the present embodiment, even if the metal silicide layer 11 is not formed on the side wall of the step of the upper electrode UE and the lower portion of the side wall insulating film SWb, the silicon film 6b has a low resistivity. By reducing the resistivity of the silicon film 6b itself, it is possible to prevent a high resistance region from being generated in the upper electrode UE. For this reason, the performance of the semiconductor device having the capacitive element CP together with the nonvolatile memory can be improved.

  FIG. 47 is a cross-sectional view of a principal part of the semiconductor device of the second comparative example, and corresponds to FIG. 1 of the present embodiment.

  The semiconductor device of the second comparative example shown in FIG. 47 is different from the semiconductor device of the first comparative example of FIG. 45 in the configuration of the memory gate electrode MG201. Other than that, the semiconductor device of the second comparative example shown in FIG. 47 has substantially the same structure as the semiconductor device of the first comparative example of FIG. 45, and here, except for the memory gate electrode MG201. Description of is omitted.

  The semiconductor device of the second comparative example shown in FIG. 47 includes a memory gate electrode MG201, a non-doped polysilicon film 106a, and a doped polysilicon film 106b in which impurities are introduced (doped) and have a low resistivity. It is formed with. The memory gate electrode MG201 is formed as follows.

  After forming the control gate electrode CG101 over the p-type well PW101 via the insulating film 103, an insulating film 105 for the gate insulating film of the memory transistor is formed on the main surface of the semiconductor substrate 101 and the surface of the control gate electrode CG101. Form. Then, after forming a non-doped polysilicon film 106a on the insulating film 105 so as to cover the control gate electrode CG101, the polysilicon film 106a is etched back by an anisotropic etching technique, thereby forming the control gate electrode CG101. The polysilicon film 106a is left on the side wall through the insulating film 105 in the form of a sidewall spacer, and the polysilicon film 106a in other regions is removed. Then, a doped polysilicon film 106b into which impurities are introduced (doped) is formed on the insulating film 105 so as to cover the polysilicon film 106a, and then the doped polysilicon film 106b is formed by an anisotropic etching technique. Etch back. By this etch back, the doped polysilicon film 106b is left on the side wall of the control gate electrode CG101 via the insulating film 105 and the polysilicon film 106a as a sidewall spacer, and the doped polysilicon film 106b in other regions is removed. To do. As a result, the memory gate electrode MG201 composed of the non-doped polysilicon film 106a and the doped polysilicon film 106b is formed on the side wall of the control gate electrode CG101 via the insulating film 105.

As described above, in the semiconductor device of the second comparative example shown in FIG. 47, the non-doped polysilicon film 106a is deposited, the polysilicon film 106a is etched back, and then the doped polysilicon film 106b is deposited. The memory gate electrode MG201 is formed by etching back the doped polysilicon film 106b. For this reason, the lower surface of the memory gate electrode MG201 (the lower surface in contact with the insulating film 105) is composed of the non-doped polysilicon film 106a on the side close to the control gate electrode CG, and the source region (the n ⁻ type semiconductor region 107a and the n ⁺ type semiconductor). The side close to the region 108a) is in a state constituted by the doped polysilicon film 106b.

  Such a semiconductor device of the second comparative example has the following problems.

  When the polysilicon film 106a is etched back, the portion of the insulating film 105 used as the memory gate insulating film (that is, the portion of the memory gate electrode MG201 that is to be located below the portion constituted by the doped polysilicon film 106b) Since the insulating film 105) is exposed, it may be damaged by over-etching. In the case where the doped polysilicon film 106b is deposited while the etching damage remains on the insulating film 105 and this silicon film 106b is etched back to form the memory gate electrode MG201, the insulating film 105 on which the etching damage remains. Is located below the memory gate electrode MG201 and is used as a memory gate insulating film, which may reduce the reliability of the nonvolatile memory.

  Therefore, in order to recover the damage of the insulating film 105 that has been subjected to the etching damage after depositing the non-doped polysilicon film 106a and etching back the polysilicon film 106a and before depositing the doped polysilicon film 106b. It is conceivable to perform reoxidation treatment. FIG. 48 is a fragmentary cross-sectional view when this reoxidation process is performed when manufacturing the semiconductor device of the second comparative example, and shows the same region as FIG. 47 described above.

  By performing this re-oxidation treatment, the exposed surface of the insulating film 105 is re-oxidized, whereby etching damage in the memory gate insulating film (the insulating film 105 under the memory gate electrode MG301) can be improved. However, this re-oxidation process oxidizes the surface of the polysilicon film 106a to form a thin oxide film (silicon oxide film) 106c. If the doped polysilicon film 106b is formed after the oxide film 106c is removed, a part of the insulating film 105 is also etched when the oxide film 106c is removed. In order to prevent this, The doped polysilicon film 106b is formed without removing the oxide film 106c. Therefore, the oxide film 106c is interposed between the polysilicon film 106a and the doped polysilicon film 106b, and the memory gate electrode MG301 is formed in this state, which is shown in FIG.

  In this case (in the case of FIG. 48), since the oxide film 106c is interposed between the polysilicon film 106a and the doped polysilicon film 106b in the memory gate electrode MG301, the polysilicon film 106a and the doped polysilicon film Since it is not in direct contact with 106b, direct conduction cannot be obtained. Therefore, it is necessary to electrically connect the polysilicon film 106a and the doped polysilicon film 106b through the metal silicide layer 111 formed on the memory gate electrode MG301 by the salicide technique. However, in this case, because the portion constituted by the polysilicon film 106a and the portion constituted by the doped polysilicon film 106b in the memory gate electrode MG301 are electrically connected via the metal silicide layer 111, The reliability of electrical connection is lowered, and the resistance of the memory gate electrode MG301 is likely to be increased. Further, in order to form the memory gate electrode MG301, a deposition process of the non-doped polysilicon film 106a, an etch-back process of the polysilicon film 106a, and a re-oxidation process of the insulating film 105 (at this time, the oxide film 106c is formed). Since the deposition process of the doped polysilicon film 106b and the etch-back process of the doped polysilicon film 106b are necessary, the number of manufacturing processes of the semiconductor device increases and the throughput of the semiconductor device decreases. Further, after the non-doped polysilicon film 106a is deposited and this polysilicon film 106a is etched back, before the doped polysilicon film 106b is deposited, damage to the insulating film 105 that has been damaged by etching is recovered. Even if the re-oxidation treatment is performed, if the damage recovery is not sufficient, there is a concern that the reliability of the nonvolatile memory may be lowered.

  In contrast, in the present embodiment, after forming (depositing) the silicon film 6a in step S8, the silicon film 6b is formed on the silicon film 6a in step S9 without etching back the silicon film 6a (see FIG. Thereafter, the laminated film 6 of the silicon films 6a and 6b is etched back by the anisotropic etching technique in the above step S10. That is, after the silicon film 6a and the silicon film 6b are continuously formed, the laminated film 6 of the silicon films 6a and 6b is anisotropically etched in the above step S10, so that the memory gate electrode MG and the upper electrode UE are formed. Is forming. Since the laminated film 6 of the silicon films 6a and 6b is formed in the steps S8 and S9, and then the laminated film 6 is etched back in the step S10, the portion of the insulating film 5 used as the memory gate insulating film. That is, the insulating film 5 scheduled to be located below the memory gate electrode MG is not exposed and is not damaged by etching. For this reason, since the insulating film 5 which is not damaged by etching is located below the memory gate electrode MG and functions as a memory gate insulating film, the reliability of the nonvolatile memory can be improved.

  In the present embodiment, the silicon film 6a deposition process in step S8, the silicon film 6b deposition process in step S9, and the stacked film 6 (stacked film 6 of silicon films 6a and 6b) in step S10 are etched. Since the memory gate electrode MG can be formed by the back process, the number of manufacturing steps of the semiconductor device can be reduced, and the throughput of the semiconductor device can be improved.

  In the present embodiment, since the portion formed of the silicon film 6a and the portion formed of the silicon film 6b in the memory gate electrode MG are in direct contact with each other, the impurity concentration of the silicon film 6b is increased. Thus, the resistance reduction effect of the memory gate electrode MG can be obtained more accurately.

  In the present embodiment, the lower surface of the memory gate electrode MG (the lower surface in contact with the insulating film 5) is composed of the silicon film 6a. The silicon film 6b having a higher impurity concentration than the silicon film 6a is the insulating film 5 The silicon film 6a is interposed between the memory gate insulating film 5 and the memory gate insulating film (the insulating film 5 located under the memory gate electrode MG). That is, in this embodiment, the insulating film 5 is in contact with the silicon film 6a having a low impurity concentration, but is not in contact with the silicon film 6b having a high impurity concentration. Therefore, in the present embodiment in which the silicon film 6b having a high impurity concentration is not in contact with the memory gate insulating film (insulating film 5), the doped polysilicon film 106b having a high impurity concentration is used as shown in FIG. Compared with the second comparative example in contact with the memory gate insulating film (insulating film 105), the charges (electrons or holes) stored in the charge storage layer (here, the silicon nitride film 5b) move to the memory gate electrode MG. Thus, the phenomenon of data inversion can be more reliably suppressed. For this reason, in this Embodiment, the data retention characteristic of a non-volatile memory can be improved more reliably.

  In addition, when SSI is used at the time of writing, a peak of the distribution of injected electrons is formed in the vicinity of the control gate electrode CG of the charge storage layer (here, the silicon nitride film 5b) formed on the lower surface of the memory gate electrode MG. Therefore, as in the semiconductor device of the second comparative example, it is preferable that the silicon film 6a having a low impurity concentration be formed at the lower end portion of the memory gate electrode MG on the control gate electrode CG side. Since the bottom of the distribution also extends to the lower surface of the insulating film 5, that is, the entire lower surface of the memory gate electrode MG, the entire lower surface of the memory gate electrode MG is formed of the silicon film 6a having a low impurity concentration. The structure of this form can be said to be more preferable because the data retention characteristics of the nonvolatile memory can be improved more reliably.

  In the present embodiment, since the silicon film 6a having a low impurity concentration is formed between the control gate electrode CG and the silicon film 6b having a high impurity concentration in the memory gate electrode MG, the control gate electrode CG And the memory gate electrode MG are secured, and the reliability of the nonvolatile memory can be secured. That is, in addition to the entire lower surface of the memory gate electrode MG being formed of the silicon film 6a having a low impurity concentration, the silicon film 6a having a low impurity concentration between the control gate electrode CG and the silicon film 6b having a high impurity concentration. As a result, the performance of the semiconductor device in this embodiment and the reliability can be improved. In other words, the insulating film 5 including the charge storage layer is formed between the control gate electrode CG and the memory gate electrode MG and between the semiconductor substrate 1 and the memory gate electrode MG, and the insulating film 5 and the silicon film having a high impurity concentration are formed. Since the silicon film 6a having a low impurity concentration is formed between the semiconductor device 6b and the semiconductor device 6b, the performance of the semiconductor device in the present embodiment can be improved and the reliability can be improved.

  Further, in order to form the silicon films 6a and 6b in the above steps S8 and S9, the semiconductor substrate 1 is disposed in the chamber (deposition chamber) of the film forming apparatus, and the step is performed without exposing the semiconductor substrate 1 to the atmosphere. The step of forming (depositing) the silicon film 6a in S8 and the step of forming (depositing) the silicon film 6b in step S9 can be continuously performed in-situ. For example, after the silicon film 6a is formed (deposited) on the main surface of the semiconductor substrate 1 disposed in the chamber of the film forming apparatus, the semiconductor substrate 1 is not removed from the chamber, and the main surface of the semiconductor substrate 1 in the chamber is removed. A silicon film 6b is formed (deposited) on the silicon film 6a. At this time, it is possible to shift from the formation (deposition) step of the silicon film 6a to the formation (deposition) step of the silicon film 6b by switching the film formation gas (film formation gas). In this case, in the formation process of the silicon film 6a in step S8, a film forming gas not containing a doping gas (impurity addition gas) is used, and in the formation process of the silicon film 6b in step S9, a doping gas (n-type impurity addition) is performed. Film-forming gas containing the gas for use) may be used.

  When the formation (deposition) process of the silicon film 6a in step S8 and the formation (deposition) process of the silicon film 6b in step S9 are continuously performed in-situ, the film formation process of the silicon films 6a and 6b is performed. It can be simplified. Moreover, the film formation time of the silicon films 6a and 6b can be shortened, and the throughput can be improved.

  On the other hand, the step of forming (depositing) the silicon film 6a in step S8 and the step of forming (depositing) the silicon film 6b in step S9 can be performed as separate steps. For example, after the silicon film 6a is formed (deposited) on the main surface of the semiconductor substrate 1 disposed in the chamber of the film forming apparatus, the film formation on the semiconductor substrate 1 is temporarily stopped and a predetermined time has elapsed. A silicon film 6 b is formed (deposited) on the silicon film 6 a on the main surface of the semiconductor substrate 1. At this time, when the semiconductor substrate 1 is exposed to the atmosphere after the silicon film 6a is formed and before the silicon film 6b is formed, such as by taking the semiconductor substrate 1 out of the film forming apparatus, Since an unnecessary film such as a natural oxide film can be formed on the surface of the silicon film 6a, a cleaning process using hydrofluoric acid or the like is performed before the formation of the silicon film 6b, so that an unnecessary film on the surface of the silicon film 6a (natural It is preferable to remove the oxide film or the like. Thereafter, the semiconductor substrate 1 is disposed again in the chamber of the film forming apparatus, and the silicon film 6 b may be formed (deposited) on the silicon film 6 a on the main surface of the semiconductor substrate 1.

  When the formation (deposition) process of the silicon film 6a in step S8 and the formation (deposition) process of the silicon film 6b in step S9 are performed in separate processes, an interface is formed between the silicon film 6a and the silicon film 6b. If this interface exists, diffusion of impurities from the silicon film 6b to the silicon film 6a is easily suppressed. Therefore, an increase in the impurity concentration of the silicon film 6a due to the diffusion of impurities from the silicon film 6b to the silicon film 6a can be suppressed or prevented more accurately.

FIG. 49 is a table (explanatory view) showing the conductivity types of the silicon films 6a and 6b. In the first embodiment and the second and third embodiments described later, the silicon films at the time of forming the silicon films 6a and 6b are shown. The conductivity types 6a and 6b and the conductivity types of the silicon films 6a and 6b after the manufacture of the semiconductor device are summarized as a table. In the table of FIG. 49, “n ⁺ type” and “n ⁻ type” are both n type, but “n ⁺ type” has a higher impurity concentration than “n ⁻ type”. Further, “p ⁻ type” is p type, but “p ⁻ type” impurity concentration (p type impurity concentration) is lower than “n ⁺ type” impurity concentration (n type impurity concentration). If the memory transistor is a p-channel MISFET, the n-type and p-type may be inverted in FIG.

In the present embodiment, the silicon film 6a (silicon film 6a at the time of film formation) formed in step S8 is a non-doped silicon film, but by various subsequent heating processes (especially the activation annealing process in step S16). The impurities in the silicon film 6b may be diffused into the silicon film 6a so that the impurities are introduced into the silicon film 6a. When impurities diffuse from the silicon film 6b to the silicon film 6a, the silicon film 6a becomes an n ⁻ -type silicon film in the semiconductor device after manufacture. However, even if the impurities in the silicon film 6b are diffused into the silicon film 6a, if the impurity concentration of the silicon film 6b is higher than the impurity concentration of the silicon film 6a in the manufactured semiconductor device, that is, If the resistivity of the silicon film 6b is lower than the resistivity of the silicon film 6a, the effect of improving the above-mentioned data retention characteristics and the effect of improving the performance by reducing the resistance of the memory gate electrode MG (for example, the effect of improving the operating speed). ) And can be obtained. However, in the manufactured semiconductor device, when the impurity is introduced into the silicon films 6a and 6b and the impurity concentration of the silicon film 6b is higher than the impurity concentration of the silicon film 6a, the conductivity type of the silicon film 6b is The conductivity type of the silicon film 6a must be the same (for example, when the silicon film 6b is n-type, the silicon film 6a is also n-type), so that the silicon film 6a is interposed between the silicon film 6a and the silicon film 6b. Formation of a PN junction can be prevented.

  In order to enhance the effect of improving the data retention characteristics, it is preferable to suppress the diffusion of impurities in the silicon film 6b into the silicon film 6a as much as possible. In the manufactured semiconductor device, the silicon film 6a is non-doped silicon. In the case of a film, the effect of improving data retention characteristics is greatest.

  Therefore, in the present embodiment, by making the silicon film 6a non-doped at the time of film formation, the impurity concentration of the silicon film 6a is lower than the impurity concentration of the silicon film 6b in the manufactured semiconductor device. In the manufactured semiconductor device, the silicon film 6a is a non-doped silicon film.

(Embodiment 2)
As shown in FIG. 49, in the first embodiment, the silicon film 6a formed in step S8 is a non-doped silicon film. However, in the second embodiment, the silicon film 6a formed in step S8 is A silicon film into which impurities are introduced (doped) is used. For this reason, in the present embodiment, impurities are intentionally introduced (added or doped) into the silicon film 6a. As for the silicon film 6b, the present embodiment is the same as the first embodiment.

  However, in the present embodiment, the conductivity type of the impurity introduced into the silicon film 6a formed (deposited) in step S8 is the same as that of the impurity introduced into the silicon film 6b formed (deposited) in step S9 (preferably And the impurity concentration of the silicon film 6a formed (deposited) in step S8 is lower than the impurity concentration of the silicon film 6b formed (deposited) in step S9. Therefore, the silicon film 6a formed in step S8 is a silicon film having the same conductivity type as that of the silicon film 6b formed in step S9 and having a lower impurity concentration than the silicon film 6b. For this reason, the resistivity of the silicon film 6b formed (deposited) in step S9 is lower than the resistivity of the silicon film 6a formed (deposited) in step S8.

  As a method for introducing impurities into the silicon film 6a, it is preferable to introduce impurities into the silicon film 6a when the silicon film 6a is formed (that is, depositing the silicon film 6a into which impurities are introduced in step S8). In this case, a doping gas (impurity addition gas) may be included in the gas for forming the silicon film 6a. Each of the silicon films 6a and 6b is preferably an n-type doped polysilicon film (where 6b is higher in impurity concentration than the silicon film 6a), but an amorphous silicon film (amorphous silicon into which impurities are introduced) is formed at the time of film formation. The film) can be converted into a polycrystalline silicon film (doped polysilicon film) by a subsequent heat treatment.

  Since the other configuration of the second embodiment is the same as that of the first embodiment, the description thereof is omitted here.

  In the present embodiment, the same effect as in the first embodiment can be obtained, but the unique effect of the present embodiment will be described later.

(Embodiment 3)
As shown in FIG. 49, in the third embodiment, the silicon film 6a formed in step S8 is a silicon film into which impurities are introduced (doped). For this reason, in the present embodiment, impurities are intentionally introduced (added or doped) into the silicon film 6a. As for the silicon film 6b, the present embodiment is the same as the first embodiment.

  However, in the present embodiment, the conductivity type of the impurity introduced into the silicon film 6a formed (deposited) in step S8 is opposite to the conductivity type of the impurity introduced into the silicon film 6b formed (deposited) in step S9 ( Preferably, the impurity introduced into the silicon film 6a is a p-type impurity, and the impurity introduced into the silicon film 6b is an n-type impurity. The impurity concentration of the silicon film 6a formed (deposited) in step S8 is set lower than the impurity concentration of the silicon film 6b formed (deposited) in step S9. Accordingly, the silicon film 6a formed in step S8 is a silicon film having a conductivity type opposite to that of the silicon film 6b formed in step S9 and having a lower impurity concentration than the silicon film 6b.

  As a method for introducing impurities into the silicon film 6a, it is preferable to introduce impurities into the silicon film 6a when the silicon film 6a is formed (that is, depositing the silicon film 6a into which impurities are introduced in step S8). In this case, a doping gas (impurity addition gas) may be included in the gas for forming the silicon film 6a. The silicon films 6a and 6b are preferably doped polysilicon films (polycrystalline silicon films into which impurities are introduced), but were amorphous silicon films (amorphous silicon films into which impurities were introduced) at the time of film formation. A thing can also be made into a polycrystalline silicon film (doped polysilicon film) by a subsequent heat treatment.

  Then, after the formation of the silicon films 6a and 6b, impurities in the silicon film 6b are diffused into the silicon film 6a by various heating processes (particularly, the activation annealing process in step S16), so that the silicon film 6a is formed. At the time of film formation, the conductivity type opposite to that of the silicon film 6b is transferred to the same conductivity type as that of the silicon film 6b. For example, when the silicon films 6a and 6b are formed, the silicon film 6a is a p-type doped polysilicon film and the silicon film 6b is an n-type doped polysilicon film (provided that the silicon film 6a is a silicon film). What has a lower impurity concentration than the film 6b) diffuses impurities in the silicon film 6b into the silicon film 6a by the activation annealing in step S16, so that the silicon film 6a becomes an n-type polysilicon film. For this reason, the impurity concentration of the silicon film 6a at the time of film formation needs to be lower than the impurity concentration diffused from the silicon film 6b to the silicon film 6a by the activation annealing in step S16. In the present embodiment, the silicon film 6a and the silicon film 6b have opposite conductivity types at the time of film formation, but in the manufactured semiconductor device, the silicon film 6a and the silicon film 6b have the same conductivity type. Accordingly, it is possible to prevent the formation of a PN junction between the silicon film 6a and the silicon film 6b. However, in the manufactured semiconductor device, the silicon film 6b needs to have a higher impurity concentration and a lower resistivity than the silicon film 6a.

  Since the other configuration of the third embodiment is the same as that of the first embodiment, the description thereof is omitted here.

  What is common to the first to third embodiments is that in the manufactured semiconductor device, the silicon film 6b has a higher impurity concentration than the silicon film 6a. In other words, in the manufactured semiconductor device, the memory gate electrode MG is separated from the insulating film 5 via the first silicon region (region formed by the silicon film 6a) adjacent to the insulating film 5 and the first silicon region. The impurity concentration of the first silicon region (region formed by the silicon film 6a) is the second silicon region (region formed by the silicon film 6b). This is lower than the impurity concentration of the region. In the manufactured semiconductor device, since the impurity concentration of the first silicon region (region formed by the silicon film 6a) is lower than the impurity concentration of the second silicon region (region formed by the silicon film 6b), the second silicon region The resistivity of the region (region formed with the silicon film 6b) is lower than the resistivity of the first silicon region (region formed with the silicon film 6a). In the manufactured semiconductor device, the silicon film 6b (second silicon region) has a higher impurity concentration and a lower resistivity than the silicon film 6a (first silicon region), and as described in the first embodiment. Since the phenomenon that charges (electrons or holes) stored in the charge storage layer (silicon nitride film 5b) move to the memory gate electrode MG and data is inverted can be suppressed or prevented, data retention characteristics of the nonvolatile memory can be improved. be able to. In the manufactured semiconductor device, the silicon film 6b (second silicon region) has a higher impurity concentration and a lower resistivity than the silicon film 6a (first silicon region), so that the first embodiment has been described. As described above, the resistance of the memory gate electrode MG can be reduced, and the operation speed of the nonvolatile memory can be improved. Thereby, the performance of the semiconductor device having a nonvolatile memory can be improved.

  In addition, when the silicon film 6a is a non-doped silicon film as in the first embodiment, a region adjacent to the insulating film 5 in the memory gate electrode MG (that is, a region constituted by the silicon film 6a). Since the impurity concentration can be reduced more accurately, the effect of preventing the phenomenon that charges (electrons or holes) stored in the charge storage layer (silicon nitride film 5b) move to the memory gate electrode MG and data is inverted can be prevented. Can be the largest. For this reason, the effect of improving the data retention characteristics is the greatest.

  Further, as in the second embodiment, when the silicon films 6a and 6b are silicon films into which impurities are introduced (doped) and the silicon film 6a has a lower impurity concentration than the silicon film 6b, the memory Although the impurity concentration of the region adjacent to the insulating film 5 in the gate electrode MG (that is, the region formed of the silicon film 6a) is lower than that of the silicon film 6b, an effect of improving data retention characteristics can be obtained. Is larger in the first embodiment. However, since the silicon film 6a is a silicon film into which impurities are introduced (doped), a region adjacent to the capacitive insulating film DE in the upper electrode UE of the capacitive element CP (that is, a region formed of the silicon film 6a in the upper electrode UE). ) Is not a non-doped region but a region into which impurities are introduced (doped) (that is, the silicon film 6a), so that the region adjacent to the capacitive insulating film DE of the upper electrode UE can be suppressed from being depleted. Therefore, the data retention characteristics of the nonvolatile memory can be improved while suppressing the capacitance of the capacitive element CP from being reduced due to this depletion and the capacitance value becoming unstable.

  Further, as in the third embodiment, when the silicon films 6a and 6b are formed, the conductivity type of the silicon film 6a is set to a conductivity type opposite to that of the silicon film 6b, and the silicon film 6a is formed more than the silicon film 6b. In the case where the conductivity type of the silicon film 6a is made the same as the conductivity type of the silicon film 6b by diffusing impurities from the silicon film 6b to the silicon film 6a by the activation annealing in the above step S16, etc. The following unique effects can be obtained.

  That is, in the first embodiment, the silicon film 6a is a non-doped silicon film at the time of film formation. However, impurities are transferred from the silicon film 6b to the silicon film 6a in various subsequent heating processes (especially, activation annealing in step S16). May diffuse and impurities may be introduced into the silicon film 6a. When impurities are diffused from the silicon film 6b into the non-doped silicon film 6a, the impurity concentration in the silicon film 6a increases, so that the effect of improving the data retention characteristics of the nonvolatile memory may be reduced by the increase in the impurities. There is sex. On the other hand, in this embodiment, by introducing (doping) an impurity having a conductivity type opposite to the impurity introduced into the silicon film 6b into the silicon film 6a in advance when the silicon film 6a is formed, Compared to the case where the silicon film 6a is formed as a non-doped silicon film, the impurity of the same type as the silicon film 6b of the silicon film 6a after the impurity is diffused from the silicon film 6b to the silicon film 6a by the activation annealing in step S16 or the like. It is possible to reduce the concentration. As a result, an increase in the impurity concentration of the same type as the effective silicon film 6b in the silicon film 6a due to the diffusion of impurities from the silicon film 6b to the silicon film 6a can be suppressed, and the data retention characteristics of the nonvolatile memory can be reduced. The improvement effect can be enhanced. For this reason, in the third embodiment, after the formation of the silicon films 6a and 6b, there is a large amount of impurity diffusion from the silicon film 6b to the silicon film 6a due to various heating processes (especially the activation annealing in step S16). If applied to, the effect is greater.

In the manufacturing process of the semiconductor device of the first to third embodiments, after the activation annealing in step S16, the temperature is higher than the activation annealing temperature (heat treatment temperature, annealing temperature) in step S16. No heat treatment (heat treatment) is performed. For this reason, each impurity concentration of the silicon films 6a and 6b in the manufactured semiconductor device is defined (determined) at the stage of performing the activation annealing in the above step S16, and after performing the activation annealing in the above step S16 ( Immediately) the respective impurity concentrations of the silicon films 6a and 6b are maintained in the manufactured semiconductor device. For this reason, in the first to third embodiments, the above-described relationship between the impurity concentrations of the silicon films 6a and 6b in the manufactured semiconductor device is the same as the silicon films 6a and 6b after the activation annealing in step S16. It can also be applied to the relationship of the impurity concentration.
(Embodiment 4)
In the present embodiment, a case will be described in which the control gate electrode CG of the nonvolatile memory of the first to third embodiments is formed of a laminated film of an insulating film and a silicon film 4.

  50 to 52 are principal part sectional views of the semiconductor device of the present embodiment. FIG. 50 is a principal part sectional view of the nonvolatile memory cell region 1A, and FIG. The principal part sectional view of the memory gate shunt region 1B is shown.

  In the memory cell of the nonvolatile memory according to the present embodiment, as described above, the control gate electrode CG is configured by a laminated film of the silicon film 4 and the insulating film. Specifically, the control gate electrode CG is composed of a laminated film of the silicon film 4, the insulating film 15, and the insulating film 16. The insulating film 15 is formed thinner than the insulating film 16, and is formed of a silicon oxide film as the insulating film in the present embodiment. On the other hand, the insulating film 16 is formed of a silicon nitride film in the present embodiment. The insulating film 15 is formed on the silicon film 4, and the insulating film 16 is formed on the insulating film 15.

  In the present embodiment, since the insulating film 15 and the insulating film 16 are formed on the control gate electrode CG of the memory cell, the metal silicide layer 11 is not formed on the control gate electrode CG of the memory cell.

  Other configurations of the memory cell of the present embodiment are the same as those of the first to third embodiments, and thus description thereof is omitted.

  As shown in FIG. 51, in the memory gate shunt region 1B in the present embodiment, a configuration in which the control gate electrode CG is formed of a laminated film of the silicon film 4, the insulating film 15, and the insulating film 16 is conceivable. .

  On the other hand, as shown in FIG. 52, in memory gate shunt region 1B, by removing insulating film 15 and insulating film 16 formed in the present embodiment, the same configuration as in the first to third embodiments ( A case in which the insulating films 15 and 16 are not formed on the silicon film 4 constituting the control gate electrode CG is also conceivable. However, when the memory gate shunt region 1B is formed as shown in FIG. 52, it is formed in the memory cell region 1A as much as the insulating film 15 and the insulating film 16 on the silicon film 4 (control gate electrode CG) are removed. The height of the control gate electrode CG (not including the insulating films 15 and 16) formed in the memory gate shunt region 1B is lower than that of the control gate electrode CG (including the insulating films 15 and 16). For this reason, even if the contact portion MGa is formed in a state of running over the control gate electrode CG, in the case of FIG. 52 (when the insulating films 15 and 16 are removed in the memory gate shunt region 1B), the insulating film 15 and Since the height of the element formed in the memory gate shunt region 1B is reduced by the amount 16 is removed, in the case of FIG. 51 (not only the memory cell region 1A but also the memory gate shunt region 1B is insulated above the control gate electrode CG. Compared to the case where the films 15 and 16 are present, the insulating film 12 can be formed thinner. For this reason, when forming the contact hole CNT, the desired contact hole CNT can be formed without causing a shape abnormality, and the reliability of the semiconductor device can be improved.

  51 and 52, in the drawings, the contact portion MGa extends in a direction perpendicular to the direction in which the control gate electrode CG extends. However, depending on the layout, the control gate electrode CG extends. You may form so that the contact part MGa may extend in the same direction as the direction to do. Since other configurations in the memory gate shunt region are the same as those in the first to third embodiments, description thereof is omitted.

  The configuration of the capacitive element CP formed in the capacitor formation region 1C is the same as that in the first to third embodiments. This is because the insulating film 15 and the insulating film 16 formed on the upper portion of the lower electrode LE are removed in the capacitor forming region 1C as in the case of FIG. By doing so, the film thickness of the insulating film formed between the lower electrode LE and the upper electrode UE is reduced, and the capacitive insulating film DE in the same layer as the insulating film 5 is formed as in the first to third embodiments. Therefore, it is possible to avoid a decrease in the capacitance of the capacitive element CP due to the formation of the insulating film 15 and the insulating film 16, and the performance of the semiconductor device can be improved.

  In the manufacturing process of the semiconductor device of the present embodiment, a process of forming the insulating film 15 and the insulating film 16 is added between step S5 and step S6 in the process flow of FIG. 7, and in step S6, the silicon film 4 and At the same time, the insulating film 15 and the insulating film 16 are also patterned, and appropriate removal (removal of the insulating film 16 and the insulating film 15) is performed in a region where the insulating film 15 and the insulating film 16 are to be removed between Step S6 and Step S7. Do. Since other manufacturing steps of the semiconductor device of the present embodiment are the same as the process flow of FIG. 7, detailed description thereof is omitted.

  Also in the present embodiment, the same effects as in the first to third embodiments can be obtained.

  In addition, in this embodiment, since the control gate electrode CG is formed of a laminated film of the silicon film 4, the insulating film 15, and the insulating film 16, the silicon film 4 is thinner than those in the first to third embodiments. Even when formed, since the height of the memory gate electrode MG formed in the shape of a sidewall spacer on the side wall of the control gate electrode CG can be secured, the memory gate electrode MG is formed of 2 of the silicon film 6a and the silicon film 6b. Another advantage is that it is easy to form the polysilicon layer.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device and a manufacturing method thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Memory cell area | region 1B Memory gate shunt area | region 1C Capacitor formation area | region 2 Element isolation area | region 3 Insulating film 4 Silicon film 5 Insulating film 5a, 5c Silicon oxide film 5b Silicon nitride film 6 Stacked film 6a, 6b Silicon film 7a, 7b n ⁻ type semiconductor regions 8a and 8b n ⁺ type semiconductor region 11 Metal silicide layer 12 Insulating film 13a Barrier conductor film 13b Main conductor film 14 Insulating film CP Capacitance element CG Control gate electrode CNT Contact hole DE Capacitance insulating film LE Lower electrode M1 Wiring MC memory cell MD, MS semiconductor region MG memory gate electrode PG plug PW p-type well RG101 high resistance region SP1 silicon spacer SW side wall insulating film UE upper electrode 15 insulating film 16 insulating film

Claims (21)

A semiconductor substrate;
A first gate electrode formed on the semiconductor substrate;
A second gate electrode formed on the semiconductor substrate and adjacent to the first gate electrode;
A first insulating film formed between the first gate electrode and the semiconductor substrate;
A second insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, the second insulating film having a charge storage portion therein; An insulating film;
Have
The second gate electrode includes a first silicon region adjacent to the second insulating film, and a second silicon region spaced from the second insulating film via the first silicon region,
The semiconductor device according to claim 1, wherein an impurity concentration of the first silicon region is lower than an impurity concentration of the second silicon region. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a resistivity of the second silicon region is lower than a resistivity of the first silicon region. The semiconductor device according to claim 2,
The second insulating film and the first silicon region of the second gate electrode are interposed between the second silicon region of the second gate electrode and the semiconductor substrate,
The second insulating film and the first silicon region of the second gate electrode are interposed between the second silicon region of the second gate electrode and the first gate electrode. Semiconductor device. The semiconductor device according to claim 3.
The semiconductor device, wherein the second silicon region is not in contact with the second insulating film. The semiconductor device according to claim 4.
The first silicon region is formed of a first silicon film;
The semiconductor device, wherein the second silicon region is formed of a second silicon film having a higher impurity concentration than the first silicon film. The semiconductor device according to claim 5.
The semiconductor device, wherein the first silicon film and the second silicon film have the same conductivity type. The semiconductor device according to claim 5.
The first silicon film is a non-doped silicon film,
The semiconductor device, wherein the second silicon film is made of a silicon film into which impurities are introduced. The semiconductor device according to claim 1,
A semiconductor device, wherein a metal silicide layer is formed on the second gate electrode. The semiconductor device according to claim 1,
The semiconductor device has a nonvolatile memory,
The semiconductor device, wherein the first and second gate electrodes are gate electrodes constituting the nonvolatile memory. The semiconductor device according to claim 5.
A capacitor element further including a first electrode formed on the semiconductor substrate and a second electrode formed on the first electrode via a capacitor insulating film;
The capacitive insulating film is formed of an insulating film in the same layer as the second insulating film,
The first electrode is formed of a conductor film in the same layer as the first gate electrode,
The second electrode is formed of a laminated film of a silicon film in the same layer as the first silicon film and a silicon film in the same layer formed on the silicon film. Semiconductor device. The semiconductor device according to claim 1,
The thickness in the gate length direction of the second gate electrode of the first silicon region formed between the first gate electrode and the second silicon region is t1,
When the thickness in the gate length direction of the second gate electrode of the region in contact with the first silicon region on the lower surface of the second silicon region is t2,
A semiconductor device characterized in that a relationship of t1 <t2 is established between the t1 and the t2. A semiconductor substrate;
A first gate electrode and a second gate electrode formed on the semiconductor substrate and adjacent to each other;
A first gate insulating film formed between the first gate electrode and the semiconductor substrate;
A second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein;
A method of manufacturing a semiconductor device having
(A) preparing the semiconductor substrate;
(B) forming a first insulating film for the first gate insulating film on a main surface of the semiconductor substrate;
(C) forming a first conductor film for the first gate electrode on the first insulating film;
(D) patterning the first conductor film to form the first gate electrode;
(E) forming a second insulating film for the second gate insulating film and having a charge storage portion therein on the main surface of the semiconductor substrate and the surface of the first gate electrode;
(F) forming a first silicon film on the second insulating film;
(G) forming a second silicon film on the first silicon film;
(H) Etching back the laminated film of the second silicon film and the first silicon film to leave the laminated film on the sidewall of the first gate electrode with the second insulating film interposed therebetween. Forming a gate electrode;
Have
A method of manufacturing a semiconductor device, wherein the impurity concentration of the second silicon film formed in the step (g) is higher than the impurity concentration of the first silicon film formed in the step (f). In the manufacturing method of the semiconductor device according to claim 12,
The second insulating film is interposed between the second gate electrode and the semiconductor substrate formed in the step (h) and between the second gate electrode and the first gate electrode,
The second gate electrode formed in the step (h) includes the first silicon film in contact with the second insulating film, and the second silicon separated from the second insulating film through the first silicon film. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 13,
The first silicon film formed in the step (f) is a non-doped silicon film,
The method of manufacturing a semiconductor device, wherein the second silicon film formed in the step (g) is made of a silicon film into which impurities are introduced. 14. The method of manufacturing a semiconductor device according to claim 13,
The first silicon film formed in the step (f) is composed of the first silicon film into which impurities are introduced,
The method of manufacturing a semiconductor device, wherein the second silicon film formed in the step (g) includes the second silicon film into which an impurity is introduced. In the manufacturing method of the semiconductor device according to claim 15,
The conductivity type of the impurity introduced into the first silicon film formed in the step (f) is the same as the conductivity type of the impurity introduced into the second silicon film formed in the step (g). A method for manufacturing a semiconductor device, wherein: In the manufacturing method of the semiconductor device according to claim 15,
The conductivity type of the impurity introduced into the first silicon film formed in the step (f) is opposite to the conductivity type of the impurity introduced into the second silicon film formed in the step (g). A method for manufacturing a semiconductor device, wherein: The method of manufacturing a semiconductor device according to claim 17.
After the step (h),
(I) forming a semiconductor region for source or drain on the semiconductor substrate by ion implantation;
(J) After the step (i), performing a heat treatment for activating impurities introduced into the source or drain semiconductor region;
Further comprising
After the step (j), the semiconductor device manufacturing method is characterized in that the conductivity types of the second silicon film and the first silicon film are the same. In the manufacturing method of the semiconductor device according to claim 12,
In (d), the first conductive film is patterned to form the first gate electrode and the lower electrode of the capacitive element,
In the step (e), the second insulating film is formed on the main surface of the semiconductor substrate and the surfaces of the first gate electrode and the lower electrode,
After the step (g) and before the step (h),
(G1) forming a first resist pattern on the second silicon film;
Further comprising
In the step (h), the second silicon film and the first silicon film are etched back using the first resist pattern as an etching mask, thereby leaving the stacked film under the first resist pattern. A method of manufacturing a semiconductor device, comprising forming an upper electrode of an element. In the manufacturing method of the semiconductor device according to claim 12,
The film thickness of the first silicon film formed in the step (f) is t1,
When the thickness of the second silicon film formed in the step (g) is t2,
A method of manufacturing a semiconductor device, wherein a relationship of t1 <t2 is established between the t1 and the t2. In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the step (f) and the step (g) are performed continuously.

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