JP2012069652A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a performance of a semiconductor device having a nonvolatile memory.SOLUTION: Insulator films 5 are formed between a memory gate electrode MG of a split gate type nonvolatile memory and a p-type well PW1, and between a control gate electrode CG and the memory gate electrode MG. Among the insulator films 5, a portion between a lower face of the memory gate electrode MG and an upper face of a semiconductor substrate 1 has silicon oxide films 6a, 6c and a silicon nitride film 6b sandwiched between the silicon oxide films 6a, 6c. Among the insulator films 5, a portion between a side face of the control gate electrode CG and a side face of the memory gate electrode MG has the silicone oxide films 6a, 6c and a cavity CAV sandwiched between the silicon oxide films 6a, 6c, and does not have the silicon nitride film 6b.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technology effective when applied to a semiconductor device having a nonvolatile memory and a method for manufacturing the same.

  EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a nonvolatile semiconductor memory device that can be electrically written and erased. These storage devices (memory) typified by currently used flash memory have a conductive floating gate electrode and a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. The charge accumulation state in the floating gate and the trapping insulating film is stored information and is read as the threshold value of the transistor. This trapping insulating film refers to an insulating film capable of accumulating charges, and examples thereof include a silicon nitride film. The threshold value of the MISFET is shifted by such charge injection / release to / from the charge storage region to operate as a memory element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, by using a silicon nitride film as a charge storage region, it is superior in data retention reliability because it accumulates charges discretely compared to a conductive floating gate film, and also in data retention reliability. Therefore, the oxide films above and below the silicon nitride film can be made thinner, and the voltage of the write / erase operation can be lowered.

  JP 2005-259843 A (Patent Document 1), JP 2009-212399 A (Patent Document 2), JP 2006-41227 A (Patent Document 3) and JP 2007-324188 A (Patent Document 4). ) Describes a technique related to a MONOS type nonvolatile memory.

JP 2005-259843 A JP 2009-212399 A JP 2006-41227 A JP 2007-324188 A

  According to the study of the present inventor, the following has been found.

  In the split gate type nonvolatile memory, a stacked gate insulating film is formed, and the control gate electrode and the memory gate electrode of the nonvolatile memory are adjacent to each other through the stacked gate insulating film. In recent years, in the nonvolatile memory, it is desired to improve the breakdown voltage between adjacent gate electrodes, ensure the reliability of the stacked gate insulating film, and improve the electrical performance.

  An object of the present invention is to provide a technique capable of improving the electrical performance of a semiconductor device. Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device. Another object of the present invention is to provide a technique capable of improving the electrical performance of a semiconductor device and to provide a technique capable of improving the reliability of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment is a semiconductor device including a memory cell of a nonvolatile memory, and includes a first gate electrode formed on a semiconductor substrate via a gate insulating film, and an upper portion of the semiconductor substrate. A second gate electrode adjacent to the first gate electrode; an insulation formed between the first gate electrode and the semiconductor substrate; and between the first gate electrode and the second gate electrode. And a membrane. Of the insulating film, a first portion between the lower surface of the second gate electrode and the upper surface of the semiconductor substrate includes a first silicon oxide film, a second silicon oxide film, and the first and second silicon oxide films. The silicon nitride film functions as a charge storage portion of a memory cell. Of the insulating film, a second portion between the side surface of the first gate electrode and the side surface of the second gate electrode includes the first silicon oxide film, the second silicon oxide film, the first and first A cavity sandwiched between silicon dioxide films, and does not have the silicon nitride film.

  In addition, a method for manufacturing a semiconductor device according to a representative embodiment is a method for manufacturing a semiconductor device including a memory cell of a nonvolatile memory, wherein (a) a step of preparing a semiconductor substrate, (b) a step of preparing the semiconductor substrate Forming a first gate electrode constituting the memory cell on the main surface through a first gate insulating film; (C) forming an insulating film made of a laminated film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film on the main surface of the semiconductor substrate and the side surface of the first gate electrode; d) forming a second gate electrode adjacent to the first gate electrode via the insulating film on the insulating film and forming the memory cell; and (e) being covered with the second gate electrode. A step of removing the insulating film in a portion not present. (F) after the step (e), forming a sidewall insulating film on the sidewall of the second gate electrode opposite to the side adjacent to the first gate electrode; g) After the step (f), a step of forming a cavity by removing the silicon nitride film in a portion of the insulating film between the side surface of the first gate electrode and the side surface of the second gate electrode. Have.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the electrical performance of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved. In addition, electrical performance can be improved and the reliability of the semiconductor device can be improved.

It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is the elements on larger scale which expanded a part of FIG. It is an equivalent circuit diagram of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. It is a process flow figure showing a part of manufacturing process of a semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; It is a partial expanded sectional view of FIG. FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is a partial expanded sectional view of FIG. FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; It is the elements on larger scale of FIG. FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is a partial expanded sectional view of FIG. FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; It is a partial expanded sectional view of FIG. FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is principal part sectional drawing of the semiconductor device of a comparative example. It is the elements on larger scale which expanded a part of FIG. It is explanatory drawing of the semiconductor device which is one embodiment of this invention. It is explanatory drawing for demonstrating the formation area of a cavity and a silicon nitride film. It is explanatory drawing for demonstrating the formation area of a cavity and a silicon nitride film. It is explanatory drawing for demonstrating the formation area of a cavity and a silicon nitride film. It is explanatory drawing for demonstrating the formation area of a cavity and a silicon nitride film. It is explanatory drawing for demonstrating the formation area of a cavity and a silicon nitride film. It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. It is the partial expanded sectional view which expanded a part of FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The present invention is a semiconductor device including a non-volatile memory (non-volatile memory element, flash memory, non-volatile semiconductor memory device), and the non-volatile memory mainly has a trapping insulating film (charge can be accumulated in a charge accumulation portion). Insulating film) is used. In the following embodiments, the nonvolatile memory will be described based on a memory cell using an n-channel MISFET (MISFET: Metal Insulator Semiconductor Field Effect Transistor) as a basis and using a trapping insulating film. The polarities (polarity of applied voltage and carrier polarity at the time of writing / erasing / reading) in the following embodiments are for explaining the operation in the case of a memory cell based on an n-channel MISFET. In the case of using a p-channel type MISFET as a basis, the same operation can be obtained in principle by inverting all the polarities such as applied potential and carrier conductivity type.

  A semiconductor device and a manufacturing method thereof according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device of the present embodiment. The semiconductor device of the present embodiment is a semiconductor device including a nonvolatile memory, and FIG. 1 shows a cross-sectional view of a main part of a memory cell region of the nonvolatile memory. FIG. 2 is a partial enlarged cross-sectional view (main cross-sectional view) of the memory cell MC in the semiconductor device of the present embodiment, and a part of FIG. 1 is enlarged. FIG. 3 is an equivalent circuit diagram of the memory cell MC. 2 shows the control gate electrode CG, the memory gate electrode MG, the insulating films 3 and 5, the side wall insulating film SW1, and the substrate region immediately below them in order to simplify the understanding. Only a part of the semiconductor substrate 1 constituting the p-type well PW1 is illustrated.

  As shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, has an element isolation region (elements described later) for isolating elements. The p-type well PW1 is formed in the active region isolated (defined) corresponding to the isolation region 2 (not shown here). In the p-type well PW1 in the memory cell region, a memory cell MC of a nonvolatile memory including a memory transistor and a control transistor (selection transistor) as shown in FIG. 1 is formed. In each memory cell region, a plurality of memory cells MC are formed in an array, and each memory cell region is electrically isolated from other regions by an element isolation region.

  As shown in FIG. 1 to FIG. 3, the memory cell MC of the nonvolatile memory in the semiconductor device of the present embodiment is a split gate type memory cell and has a control gate electrode (selection gate electrode) CG. Two MISFETs of a (selection transistor) and a memory transistor having a memory gate electrode (memory gate electrode) MG are connected.

  Here, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) including a gate insulating film including a charge storage portion (charge storage layer) and a memory gate electrode MG is referred to as a memory transistor (memory transistor). The MISFET including the gate electrode CG is referred to as a control transistor (selection transistor, memory cell selection transistor). Therefore, the memory gate electrode MG is a gate electrode of the memory transistor, the control gate electrode CG is a gate electrode of the control transistor, and the control gate electrode CG and the memory gate electrode MG are nonvolatile memories (memory cells thereof). It is the gate electrode which comprises.

  Hereinafter, the configuration of the memory cell MC will be specifically described.

  As shown in FIGS. 1 and 2, the memory cell MC of the nonvolatile memory includes n-type semiconductor regions MS and MD for source and drain formed in the p-type well PW1 of the semiconductor substrate 1, and the semiconductor substrate. A control gate electrode CG formed on the top of 1 (p-type well PW1), and a memory gate electrode MG formed on the top of the semiconductor substrate 1 (p-type well PW1) and adjacent to the control gate electrode CG. Yes. The memory cell MC of the nonvolatile memory further includes an insulating film (gate insulating film) 3 formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1), the memory gate electrode MG, and the semiconductor substrate 1 The insulating film 5 is formed between the (p-type well PW1) and between the memory gate electrode MG and the control gate electrode CG.

  The control gate electrode CG and the memory gate electrode MG extend along the main surface of the semiconductor substrate 1 and are arranged side by side with the insulating film 5 interposed between the opposing side surfaces (side walls). The extending direction of the control gate electrode CG and the memory gate electrode MG is a direction perpendicular to the paper surface of FIG. The control gate electrode CG and the memory gate electrode MG are disposed above the semiconductor substrate 1 (p-type well PW1) between the semiconductor region MD and the semiconductor region MS via insulating films 3 and 5 (however, the control gate electrode CG is an insulating film). 3, the memory gate electrode MG is formed via the insulating film 5), the memory gate electrode MG is located on the semiconductor region MS side, and the control gate electrode CG is located on the semiconductor region MD side.

  The control gate electrode CG and the memory gate electrode MG are adjacent to each other with the insulating film 5 interposed therebetween, and the memory gate electrode MG is disposed on the side wall of the control gate electrode CG via the insulating film 5 via the sidewall spacer. It is formed in a shape. The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. .

  An insulating film 3 (that is, an insulating film 3 under the control gate electrode CG) formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1) functions as a gate insulating film of the control transistor, and is a memory gate. The insulating film 5 between the electrode MG and the semiconductor substrate 1 (p-type well PW1) (that is, the insulating film 5 under the memory gate electrode MG) is a gate insulating film of the memory transistor (a gate insulating film having a charge storage portion inside). ).

  The insulating film 3 can be formed of, for example, a silicon oxide film or a silicon oxynitride film. The insulating film 3 is a metal oxide having a dielectric constant higher than that of the silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, in addition to the above-described silicon oxide film or silicon oxynitride film. A membrane may be used.

  The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. The configuration (structure) of the insulating film 5 is different between a region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and a region between the memory gate electrode MG and the control gate electrode CG.

  That is, the insulating film 5 includes a silicon oxide film (silicon oxide layer) 6a, a silicon nitride film (silicon nitride layer, charge storage layer) 6b on the silicon oxide film 6a, and a silicon oxide film (oxidized film) on the silicon nitride film 6b. The silicon layer 6c has a region having a laminated structure and the silicon oxide films 6a and 6c, but there is no silicon nitride film 6b between the silicon oxide films 6a and 6c, and a cavity CAV exists instead. And a region that has Although details will be described later, the insulating film 5 was formed as a laminated film of the silicon oxide film 6a, the silicon nitride film 6b on the silicon oxide film 6a, and the silicon oxide film 6c on the silicon nitride film 6b at the time of formation. However, by removing a part of the silicon nitride film 6b after that, the part from which the silicon nitride film 6b is removed becomes a cavity CAV. Therefore, the insulating film 5 has no cavity CAV in the region having the silicon nitride film 6b (that is, the region in which the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are stacked). On the other hand, the silicon nitride film 6b is not present in the region where the cavity CAV is formed between the silicon oxide films 6a and 6c. For this reason, the cavity CAV and the silicon nitride film 6b are adjacent to each other, and the end of the silicon nitride film 6b forms a part of the inner wall of the cavity CAV adjacent to the cavity CAV. Further, since the portion from which the silicon nitride film 6b has been removed is a cavity CAV, the thickness of the cavity CAV and the thickness of the silicon nitride film 6b are substantially the same. Here, the thickness of the cavity CAV corresponds to the thickness (dimension) in a direction parallel to the thickness direction of the silicon oxide films 6a and 6c sandwiching the cavity CAV. Further, the silicon oxide film 6 a is integrally formed over the entire insulating film 5, and the silicon oxide film 6 c is formed integrally over the entire insulating film 5.

  A portion of the insulating film 5 located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) functions as a gate insulating film of the memory transistor. On the other hand, the portion of the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG is an insulating film for insulating (electrically separating) the memory gate electrode MG and the control gate electrode CG. Function.

  The gate insulating film of the memory transistor has a charge storage portion, and the silicon nitride film 6b is the charge storage portion. That is, in the insulating film 5, the silicon nitride film 6b is an insulating film for accumulating charges and functions as a charge accumulation layer (charge accumulation portion). That is, the silicon nitride film 6 b is a trapping insulating film formed in the insulating film 5. Therefore, a portion of the insulating film 5 that is a laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c has a charge storage portion (charge storage layer, here, the silicon nitride film 6b). ). The silicon oxide film 6c and the silicon oxide film 6a located above and below the silicon nitride film 6b can function as a charge block layer (charge block film, charge confinement layer). With the structure in which the silicon nitride film 6b is sandwiched between the silicon oxide film 6c and the silicon oxide film 6a, charges can be accumulated in the silicon nitride film 6b.

  In the present embodiment, a portion of the insulating film 5 located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) has a silicon nitride film 6b sandwiched between silicon oxide films 6a and 6c. The silicon nitride film 6b functions as a charge storage portion, while the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG has a cavity CAV. That is, a portion of the insulating film 5 between the lower surface of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1) is sandwiched between the silicon oxide films 6a and 6c and the silicon oxide films 6a and 6c. A portion of the insulating film 5 between the side surface of the control gate electrode CG and the side surface of the memory gate electrode MG is sandwiched between the silicon oxide films 6a and 6c and the silicon oxide films 6a and 6c. The cavity CAV is included and the silicon nitride film 6b is not included.

  As described above, the insulating film 5 located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) mainly has a laminated structure of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c. On the other hand, a portion of the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG mainly includes a cavity CAV between the silicon oxide film 6a and the silicon oxide film 6c and the silicon oxide films 6a and 6c. It consists of and.

  The reason why the insulating film 5 has such a configuration will be described later in detail.

  The upper part of the cavity CAV is in a state (covered state) closed by an insulating film part (insulator part) 10a sandwiched between the silicon oxide film 6a and the silicon oxide film 6c. Although details will be described later, the insulating film portion 10a is formed by a part of an insulating film (corresponding to an insulating film 10 described later) for forming the sidewall spacer SW2, and an insulator (of the sidewall spacer SW2). At least part of the same kind of insulator material), but preferably made of silicon oxide. Therefore, the cavity CAV is surrounded by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a. The inner wall of the cavity CAV is surrounded by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a. Is formed.

The semiconductor region MS is a semiconductor region that functions as one of a source region or a drain region, and the semiconductor region MD is a semiconductor region that functions as the other of a source region or a drain region. Here, the semiconductor region MS is a semiconductor region functioning as a source region, and the semiconductor region MD is a semiconductor region functioning as a drain region. The semiconductor regions MS and MD are each composed of a semiconductor region (n-type impurity diffusion layer) into which n-type impurities are introduced, and each has an LDD (lightly doped drain) structure. That is, the source semiconductor region MS includes an n ⁻ type semiconductor region (extension region) 9a and an n ⁺ type semiconductor region (source region) 11a having an impurity concentration higher than that of the n ⁻ type semiconductor region 9a. The semiconductor region MD for drain has an n ⁻ type semiconductor region (extension region) 9b and an n ⁺ type semiconductor region (drain region) 11b having an impurity concentration higher than that of the n ⁻ type semiconductor region 9b. The n ⁺ type semiconductor region 11a has a deeper junction depth and higher impurity concentration than the n ⁻ type semiconductor region 9a, and the n ⁺ type semiconductor region 11b has a deeper junction depth than the n ⁻ type semiconductor region 9b. And the impurity concentration is high.

  On the side walls (side walls not adjacent to each other) of the memory gate electrode MG and the control gate electrode CG, side wall insulating films (side walls, side wall spacers, side wall spacers, offset spacers) made of an insulator (insulating film) SW1 is formed. Furthermore, sidewall spacers (sidewalls) made of an insulator (insulating film) are formed on the sidewalls (sidewalls not adjacent to each other) of the memory gate electrode MG and the control gate electrode CG via the sidewall insulating film SW1. , Sidewall spacers, sidewall insulating films) SW2 are formed. That is, the side (side surface) of the memory gate electrode MG opposite to the side adjacent to the control gate electrode CG via the insulating film 5 and the side adjacent to the memory gate electrode MG via the insulating film 5 are opposite. A side wall insulating film SW1 and a side wall spacer SW2 are formed on the side wall (side surface) of the control gate electrode CG on the side, and the side wall insulating film SW1 is far from the side close to the memory gate electrode MG and the control gate electrode CG. Side wall spacers SW2 are arranged on the side.

The n ⁻ type semiconductor region 9a of the source part is formed in a self-aligned manner with respect to the sidewall insulating film SW1 on the sidewall of the memory gate electrode MG, and the n ⁺ type semiconductor region 11a is formed on the sidewall of the memory gate electrode MG. It is formed in a self-aligned manner with respect to the sidewall spacer SW2 formed through SW1. Therefore, the low concentration n ⁻ type semiconductor region 9a is formed under the sidewall spacer SW2 on the side wall of the memory gate electrode MG, and the high concentration n ⁺ type semiconductor region 11a is the low concentration n ⁻ type semiconductor region 9a. It is formed outside. Accordingly, the lightly doped n ⁻ type semiconductor region 9a is formed adjacent to the channel region of the memory transistor, the heavily doped n ⁺ type semiconductor region 11a is in contact with the lightly doped n ⁻ type semiconductor region 9a, and The n ⁻ type semiconductor region 9a is formed so as to be separated from the channel region.

The n ⁻ type semiconductor region 9b in the drain portion is formed in a self-aligned manner with respect to the sidewall insulating film SW1 on the sidewall of the control gate electrode CG, and the n ⁺ type semiconductor region 11b is formed on the sidewall of the control gate electrode CG. It is formed in a self-aligned manner with respect to the sidewall spacer SW2 formed through SW1. Therefore, the low concentration n ⁻ type semiconductor region 9b is formed under the sidewall spacer SW2 on the side wall of the control gate electrode CG, and the high concentration n ⁺ type semiconductor region 11b is the low concentration n ⁻ type semiconductor region 9b. It is formed outside. Therefore, the low concentration n ⁻ type semiconductor region 9b is formed adjacent to the channel region of the control transistor, the high concentration n ⁺ type semiconductor region 11b is in contact with the low concentration n ⁻ type semiconductor region 9b, and the control transistor The n ⁻ type semiconductor region 9b is formed so as to be separated from the channel region.

  A channel region of the memory transistor is formed under the insulating film 5 under the memory gate electrode MG, and a channel region of the control transistor is formed under the insulating film 3 under the control gate electrode CG. In the channel formation region of the control transistor under the insulating film 3 under the control gate electrode CG, a semiconductor region (p-type semiconductor region or n-type semiconductor region) for adjusting the threshold value of the control transistor is formed as necessary. In the channel formation region of the memory transistor under the insulating film 5 under the memory gate electrode MG, a semiconductor region for adjusting the threshold value of the memory transistor (p-type semiconductor region or n-type semiconductor region) is formed as necessary. Has been.

  The control gate electrode CG is made of a conductor (conductor film), but is preferably made of a silicon film 4n such as an n-type polysilicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). The silicon film 4n is preferably an n-type silicon film and has a low resistivity by introducing n-type impurities. Specifically, the control gate electrode CG is made of a patterned silicon film 4n.

  The memory gate electrode MG is made of a conductor (conductor film), but is preferably made of a silicon film 7n. The silicon film 7n is preferably an n-type silicon film and has a low resistivity by introducing n-type impurities. The silicon film 7n is more preferably an n-type polysilicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). As will be described later, the memory gate electrode MG is formed by anisotropically etching a silicon film 7n formed on the semiconductor substrate 1 so as to cover the control gate electrode CG, and an insulating film 5 is interposed on the side wall of the control gate electrode CG. It is formed by leaving this silicon film 7n. For this reason, the memory gate electrode MG is formed in the shape of a sidewall spacer on the sidewall of the control gate electrode CG via the insulating film 5.

The upper portion (upper surface) of the memory gate electrode MG (the silicon film 7n constituting the memory gate), the upper portion (upper surface) of the control gate electrode CG (the silicon film 4n constituting the memory gate electrode CG), and the upper portions (upper surface, surface) of the n ⁺ type semiconductor regions 11a and 11b. ), A metal silicide layer (metal silicide film) 13 is formed by a salicide (Salicide: Self Aligned Silicide) technique or the like. The metal silicide layer 13 is made of, for example, a cobalt silicide layer or a nickel silicide layer. The metal silicide layer 13 can reduce diffusion resistance and contact resistance. A combination of the silicon film 4n constituting the control gate electrode CG and the metal silicide layer 13 on the upper part thereof can be regarded as the control electrode CG, and the silicon film 7n constituting the memory gate electrode MG, The combination of the upper metal silicide layer 13 can also be regarded as the memory gate electrode MG. In addition, from the viewpoint of preventing a short circuit between the memory gate electrode MG and the control gate electrode CG as much as possible, the metal silicide layer 13 may not be formed on one or both of the memory gate electrode MG and the control gate electrode CG. obtain.

  On the semiconductor substrate 1, an insulating film 14 and an insulating film 15 on the insulating film 14 are formed so as to cover the control gate electrode CG, the memory gate electrode MG, the side wall insulating film SW1, and the side wall spacer SW2. The insulating film 14 is thinner than the insulating film 15 and is preferably made of a silicon nitride film. The insulating film 15 is thicker than the insulating film 14 and is preferably made of a silicon oxide film. As will be described later, contact holes CNT are formed in the insulating films 14 and 15, plugs PG are embedded in the contact holes CNT, and wirings M1 and the like are formed on the insulating film 15 in which the plugs PG are embedded. The illustration is omitted in FIGS. 1 and 2. The insulating film 15 functions as an interlayer insulating film, and the insulating film 14 can function as an etching stopper film when a contact hole CNT described later is formed in the insulating film 15.

  FIG. 4 is a table showing an example of voltage application conditions to each part of the selected memory cell during “write”, “erase”, and “read” in the present embodiment. The table of FIG. 4 shows the voltage applied to the memory gate electrode MG of the memory cell (selected memory cell) as shown in FIGS. 1 and 2 at the time of “write”, “erase”, and “read”. Vmg, voltage Vs applied to the source region (semiconductor region MS), voltage Vcg applied to the control gate electrode CG, voltage Vd applied to the drain region (semiconductor region MD), and base voltage Vb applied to the p-type well PW1 Is described. Note that what is shown in the table of FIG. 4 is a preferred example of the voltage application conditions, and is not limited to this, and can be variously changed as necessary. In the present embodiment, the electron injection into the silicon nitride film 6b, which is the charge storage portion (charge storage layer) in the insulating film 5 of the memory transistor, is “writing”, and the injection of holes (holes). Is defined as “erase”.

  In the table of FIG. 4, the column A corresponds to the case where the writing method is the SSI method and the erasing method is the BTBT method, and the column B is the writing method is the SSI method and the erasing method is the FN method. The column C corresponds to the case where the writing method is the FN method and the erasing method is the BTBT method, and the column D is the case where the writing method is the FN method and the erasing method is the FN method. It corresponds to.

  The SSI method can be regarded as an operation method in which a memory cell is written by injecting hot electrons into the silicon nitride film 6b. The BTBT method is an erasure of the memory cell by injecting hot holes into the silicon nitride film 6b. The FN method can be regarded as an operation method in which writing or erasing is performed by electron or hole tunneling. In other words, the FN method writing can be regarded as an operation method in which memory cells are written by injecting electrons into the silicon nitride film 6b by the FN tunnel effect. Can be regarded as an operation method in which memory cells are erased by injecting holes into the silicon nitride film 6b by the FN tunnel effect. This will be specifically described below.

  There are two writing methods: a so-called SSI (Source Side Injection) method that writes by hot electron injection by source side injection (hot electron injection writing method) and a so-called FN method called FN (Fowler Nordheim). There is a writing method (tunneling writing method) in which writing is performed by tunneling.

  In the SSI writing, for example, voltages (Vmg = 10V, Vs = 5V, Vcg = 1V, Vd = 0.5V) as shown in the “write operation voltage” in the column A or B in the table of FIG. , Vb = 0 V) is applied to each part of the selected memory cell to be written, and writing is performed by injecting electrons into the silicon nitride film 6b in the insulating film 5 of the selected memory cell. At this time, hot electrons are generated in a channel region (between the source and drain) between the two gate electrodes (memory gate electrode MG and control gate electrode CG), and in the insulating film 5 below the memory gate electrode MG. Hot electrons are injected into the silicon nitride film 6b which is a charge storage portion. The injected hot electrons (electrons) are trapped in the trap level in the silicon nitride film 6b in the insulating film 5, and as a result, the threshold voltage of the memory transistor rises (becomes a write state).

  In the FN system writing, for example, voltages (Vmg = −12V, Vs = 0V, Vcg = 0V, Vd = 0V, as shown in “writing operation voltage” in the column C or D in the table of FIG. Vb = 0V) is applied to each part of the selected memory cell to be written, and electrons are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b in the insulating film 5 in the selected memory cell. Do. At this time, electrons are injected from the memory gate MG through the silicon oxide film 6 c by FN tunneling (FN tunneling effect) and injected into the insulating film 5, and are trapped by trap levels in the silicon nitride film 6 b in the insulating film 5. As a result, the threshold voltage of the memory transistor increases (becomes a write state).

  In the FN mode writing, writing can also be performed by tunneling electrons from the semiconductor substrate 1 and injecting the electrons into the silicon nitride film 6b in the insulating film 5. In this case, the writing operation voltage is, for example, FIG. The “write operation voltage” in the column C or D in the table of FIG.

  The erasing method includes an erasing method (hot hole injection erasing method) in which erasing is performed by hot hole injection by BTBT (Band-To-Band Tunneling) called a BTBT method, and an FN (Fowler) called a FN method. There is an erasing method (tunneling erasing method) that performs erasing by tunneling.

  In the BTBT erasure, erasure is performed by injecting holes generated by BTBT (Band-To-Band Tunneling) into the charge storage portion (the silicon nitride film 6b in the insulating film 5). For example, the voltage (Vmg = −6V, Vs = 6V, Vcg = 0V, Vd = open, Vb = 0V) as shown in the “erase operation voltage” in the column A or C in the table of FIG. Is applied to each part of the selected memory cell. As a result, holes are generated by the BTBT (Band-To-Band Tunneling) phenomenon and the electric field is accelerated to inject holes into the silicon nitride film 6b in the insulating film 5 of the selected memory cell. The threshold voltage of the transistor is lowered (becomes an erased state).

  In the FN type erasure, for example, voltages (Vmg = 12 V, Vs = 0 V, Vcg = 0 V, Vd = 0 V, Vb = 0V) is applied to each part of the selected memory cell to be erased, and in the selected memory cell, holes (holes) are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b in the insulating film 5. Erase. At this time, holes are injected into the insulating film 5 by tunneling the silicon oxide film 6 c from the memory gate MG by FN tunneling (FN tunneling effect), and trapped in trap levels in the silicon nitride film 6 b in the insulating film 5. As a result, the threshold voltage of the memory transistor decreases (becomes an erased state).

  In FN erasing, erasing can also be performed by tunneling holes from the semiconductor substrate 1 and injecting them into the silicon nitride film 6b in the insulating film 5. In this case, the erasing operation voltage is, for example, as shown in FIG. The sign of “erase operation voltage” in the column B or D in the table can be reversed.

  When writing or erasing is performed by the FN method (that is, in the case of the operation methods B, C, and D), when charges are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b, the silicon oxide film 6c It is preferable to make the film thickness thinner than the film thickness of the silicon oxide film 6a. On the other hand, when writing or erasing is performed by the FN method (that is, in the case of the operation methods B, C, and D), when charges are tunneled from the semiconductor substrate 1 and injected into the silicon nitride film 6b, the film of the silicon oxide film 6a It is preferable to make the thickness smaller than the thickness of the silicon oxide film 6c. In addition, when the writing is the SSI method and the erasing is the BTBT method (that is, the operation method A), the thickness of the silicon oxide film 6c is preferably set to be equal to or larger than the thickness of the silicon oxide film 6a.

  At the time of reading, for example, a voltage as shown in “reading operation voltage” in the columns A, B, C, or D in the table of FIG. 4 is applied to each part of the selected memory cell to be read. . The voltage Vmg applied to the memory gate electrode MG at the time of reading is set to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage in the erasing state, thereby discriminating between the writing state and the erasing state. can do.

  In the following, for simplification, the case where the writing is the SSI method and the erasing is the BTBT method is referred to as operation method A, and the case where the writing is the SSI method and the erasing is FN method is referred to as the operation method B. Is the operation method C, and the writing is the FN method and the erasing is the FN method, and the operation method D is called the FN method. In the operation method A, for example, the operation voltage in the column A in the table of FIG. 4 can be used. In the operation method B, for example, the operation voltage in the column B of the table in FIG. 4 can be used. In C, for example, the operating voltage in the column C of the table of FIG. 4 can be used, and in the operation method D, for example, the operating voltage in the column of D in the table of FIG. 4 can be used.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described.

  FIG. 5 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the present embodiment. 6 to 32 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. Among these, the cross-sectional views of FIGS. 6 to 15, 17, 18, 20, 21, 23, 25, and 27 to 32 show the memory cell region (the memory cell MC of the non-volatile memory). 1A and a peripheral circuit region (region where a circuit other than a non-volatile memory is formed) 1B are shown. The memory cell MC is shown in the memory cell region 1A, and the peripheral circuit region 1B is shown in the memory cell region 1B. A state in which MISFETs are formed is shown. 16 corresponds to the partially enlarged sectional view of FIG. 15, FIG. 19 corresponds to the partially enlarged sectional view of FIG. 18, FIG. 22 corresponds to the partially enlarged sectional view of FIG. 21, and FIG. 26 corresponds to the partially enlarged sectional view, and FIG. 26 corresponds to the partially enlarged sectional view of FIG. The memory cell region 1A and the peripheral circuit region 1B are formed on the same semiconductor substrate 1. Although the memory cell region 1A and the peripheral circuit region 1B do not have to be adjacent to each other, for the sake of easy understanding, FIGS. 6 to 15, 17, 18, 20, 20, 21, 23, 25, and 25 27 to 32, the peripheral circuit region 1B is shown next to the memory cell region 1A. Here, the peripheral circuits are, for example, a processor such as a CPU, a control circuit, a sense amplifier, a column decoder, a row decoder, an input / output circuit, and the like.

  In the present embodiment, the case where an n-channel MISFET (control transistor and memory transistor) is formed in the memory cell region 1A will be described. However, the p-channel MISFET (control transistor and Memory transistor) can also be formed in the memory cell region 1A. Similarly, in this embodiment, the case where an n-channel type MISFET is formed in the peripheral circuit region 1B will be described, but a p-channel type MISFET may be formed in the peripheral circuit region 1B with the conductivity type reversed. In addition, a CMISFET (Complementary MISFET) or the like can be formed in the peripheral circuit region 1B.

  As shown in FIG. 6, first, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared (prepared) (step S1 in FIG. 5). Then, an element isolation region (inter-element isolation insulating region) 2 that defines (defines) an active region is formed on the main surface of the semiconductor substrate 1 (step S2 in FIG. 5). The element isolation region 2 is made of an insulator such as silicon oxide, and can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 can be formed by forming an element isolation groove in the main surface of the semiconductor substrate 1 and then embedding an insulating film made of, for example, silicon oxide in the element isolation groove. .

  Next, as shown in FIG. 7, a p-type well PW1 is formed in the memory cell region 1A of the semiconductor substrate 1 and a p-type well PW2 is formed in the peripheral circuit region 1B (step S3 in FIG. 5). The p-type wells PW1 and PW2 can be formed by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate 1, for example. The p-type wells PW1 and PW2 are formed from the main surface of the semiconductor substrate 1 to a predetermined depth.

  Next, in order to adjust the threshold voltage of a control transistor formed later in the memory cell region 1A, a channel is formed with respect to the surface portion (surface layer portion) of the p-type well PW1 in the memory cell region 1A as necessary. Dope ion implantation is performed. Further, in order to adjust the threshold voltage of the MISFET formed later in the peripheral circuit region 1B, channel dope ions are applied to the surface portion (surface layer portion) of the p-type well PW2 in the peripheral circuit region 1B as necessary. Make an injection.

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW2) by dilute hydrofluoric acid cleaning or the like, the main surface of the semiconductor substrate 1 (surfaces of the p-type wells PW1, PW2) is used for the gate insulating film. The insulating film 3 is formed (step S4 in FIG. 5). The insulating film 3 can be formed of, for example, a thin silicon oxide film or a silicon oxynitride film. The film thickness (formed film thickness) of the insulating film 3 can be set to, for example, about 2 to 3 nm.

  Next, as shown in FIG. 8, a silicon film 4 is formed (deposited) on the main surface (entire main surface) of the semiconductor substrate 1, that is, on the insulating film 3, as a gate electrode conductor film (FIG. 8). 5 step S5). The silicon film 4 is made of a polycrystalline silicon film and can be formed using a CVD (Chemical Vapor Deposition) method or the like. The film thickness (deposition film thickness) of the silicon film 4 can be set to, for example, about 50 to 250 nm. At the time of film formation, the silicon film 4 can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  After the silicon film 4 is formed, a photoresist pattern (not shown here, but this photoresist pattern is formed over the entire peripheral circuit region 1B) is formed on the silicon film 4 by photolithography. An n-type silicon film 4n is formed in the memory cell region 1A by introducing an n-type impurity into the memory cell region 1A (the silicon film 4) by an ion implantation method or the like using the resist pattern as a mask. That is, an n-type impurity is introduced into the silicon film 4 in the memory cell region 1A, and the silicon film 4 in the memory cell region 1A becomes an n-type silicon film 4n into which the n-type impurity is introduced.

  Next, as shown in FIG. 9, the n-type silicon film 4n in the memory cell region 1A is patterned by etching to form a control gate electrode CG (step S6 in FIG. 5). The patterning process of step S6 can be performed as follows, for example.

  That is, a photoresist pattern is formed on the silicon 4n and 4 using a photolithography method (although not shown here, this photoresist pattern is formed in the entire region of the control gate electrode CG and the peripheral circuit region 1B). Then, using this photoresist pattern as an etching mask, the silicon film 4n in the memory cell region 1A is etched (dry etching) and patterned. Thereafter, the photoresist pattern is removed.

  In this manner, the silicon film 4n is patterned in step S6, and as shown in FIG. 9, the control gate electrode CG made of the patterned silicon film 4n is formed in the memory cell region 1A. At this time, since the photoresist pattern is formed in the peripheral circuit region 1B as described above, the silicon film 4 is not patterned. In the memory cell region 1A, the insulating film 3 remaining under the control gate electrode CG becomes a gate insulating film of the control transistor. Therefore, the control gate electrode CG made of the silicon film 4n is formed on the semiconductor substrate 1 (p-type well PW1) via the insulating film 3 as a gate insulating film.

  In the memory cell region 1A, the insulating film 3 other than the portion covered with the control gate electrode CG (that is, the insulating film 3 other than the portion that becomes the gate insulating film) is dry-etched in the patterning process of step S6 or the dry film thereof. It can be removed by wet etching after etching.

  Next, in order to adjust the threshold voltage of a memory transistor formed later in the memory cell region 1A, the surface portion (surface layer portion) of the p-type well PW1 in the memory cell region 1A is adjusted as necessary. Channel doped ion implantation is performed.

  Next, after performing a cleaning process to clean the main surface of the semiconductor substrate 1, as shown in FIG. 10, the main surface (front surface) of the semiconductor substrate 1 and the surface of the control gate electrode CG (upper surface and side surfaces). ), An insulating film 5 made of a laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c is formed (step S7 in FIG. 5).

  The insulating film 5 is an insulating film for a gate insulating film of the memory transistor, and is an insulating film having a charge storage portion (charge storage layer) inside, and a silicon oxide film (oxide film) 6a formed in order from the bottom. It consists of a laminated film (ONO film) of a silicon nitride film (nitride film) 6b and a silicon oxide film (oxide film) 6c. That is, the insulating film 5 includes a silicon oxide film (oxide film) 6a, a silicon nitride film (nitride film) 6b on the silicon oxide film 6a, and a silicon oxide film (oxide film) 6c on the silicon nitride film 6b. It consists of a membrane. In step S7, as shown in FIG. 10, the insulating film 5 includes the surface of the semiconductor substrate 1 that is not covered with the control gate electrode CG and the silicon film 4, and the surface (side surface and upper surface) of the control gate electrode CG. And on the surface (side surface and upper surface) of the silicon film 4.

  Of the insulating film 5, the silicon oxide films 6a and 6c can be formed by, for example, an oxidation process (thermal oxidation process), a CVD method, or a combination thereof. It is possible to use ISSG (In Situ Steam Generation) oxidation for the oxidation treatment (thermal oxidation treatment) at this time. Of the insulating film 5, the silicon nitride film 6b can be formed by, for example, a CVD method.

  In order to form the insulating film 5, for example, first, the silicon oxide film 6a is formed on the surface of the semiconductor substrate 1, on the surface (side surface and upper surface) of the control gate electrode CG, and on the surface (side surface and upper surface) of the silicon film 4. Is formed by a thermal oxidation method (preferably ISSG oxidation), a silicon nitride film 6b is deposited on the silicon oxide film 6a by a CVD method, and a silicon oxide film 6c is further formed on the silicon nitride film 6b by a CVD method or thermal oxidation. Alternatively, both are formed. Thereby, the insulating film 5 composed of a laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c can be formed.

  The thickness of the silicon oxide film 6a can be, for example, about 2 to 10 nm, the thickness of the silicon nitride film 6b can be, for example, about 5 to 15 nm, and the thickness of the silicon oxide film 6c can be, for example, 2 to 10 nm. Can be about. The last oxide film (the uppermost silicon oxide film 6c in the insulating film 5) is formed by oxidizing the upper layer portion of, for example, the nitride film (the intermediate silicon nitride film 6b in the insulating film 5). A high breakdown voltage film can also be formed.

  The insulating film 5 functions as a gate insulating film of a memory gate electrode MG to be formed later and has a charge holding function. Therefore, the insulating film 5 has a laminated structure of at least three layers so that it can function as a gate insulating film having a charge holding (charge accumulation) function of the memory transistor, and the outer layers (silicon oxide films 6a and 6c). The potential barrier height of the inner layer (silicon nitride film 6b) is lower than the potential barrier height. This is because, as in the present embodiment, the insulating film 5 includes a silicon oxide film 6a, a stacked film including a silicon nitride film 6b on the silicon oxide film 6a, and a silicon oxide film 6c on the silicon nitride film 6b. This can be achieved. At the stage where the insulating film 5 is formed in step S7, the entire insulating film 5 is composed of a laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c, and the cavity CAV has not yet been formed. .

  Next, as shown in FIG. 11, on the main surface (entire main surface) of the semiconductor substrate 1, that is, on the insulating film 5, in the memory cell region 1A, the peripheral circuit region is covered so as to cover the control gate electrode CG. In 1B, a silicon film 7n is formed (deposited) as a conductor film for forming the memory gate electrode MG so as to cover the silicon film 4 (step S8 in FIG. 5).

  The silicon film 7n is made of a polycrystalline silicon film and can be formed using a CVD method or the like. The film thickness (deposition film thickness) of the silicon film 7n can be, for example, about 30 to 150 nm. At the time of film formation, the silicon film 7n can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  The silicon film 7n has a low resistance by introducing an n-type impurity. An n-type impurity can be introduced into the silicon film 7n by ion implantation after the formation of the silicon film 7n, but an n-type impurity can also be introduced into the silicon film 7n when the silicon film 7n is formed. When introducing an n-type impurity when forming the silicon film 7n, the doping gas (gas for adding an n-type impurity) is included in the gas for forming the silicon film 7n so that the n-type impurity is introduced. The silicon film 7n can be formed. In any case, a silicon film 7n doped with n-type impurities is formed in the memory cell region 1A and the peripheral circuit region 1B.

  Next, the silicon film 7n is etched back (etching, dry etching, anisotropic etching) by an anisotropic etching technique (step S9 in FIG. 5).

  In the etch back process of step S9, the silicon film 7n is anisotropically etched (etched back) by an amount corresponding to the deposited film thickness of the silicon film 7n, so that both sides of the control gate electrode CG (on the insulating film 5) are formed. The silicon film 7n is left in the shape of a sidewall spacer, and the silicon film 7n in other regions is removed. As a result, as shown in FIG. 12, in the memory cell region 1A, the silicon film 7n remaining in the shape of a sidewall spacer on one of the sidewalls of the control gate electrode CG via the insulating film 5 is used. Then, the memory gate electrode MG is formed, and the silicon spacer SP1 is formed by the silicon film 7n remaining in the shape of the sidewall spacer on the other sidewall via the insulating film 5. The memory gate electrode MG is formed on the insulating film 5 so as to be adjacent to the control gate electrode CG with the insulating film 5 interposed therebetween.

  The silicon spacer SP1 can also be regarded as a side wall spacer made of a conductor, that is, a conductor spacer. The memory gate electrode MG and the silicon spacer SP1 are formed on the side walls opposite to each other of the control gate electrode CG, and have a substantially symmetrical structure with the control gate electrode CG interposed therebetween. Also, the silicon spacer SP1 can be formed on the sidewall of the silicon film 4 remaining in the peripheral circuit region 1B via the insulating film 5.

  At the stage where the etch back process of step S9 is performed, the insulating film 5 in the region not covered with the memory gate electrode MG and the silicon spacer SP1 is exposed. The insulating film 5 under the memory gate electrode MG in the memory cell region 1A becomes a gate insulating film of the memory transistor. Since the memory gate length (the gate length of the memory gate electrode MG) is determined by the deposited film thickness of the silicon film 7n, the memory gate length is adjusted by adjusting the deposited film thickness of the silicon film 7n deposited in step S8. Can do.

  Next, a photolithography technique is used to form a photoresist pattern (not shown) on the semiconductor substrate 1 so as to cover the memory gate electrode MG and expose the silicon spacer SP1. The silicon spacer SP1 is removed by dry etching using as an etching mask (step S10 in FIG. 5). Thereafter, the photoresist pattern is removed. As shown in FIG. 13, the silicon spacer SP <b> 1 is removed by the etching process of step S <b> 10, but the memory gate electrode MG remains unetched because it is covered with the photoresist pattern.

  Next, as shown in FIG. 14, a portion of the insulating film 5 that is exposed without being covered with the memory gate electrode MG is removed by etching (for example, wet etching) (step S11 in FIG. 5). At this time, in the memory cell region 1A, the insulating film 5 located under the memory gate electrode MG and between the memory gate electrode MG and the control gate electrode CG remains without being removed, and the insulating film 5 in other regions remains Removed.

  Next, a photoresist pattern is formed on the silicon film 4 formed in the peripheral circuit region 1B by using a photolithography method (although not shown here, a p-channel MISFET is to be formed in the entire memory cell region 1A and the peripheral circuit region 1B). This photoresist pattern is formed in the region), and using this photoresist pattern as a mask, an n-type impurity is introduced into the silicon film 4 in the peripheral circuit region 1B by ion implantation or the like. As a result, an n-type silicon film (corresponding to the silicon film 4 doped with n-type impurities in the peripheral circuit region 1B) is formed in the peripheral circuit region 1B. Thereafter, a photoresist pattern is formed on the n-type silicon film by using a photolithography method (although not shown here, this photoresist pattern is formed in the entire memory cell region 1A and the gate electrode GE formation region in the peripheral circuit region 1B). The n-type silicon film is etched (dry etching) and patterned using this photoresist pattern as an etching mask. At this time, the memory cell region 1A is covered with the photoresist pattern and is not etched. Thereafter, the photoresist pattern is removed. As a result, as shown in FIG. 15, a gate electrode GE made of a patterned n-type silicon film (that is, a patterned silicon film 4 doped with n-type impurities in the peripheral circuit region 1B) is formed. .

  FIG. 16 is a partially enlarged cross-sectional view of FIG. 15, and shows a part of the memory cell region 1A in FIG. 15 in an enlarged manner. As can be seen from FIG. 16, the insulating film 5 includes both a region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and a region between the memory gate electrode MG and the control gate electrode CG. The entire insulating film 5 is composed of a laminated film of a silicon oxide film 6a, a silicon nitride film 6b, and a silicon oxide film 6c. At this stage, the cavity CAV has not yet been formed in the insulating film 5.

  Next, as shown in FIG. 17, an insulating film 8 is formed on the main surface (entire main surface) of the semiconductor substrate 1 so as to cover the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE ( Step S12a in FIG.

  The insulating film 8 is preferably made of a silicon oxide film, and the formed film thickness (thickness) can be set to about 5 to 20 nm, for example. The insulating film 8 can be formed using, for example, a CVD method.

  Next, as shown in FIG. 18, the insulating film 8 is etched back (etching, dry etching, anisotropic etching) by an anisotropic etching technique (step S12b in FIG. 5). FIG. 19 is a partially enlarged cross-sectional view of FIG. 18, showing a part of the memory cell region 1A in FIG. 18 in an enlarged manner.

  In the etch back process of step S12b, the insulating film 8 is anisotropically etched (etched back) by the amount of the deposited film of the insulating film 8 so that the sidewalls of the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE are formed. Then, the insulating film 8 is left, and the insulating film 8 in other regions is removed. As a result, as shown in FIGS. 18 and 19, sidewall insulating films (sidewall spacers, offset spacers) made of the insulating film 8 remaining on the sidewalls of the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE. SW1 is formed.

  Side wall insulating film SW1 is formed on both side walls of gate electrode GE and on the side wall of control gate electrode CG opposite to the side wall adjacent to memory gate electrode MG through insulating film 5 Of the sidewalls of the memory gate electrode MG, the sidewalls on the side opposite to the sidewall adjacent to the control gate electrode CG via the insulating film 5 are formed.

In the present embodiment, the side wall of the memory gate electrode MG that is opposite to the side adjacent to the control gate electrode CG (via the insulating film 5) so that the cavity CAV can be accurately formed later. It is important that the sidewall insulating film SW1 is formed thereon. The sidewall insulating film SW1 can also function as an ion implantation element mask when forming extension regions (corresponding to the n ⁻ type semiconductor regions 9a, 9b, and 9c), as will be described later.

Next, an n-type impurity such as arsenic (As) or phosphorus (P) is removed from the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the side wall insulating film on the side walls using an ion implantation method or the like. By introducing (doping) into the semiconductor substrate 1 (p-type wells PW1, PW2) using SW1 as a mask (ion implantation blocking mask), an n ⁻ -type semiconductor region (impurity diffusion layer) 9a as shown in FIG. , 9b, 9c are formed (step S13 in FIG. 5).

At this time, the n ⁻ -type semiconductor region 9a includes a sidewall insulating film on the sidewall of the memory gate electrode MG (the sidewall opposite to the side adjacent to the control gate electrode CG via the insulating film 5) in the memory cell region 1A. It is formed in self-alignment with the side surface of SW1 (the side surface opposite to the side in contact with the control gate electrode CG). Further, the n ⁻ type semiconductor region 9b includes the sidewall insulating film SW1 on the sidewall of the control gate electrode CG (the sidewall opposite to the side adjacent to the memory gate electrode MG via the insulating film 5) in the memory cell region 1A. Is formed in a self-aligned manner on the side surface (the side surface opposite to the side in contact with the memory gate electrode MG). The n ⁻ type semiconductor region 9c is self-aligned with the side surface of the side wall insulating film SW1 on the both side walls of the gate electrode GE (the side surface opposite to the side in contact with the gate electrode GE) in the peripheral circuit region 1B. Formed. The n ⁻ type semiconductor region 9a and the n ⁻ type semiconductor region 9b function as a part of the source / drain region of the memory cell formed in the memory cell region 1A, and the n ⁻ type semiconductor region 9c is formed in the peripheral circuit region 1B. It can function as a part of the source / drain region of the MISFET.

Next, as shown in FIG. 21, the region extending over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG are extended. Of the existing insulating film 5, a part of the silicon nitride film 6b is removed by etching (step S14 in FIG. 5). The portion from which the silicon nitride film 6b is removed becomes a cavity CAV. 22 is a partially enlarged cross-sectional view of FIG. 21, in which a part of the memory cell region 1A in FIG. 21 is shown enlarged (in FIG. 22, the n ⁻ type semiconductor regions 9a and 9b are not shown). And included in the p-type well PW1).

  In this step S14, a portion of the silicon nitride film 6b between the side surface of the control gate electrode CG and the side surface of the memory gate electrode MG in the insulating film 5 is removed to form a cavity CAV.

  In the stage before performing step S14, the insulating film 5 includes both of a region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and a region between the memory gate electrode MG and the control gate electrode CG. The insulating film 5 as a whole extends over a region, and is composed of a laminated film (ONO film) of a silicon oxide film 6a, a silicon nitride film 6b, and a silicon oxide film 6c (state of FIG. 19). Corresponding). At this stage, the upper end portion 5a of the portion of the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG is exposed. Here, the upper end portion 5a of the insulating film 5 corresponds to the end portion of the insulating film 5 that is sandwiched between the upper portion of the memory gate electrode MG and the upper portion of the control gate electrode CG.

  In step S14, wet etching is preferably performed. At this time, an etching solution capable of selectively etching the silicon nitride film 6b constituting the insulating film 5 is used. That is, the etching rate of the silicon nitride film 6b is the same as the etching rate of the silicon oxide films 6a and 6c and the silicon films 4n, 7n and 4 (that is, the silicon films constituting the control gate electrode CG, the memory gate electrode MG and the gate electrode GE). An etching solution that is larger than the etching rate is used. In other words, an etchant is used that is easy to etch the silicon nitride film 6b and is less likely to etch the silicon oxide films 6a, 6c and the silicon films 4n, 6n, 4 than the silicon nitride film 6b. As the etchant, for example, hot phosphoric acid can be used. Thereby, in step S14, a part of the silicon nitride film 6b constituting the insulating film 5 is selectively removed by etching, and the silicon oxide films 6a and 6c constituting the insulating film 5, the control gate electrode CG, the memory It is possible to suppress or prevent etching of the silicon films 4n, 6n, and 4 constituting the gate electrode MG and the gate electrode GE.

  In the present embodiment, the insulating film 5 is formed by a laminated film (ONO film) of a silicon oxide film 6a, a silicon nitride film 6b, and a silicon oxide film 6c, and then the silicon nitride film 6b at a desired location is removed. ing. However, if the silicon nitride film 6b can be selectively etched in the etching process of the silicon nitride film 6b, the silicon oxide film 6a and the silicon oxide film 6c are not only silicon oxide films but also other insulating materials. It is also possible to form with a film. For example, a silicon oxynitride film in which nitrogen is introduced after forming a silicon oxide film does not have a large amount of nitrogen introduced, and if the etching rate of the silicon nitride film is sufficiently high, the silicon oxide film 6a and the silicon oxide film It is also possible to form the film 6c with a silicon oxynitride film or the like.

  Immediately before the etching process in step S14, the upper end portion 5a of the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG is exposed, while the memory gate electrode MG and the semiconductor substrate are exposed. A portion of the insulating film 5 located between 1 (p-type well PW1) does not have an exposed portion. This is because the side wall insulating film SW1 is formed on the side wall of the memory gate electrode MG (the side wall opposite to the side adjacent to the control gate electrode CG via the insulating film 5). This is because the end portion (end portion in contact with the side wall insulating film SW1) 5b of the portion of the insulating film 5 located between the semiconductor substrates 1 (p-type well PW1) is covered with the side wall insulating film SW1 and is not exposed. is there. That is, after the sidewall insulating film SW1 is formed in step S12b, the end 5b on the side of the insulating film 5 sandwiched between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) is the sidewall insulating film SW1. Covered and not exposed.

  Since the silicon nitride film 6b constituting the insulating film 5 is sandwiched between the silicon oxide films 6a and 6c, the silicon nitride film 6b is exposed at the end of the insulating film 5. Therefore, if the silicon nitride film 6b is to be etched in the etching process of step S14, the etching of the silicon nitride film 6b can proceed from the exposed portion of the end portion of the insulating film 5. However, since the exposed end portion of the insulating film 5 is the upper end portion 5a, the etching of the silicon nitride film 6b proceeds from the upper end portion 5a side of the insulating film 5 in the etching process of step S14. That is, in the etching process of step S14, the etching of the silicon nitride 6b film proceeds from the upper end 5a side sandwiched between the upper part of the control gate electrode CG and the upper part of the memory gate electrode MG in the insulating film 5. Etching of the silicon nitride film 6b does not proceed from the end 5b side of the silicon nitride film 6b.

  By adjusting the etching time and the like in the etching process of step S14, the distance at which the silicon nitride film 6b is etched away can be controlled. A portion of the insulating film 5 from which the silicon nitride film 6b has been removed becomes a cavity (space) CAV. That is, a part of the silicon nitride film 6b in the insulating film 5 is removed by the etching process in step S14 to form a cavity CAV. The material of the insulating film 5 does not exist in the cavity CAV.

  In the etching process of step S14, the silicon nitride film 6b is etched from the upper end portion 5a side of the insulating film 5, but in the portion of the insulating film 5 located between the side surface of the memory gate electrode MG and the side surface of the control gate electrode CG. Etching is preferably continued until all of the silicon nitride film 6b is removed. As a result, when the etching process of step S14 is completed, as shown in FIG. 22, the insulating film 5 in a portion located between the side surface of the memory gate electrode MG and the side surface of the control gate electrode CG is formed of a silicon nitride film. 6b is not provided, and the silicon oxide film 6a, the silicon oxide film 6c, and the cavity CAV between the silicon oxide films 6a and 6c can be formed.

  However, if the etching time in step S14 is too long, all of the silicon nitride film 6b is removed from the insulating film 5, and the insulating portion located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) is insulated. The film 5 also does not have the silicon nitride film 6b. However, in this case, since the charge storage portion does not exist in the insulating film 5, the operation as a nonvolatile memory cannot be performed. Therefore, the etching process in step S14 is performed before the entire silicon nitride film 6b is removed from the insulating film 5 in the portion located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1). finish. As a result, after the etching process in step S14, the insulating film 5 in a portion located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) has the silicon nitride film 6b. Since the silicon film 6b can function as a charge storage portion, it is possible to perform an operation as a nonvolatile memory. That is, the silicon nitride film 6b remaining between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) without being removed in step S14 (etching process of the silicon nitride film 6b) is a charge storage portion of the memory cell. It can function as a (charge storage layer).

Next, as shown in FIG. 23, an insulating film is formed on the main surface (entire main surface) of the semiconductor substrate 1 so as to cover the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the sidewall insulating film SW1. 10 is formed (step S15 in FIG. 5). 24 is a partially enlarged cross-sectional view of FIG. 23, in which a part of the memory cell region 1A in FIG. 23 is shown enlarged (in FIG. 24, the n ⁻ type semiconductor regions 9a and 9b are not shown). And included in the p-type well PW1).

  The insulating film 10 is preferably composed of a single film of a silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film in order from the bottom, or a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film in order from the bottom. . The formed film thickness (thickness) of the insulating film 10 can be, for example, about 30 to 100 nm. The insulating film 10 can be formed using, for example, a CVD method. The cavity CAV is closed (covered) by the insulating film 10 and becomes a closed space.

  As shown in FIG. 24, when the insulating film 10 is formed in step S15, the cavity CAV is covered with the insulating film 10, but a part of the insulating film 10 penetrates into the upper part of the cavity CAV, and the cavity CAV becomes the insulating film. A part of 10 (portion that has entered the upper part of the cavity CAV) is closed (covered). For this reason, after forming the cavity in step S14 and before forming the insulating film 10 in step S15, the cavity CAV was an open space in which the upper part (the part corresponding to the upper end part 5a) was opened. When the insulating film 10 is formed in step S15, the cavity CAV becomes a closed space in which the upper portion (the portion corresponding to the upper end portion 5a) is closed (closed) with the insulating film 10.

Next, as shown in FIG. 25, the insulating film 10 is etched back (etching, dry etching, anisotropic etching) by an anisotropic etching technique (step S16 in FIG. 5). 26 is a partially enlarged cross-sectional view of FIG. 25, in which a part of the memory cell region 1A in FIG. 25 is shown enlarged (in FIG. 26, the n ⁻ type semiconductor regions 9a and 9b are not shown). And included in the p-type well PW1).

  In the etch back process of step S16, the insulating film 10 is anisotropically etched (etched back) by the amount of the deposited film thickness of the insulating film 10, so that the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE are formed on the sidewalls. Then, the insulating film 10 is left in the form of a sidewall spacer, and the insulating film 10 in other regions is removed. Thus, as shown in FIGS. 25 and 26, sidewall spacers (sidewalls, sidewall spacers, side walls made of the remaining insulating film 10 are formed on the sidewalls of the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE. Side wall insulating film (SW2) is formed. The side wall spacer SW2 is made of the remaining insulating film 10, but the side wall spacer SW2 is formed on each side wall of the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE via the side wall insulating film SW1. .

  Specifically, a side wall spacer SW2 is formed on the side wall of the control gate electrode CG opposite to the side wall adjacent to the memory gate electrode MG via the side wall insulating film SW1, A side wall spacer SW2 is formed on the side wall of the memory gate electrode MG opposite to the side wall adjacent to the control gate electrode CG via the side wall insulating film SW1. Further, the side wall spacer SW2 is formed on both side walls of the gate electrode GE via the side wall insulating film SW1. That is, in the control gate electrode CG and the memory gate electrode MG, the side wall spacer SW2 is formed on the side wall opposite to the side adjacent to each other (via the side wall insulating film SW1).

  When the insulating film 10 is formed in step S15, a part of the insulating film 10 enters the upper part of the cavity CAV, and the cavity CAV is blocked by a part of the insulating film 10 (a part that enters the upper part of the cavity CAV) ( In this state, when the insulating film 10 is anisotropically etched by performing the etch-back process in step S16, the portion of the insulating film 10 that has entered the upper part of the cavity CAV is removed. The insulating film portion (insulator portion) 10a remains. That is, after the etch back process in step S16, a part of the insulating film 10 remains as the insulating film portion 10a on the cavity CAV.

  The insulating film portion 10a is formed by a part of the insulating film 10 (portion remaining between the silicon oxide film 6a and the silicon oxide film 6c). For this reason, the upper part of the cavity CAV is closed (covered) by the insulating film portion 10a sandwiched between the silicon oxide film 6a and the silicon oxide film 6c. That is, the cavity CAV becomes a closed space surrounded by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a, and the cavity CAV is formed by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a. The inner wall will be formed. After the cavity CAV is closed by the insulating film portion 10a, it can be maintained that the cavity CAV is a closed space. Since the cavity CAV is blocked by the insulating film portion 10a, unnecessary liquids (for example, various liquids used in the cleaning process, a photoresist material, or a metal film 12 described later) enter the cavity CAV. Can be prevented. From this point of view, it is preferable to form the insulating film 10 in step S15 without performing the photolithography process or other etching processes after the silicon nitride film 6b is etched in step S14 to form the cavity CAV.

  Since the insulating film portion 10a is composed of a lower layer portion of the insulating film 10, the insulating film 10 is a single film of a silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film, or a silicon oxide film, a silicon nitride film, and an oxide film. In any case of the laminated film of the silicon film, the insulating film portion 10a is made of silicon oxide. For this reason, the insulating film portion 10a is preferably made of silicon oxide. Since both the sidewall spacer SW2 and the insulating film portion 10a are formed by a part of the insulating film 10, the insulating film portion 10a is made of the same kind of insulator material as at least a part of the sidewall spacer SW2.

Next, as shown in FIG. 27, n ⁺ -type semiconductor regions (impurity diffusion layers) 11a, 11b, and 11c are formed using an ion implantation method or the like (step S17 in FIG. 5). For example, an n-type impurity such as arsenic (As) or phosphorus (P) is masked on the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE and the sidewall insulating film SW1 and the sidewall spacer SW2 on the sidewalls thereof ( By introducing it into the semiconductor substrate 1 (p-type wells PW1, PW2) using it as an ion implantation blocking mask), n ⁺ -type semiconductor regions 11a, 11b, 11c can be formed. At this time, the n ⁺ -type semiconductor region 11a is formed in self-alignment with the sidewall spacer SW2 on the sidewall of the memory gate electrode MG in the memory cell region 1A, and the n ⁺ -type semiconductor region 11b is formed in the memory cell region 1A. , Formed in self-alignment with the sidewall spacer SW2 on the sidewall of the control gate electrode CG. The n ⁺ type semiconductor region 11c is formed in self-alignment with the sidewall spacer SW2 on both side walls of the gate electrode GE in the peripheral circuit region 1B. Thereby, an LDD (lightly doped drain) structure is formed.

In this manner, the n ⁻ type semiconductor region 9 a functioning as the source region of the memory transistor is formed by the n ⁻ type semiconductor region 9 a and the n ⁺ type semiconductor region 11 a having a higher impurity concentration than that, thereby forming the n ⁻ type semiconductor. An n-type semiconductor region MD that functions as a drain region of the control transistor is formed by the region 9b and the n ⁺ -type semiconductor region 11b having a higher impurity concentration. The n ⁻ type semiconductor region 9c and the n ⁺ type semiconductor region 11c having a higher impurity concentration form an n type semiconductor region SD that functions as a source / drain region of the MISFET in the peripheral circuit region 1B.

Next, the impurities introduced into the n-type semiconductor regions MS, MD, SD (n ⁻ type semiconductor regions 9a, 9b, 9c and n ⁺ type semiconductor regions 11a, 11b, 11c) for the source and drain are activated. Activation annealing, which is a heat treatment for the purpose, is performed.

  In this manner, the memory cell MC of the nonvolatile memory is formed in the memory cell region 1A, and the MISFET is formed in the peripheral circuit region 1B.

Next, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1 by a CVD method or the like. Next, silicon surfaces (upper surfaces) of the n ⁺ type semiconductor regions 11a, 11b, and 11c, the upper surface of the control gate electrode CG, the upper surface of the memory gate electrode MG, and the upper surface of the gate electrode GE are formed by photolithography and etching. (Silicon region, silicon film) is exposed. Then, as shown in FIG. 28, on the upper surfaces (surfaces) of the n ⁺ -type semiconductor regions 11a, 11b, and 11c, on the upper surface of the memory gate electrode MG (portion not covered with the sidewall spacer SW2), and the control gate electrode The metal film 12 covers the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the sidewall spacer SW2 over the entire main surface of the semiconductor substrate 1 including the upper surface of the CG and the upper surface of the gate electrode GE. Is formed (deposited). The metal film 12 is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like.

Next, by subjecting the semiconductor substrate 1 to heat treatment, the upper layer portion (surface layer portion) of the n ⁺ type semiconductor regions 11a, 11b, and 11c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE is changed to the metal film 12. React with. As a result, as shown in FIG. 29, metal silicide is formed on the n ⁺ type semiconductor regions 11a, 11b, 11c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE, respectively (upper surface, surface, upper layer portion). Layer 13 is formed. The metal silicide layer 13 can be, for example, a cobalt silicide layer (when the metal film 12 is a cobalt film) or a nickel silicide layer (when the metal film 12 is a nickel film). Thereafter, the unreacted metal film 12 is removed. FIG. 29 shows a cross-sectional view at this stage. Thus, by performing the so-called salicide process, the metal silicide layer 13 is formed on the n ⁺ type semiconductor regions 11a, 11b, and 11c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE, thereby The resistance of the source, drain and each gate electrode (CG, MG, GE) can be reduced.

  Next, as shown in FIG. 30, an insulating film 14 is formed on the entire main surface of the semiconductor substrate 1 so as to cover the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the sidewall spacer SW2 ( The insulating film 15 is formed (deposited) on the insulating film 14. Then, the upper surface of the insulating film 15 is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary.

  The insulating film 14 is preferably made of a silicon nitride film, and the insulating film 15 on the insulating film 14 is preferably made of a silicon oxide film or the like, and each can be formed using a CVD method or the like. The insulating film 14 is thinner than the insulating film 15. The thick insulating film 15 functions as an interlayer insulating film, and the thin insulating film 14 functions as an etching stopper film when a contact hole is formed in the insulating film 15.

  Next, as shown in FIG. 31, the insulating film 15 and the insulating film 14 are dry-etched by using a photoresist pattern (not shown) formed on the insulating film 15 by photolithography as an etching mask. Then, contact holes (openings, through holes) CNT are formed in the insulating films 14 and 15. When forming the contact hole CNT, first, the insulating film 15 is dry-etched to cause the insulating film 14 to function as an etching stopper film, and then the insulating film 14 at the bottom of the contact hole CNT is removed by dry etching to provide insulation. A contact hole CNT penetrating the films 14 and 15 is formed. In this way, by causing the insulating film 14 to function as an etching stopper when etching the insulating film (interlayer insulating film) 15, when the contact hole CNT is formed by etching, the lower layer is damaged due to excessive digging. It is possible to avoid the deterioration of the processing dimensional accuracy.

The contact hole CNT is formed over the n ⁺ type semiconductor regions 11a, 11b, 11c, the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the like. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor regions 11a, 11b, 11c (the metal silicide layer 13 on the surface thereof), the control gate electrode CG (on the surface of the control hole electrode CG) Part of the metal silicide layer 13), part of the memory gate electrode MG (metal silicide layer 13 on the surface thereof), or part of the gate electrode GE (metal silicide layer 13 on the surface thereof), etc. are exposed. . In the cross-sectional view of FIG. 31, a cross section in which a part of the n ⁺ type semiconductor regions 11b and 11c (the metal silicide layer 13 on the surface thereof) is exposed at the bottom of the contact hole CNT is shown.

  Next, a conductive plug (connection conductor portion) PG made of tungsten (W) or the like is formed in the contact hole CNT. In order to form the plug PG, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the insulating film 15 including the inside (on the bottom and side walls) of the contact hole CNT. . Then, a main conductor film made of a tungsten film or the like is formed on the barrier conductor film so as to fill the contact holes CNT, and unnecessary main conductor films and barrier conductor films on the insulating film 15 are formed by a CMP method or an etch back method. By removing, the plug PG can be formed. For simplification of the drawing, FIG. 31 shows the barrier conductor film and the main conductor film (tungsten film) constituting the plug PG in an integrated manner.

  Next, as shown in FIG. 32, the insulating film 16 is formed on the insulating film 15 in which the plug PG is embedded. The insulating film 16 can also be formed of a stacked film of a plurality of insulating films.

  Next, the wiring M1 which is the first layer wiring is formed by a single damascene method. Specifically, the wiring M1 can be formed as follows. First, after a wiring groove is formed in a predetermined region of the insulating film 16 by dry etching using a photoresist pattern (not shown) as a mask, a barrier conductor film (on the insulating film 16 including the bottom and side walls of the wiring groove is formed. For example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like is formed. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by using an electrolytic plating method. Embed the inside. Then, the main conductor film (copper plating film and seed layer) and the barrier conductor film in the region other than the wiring trench are removed by the CMP method, and the first layer wiring using the copper buried in the wiring trench as the main conductive material M1 is formed. For simplification of the drawing, the wiring M1 is shown by integrating a barrier conductor film, a seed layer, and a copper plating film.

  The wiring M1 is connected via a plug PG to the source region (semiconductor region MS) of the memory transistor, the drain region (semiconductor region MD) of the control transistor, the source / drain region (semiconductor region SD) of the MISFET in the peripheral circuit region 1B, and the control gate. It is electrically connected to the electrode CG, the memory gate electrode MG, the gate electrode GE, or the like. Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here. Further, the wiring M1 and the wiring higher than that are not limited to damascene wiring, and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring.

  As described above, the semiconductor device of the present embodiment is manufactured.

  Next, the configuration and effects of the present embodiment will be described in more detail with reference to a comparative example.

  First, a semiconductor device of a comparative example will be described. FIGS. 33 and 34 are cross-sectional views of main parts of the semiconductor device of the comparative example, and correspond to FIGS. 1 and 2 of the present embodiment, respectively.

The semiconductor device of the comparative example shown in FIG. 33 and FIG. 34 is a semiconductor device having a memory cell of a nonvolatile memory, and a control gate electrode constituting the nonvolatile memory cell is formed above the p-type well PW101 of the semiconductor substrate 101. The CG 101 and the memory gate electrode MG101 are formed adjacent to each other. An insulating film 103 as a gate insulating film is formed between the control gate electrode CG101 and the p-type well PW101. Further, an insulating film made of a stacked film of a silicon oxide film 106a, a silicon nitride film 106b, and a silicon oxide film 106c is provided between the memory gate electrode MG101 and the p-type well PW101 and between the control gate electrode CG101 and the memory gate electrode MG101. A film 105 is formed. Control gate electrode CG101 and memory gate electrode MG101 are each formed of an n-type polysilicon film. In the p-type well PW101, a semiconductor region functioning as a source region is formed by an n ⁻ type semiconductor region 109a and an n ⁺ type semiconductor region 111a having a higher impurity concentration than that, and a semiconductor region functioning as a drain region is formed The n ⁻ type semiconductor region 109b and the n ⁺ type semiconductor region 111b having a higher impurity concentration than that are formed. A side wall insulating film SW101 is formed on the side wall of the control gate electrode CG101 and the memory gate electrode MG101 opposite to the side adjacent to each other. A metal silicide layer 113 is formed on the n ⁺ type semiconductor regions 111a and 111b, the control gate electrode CG101, and the memory gate electrode MG101. On the semiconductor substrate 101, a laminated film of insulating films 114 and 115 is formed as an interlayer insulating film so as to cover the control gate electrode CG101, the memory gate electrode MG101, and the sidewall spacer SW102.

  In the semiconductor device of the comparative example shown in FIGS. 33 and 34, the insulating film 105 includes the region between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101), the memory gate electrode MG101, and the control gate electrode CG101. The insulating film 105 as a whole is formed of a laminated film of a silicon oxide film 106a, a silicon nitride film 106b, and a silicon oxide film 106c. Therefore, the silicon nitride film 106b is not only in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101), but also in the insulating film 105 between the memory gate electrode MG101 and the control gate electrode CG101. Also exist.

  The semiconductor device of the comparative example having such a structure has the following problems (first problem and second problem).

  First, the first problem will be described. The memory gate electrode MG101 and the control gate electrode CG101 are adjacent to each other with a thin insulating film 105 interposed therebetween, and the withstand voltage between the memory gate electrode MG101 and the control gate electrode CG101 depends on the insulating film 105. Yes. However, the insulating film 105 extends over both the region between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101) and the region between the memory gate electrode MG101 and the control gate electrode CG101. . Since the thicknesses of the silicon oxide films 106a and 106c and the silicon nitride film 106b constituting the insulating film 105 are determined in consideration of the functions as the gate insulating film and the charge storage film of the memory transistor, the memory gate electrode MG101 and the control gate It is not easy to improve the withstand voltage between the memory gate electrode MG101 and the control gate electrode CG101 by adjusting the thickness of the insulating film 105 between the electrodes CG101.

  In addition, in order to improve the breakdown voltage between the memory gate electrode MG101 and the control gate electrode CG101, the thickness of each of the silicon oxide films 106a and 106c and the silicon nitride film 106b constituting the insulating film 105 is adjusted, whereby the memory gate electrode When the thickness of the insulating film 105 between the MG 101 and the control gate electrode CG101 is increased, there is a possibility that the read current of the nonvolatile memory is decreased or the write speed is decreased.

  That is, when the thickness of the insulating film 105 is increased, the distance L101 between the memory gate electrode MG101 and the control gate electrode CG101 (this distance L101 is shown in FIG. 34, and the thickness of the insulating film 105 is equal to the distance L101). Becomes larger). In the p-type well PW101, an electric field is hardly applied to both the memory gate electrode MG101 and the control gate electrode CG101 below the insulating film 105 interposed between the memory gate electrode MG101 and the control gate electrode CG101. Is formed in a region 121 (this region 121 is shown in FIG. 33). The dimension of the region 121 in the gate length direction is the distance L101 between the memory gate electrode MG101 and the control gate electrode CG101 (that is, the thickness of the insulating film 105 interposed between the memory gate electrode MG101 and the control gate electrode CG101). The bigger it gets, the bigger it gets. Since this region 121 becomes a resistance component, when the distance L101 (corresponding to the film thickness of the insulating film 105) increases and the size of the region 121 in the gate length direction increases, the read current of the memory cell of the nonvolatile memory increases. (Current value flowing between the source and drain during the read operation) may decrease, or the write speed may decrease. Therefore, a technique that can improve the withstand voltage between the memory gate electrode MG101 and the control gate electrode CG101 without increasing the distance L101 between the memory gate electrode MG101 and the control gate electrode CG101 is desired.

  Next, the second problem will be described. As described above, the writing method to the nonvolatile memory includes the SSI method and the FN method, and the erasing method includes the BTBT method and the FN method. When writing to the nonvolatile memory, electrons are injected into the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101) in both cases of the SSI method and the FN method. . When erasing the non-volatile memory, in both the BTBT method and the FN method, holes are formed in the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101). Inject.

  When writing by the SSI method, electrons are not uniformly injected into the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101), but hot electrons are injected. Due to the location of occurrence of electrons, electrons tend to be injected at a higher density into a region closer to the control gate electrode CG (that is, closer to the drain region) than to a region on the source region side.

  In addition, in the FN method writing, compared to the SSI method writing, electrons are likely to be injected relatively uniformly into the silicon nitride film 106b. However, even in the FN mode writing, the electric field is concentrated in the corner portion MG101a of the memory gate electrode MG101 in the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101). As a result, electrons tend to be injected at a higher density in a region closer to the control gate electrode CG (that is, closer to the drain region) than in the region on the source region side.

  Therefore, in both of the SSI method writing and the FN method writing, the control gate electrode CG in the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101). There is a tendency that electrons are injected at a high density into a region close to (that is, a side close to the drain region).

  On the other hand, in the BTBT erase, holes are not uniformly injected into the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101). Due to the generation location, electrons tend to be injected at a higher density in the region closer to the source region than in the region closer to the control gate electrode CG (that is, closer to the drain region).

  In the FN mode erasure, the silicon nitride film 106b in the insulating film 105 between the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101) is caused by electric field concentration at the corner MG101a of the memory gate electrode MG101. As a result, holes tend to be injected at a higher density in a region closer to the control gate electrode CG (that is, closer to the drain region) than the region on the source region side.

  Therefore, the silicon nitride film in the insulating film 105 is used when the writing is the SSI method and the erasing is the BTBT method (operation method A) and when the writing is the FN method and the erasing is the BTBT method (operation method C). In 106b, the position where electrons are likely to be injected at the time of writing and the position where holes are easily injected at the time of erasure are misaligned, so that unerased charges remain after the erasing operation. That is, electrons are injected at a higher density in the silicon nitride film 106b in the region 122 surrounded by the dotted line in FIG. 34 than in other regions when writing in the SSI method or FN method, but when erasing in the BTBT method, Since holes are not easily injected into the silicon nitride film 106b in the region 122, after erasing, the unerased electrons are likely to remain in the silicon nitride film 106b in the region 122. If there are unerased electrons in the silicon nitride film 106b, the threshold voltage of the memory transistor may fluctuate due to the unerased electrons, which degrades the performance of a semiconductor device including a nonvolatile memory. There is a risk of inviting.

  The silicon nitride film 106b in the insulating film 105 is used when the writing is the SSI method and the erasing is the FN method (operation method B) and when the writing is the FN method and the erasing is the FN method (operation method D). In FIG. 2, the position where electrons are easily injected at the time of writing and the position where holes are easily injected at the time of erasure substantially coincide with each other. That is, electrons are injected at a higher density in the silicon nitride film 106b in the region 122 surrounded by the dotted line in FIG. 34 than in other regions when writing with the SSI method or the FN method. Since holes are likely to be injected into the silicon nitride film 106b in the region 122, it is difficult for erasure remaining electrons to remain in the silicon nitride film 106b in the region 122 after erasing. Therefore, the threshold voltage of the memory transistor is unlikely to vary due to the unerased charge in the silicon nitride film 106b. However, in the operation method B and the operation method D, the corner portion MG101a of the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well) are caused by electric field concentration at the corner portion MG101a of the memory gate electrode MG101. A large amount of charge is injected into the silicon nitride film 106b (substantially corresponding to the silicon nitride film 106b in the region 122) in the insulating film 105 with the PW101). For this reason, the insulating film 105 (corresponding to the insulating film 105 in the region 122) between the corner portion MG101a of the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101) is deteriorated, and the reliability of the insulating film 105 is improved. There is a possibility that the performance of a semiconductor device including a nonvolatile memory may be degraded.

  Thus, the semiconductor device of the comparative example has the first problem and the second problem.

  On the other hand, in the present embodiment, the insulating film 5 includes a region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and a region between the memory gate electrode MG1 and the control gate electrode CG1. Although extending over both regions, the structure (structure) of the insulating film 5 is different in both regions.

  That is, in the present embodiment, a portion (first portion, gate insulating film portion) 5c between the lower surface 24 of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1) in the insulating film 5 is A silicon oxide film 6a, a silicon oxide film 6c, and a silicon nitride film 6b sandwiched between the silicon oxide films 6a and 6c. Of the insulating film 5, a portion (second portion, insulating portion) 5d between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG is composed of the silicon oxide film 6a and the silicon oxide film 6c. The cavity CAV is sandwiched between the silicon oxide films 6a and 6c, and the silicon nitride film 6b is not included.

  Here, the insulating film 5 is virtually divided into a gate insulating film portion 5c, an insulating portion 5d, and a corner portion 5e. FIG. 35 is an explanatory diagram of the semiconductor device of the present embodiment, and schematically shows which part of the insulating film 5 the gate insulating film part 5c, the insulating part 5d, and the corner part 5e indicate. FIG. 35 shows the same cross-sectional area as FIG. 2, and in FIG. 35, the insulating film 5 is virtually divided into a gate insulating film portion 5c, an insulating portion 5d, and a corner portion 5e. Actually, the insulating film 5 has a cross-sectional structure as shown in FIG. 2, and the insulating film 5 is formed of silicon oxide films 6a and 6c, a silicon nitride film 6b, and a cavity CAV.

  Of the insulating film 5, a portion 5c between the lower surface 24 of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1) is referred to as a “gate insulating film portion 5c”. In the insulating film 5, a portion 5d between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG is referred to as an “insulating portion 5d”. Of the insulating film 5, the gate insulating film portion 5c (that is, the portion 5c between the lower surface 24 of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1)) and the insulating portion 5d (that is, the control gate electrode). A portion (third portion) 5e between the side surface 26 of the CG and the portion 5d between the side surface 25 of the memory gate electrode MG is referred to as a “corner portion 5e”. A corner portion 5e is interposed between the gate insulating film portion 5c and the insulating portion 5d. The side surface 26 of the control gate electrode CG is a side surface facing the memory gate electrode MG through the insulating film 5, and the side surface 25 of the memory gate electrode MG is connected to the control gate electrode CG through the insulating film 5. It is a side surface on the opposite side. The lower surface 24 of the memory gate electrode MG is a surface in contact with the gate insulating film portion 5c.

  Since the gate insulating film portion 5c is located between the lower surface 24 of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1), it can function as a gate insulating film of the memory transistor. The silicon nitride film 6b in the gate insulating film portion 5c can function as a charge storage portion (charge storage layer) of the memory cell.

  Since the insulating portion 5d is located between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG, the insulating portion 5d can function to insulate and separate the control gate electrode CG and the memory gate electrode MG. .

  The corner portion 5e has a cross section (corresponding to the cross section of FIGS. 1 and 2) located at a corner portion of the L-shaped insulating film 5. For this reason, the gate insulating film portion 5c and the corner portion 5e extend along the main surface of the semiconductor substrate 1 (that is, substantially parallel to the main surface of the semiconductor substrate 1). The portion 5e extends in the up-down direction (that is, the direction substantially perpendicular to the main surface of the semiconductor substrate 1), and in the insulating film 5, from the horizontal direction (direction parallel to the main surface of the semiconductor substrate 1) in the up-down direction. A corner portion bent in a direction (substantially perpendicular to the main surface of the semiconductor substrate 1) corresponds to the corner portion 5e.

  In the insulating film 5, the gate insulating film portion 5c is located immediately below the memory gate electrode MG, but the insulating portion 5d and the corner portion 5e are not located immediately below the memory gate electrode MG. As can be seen from FIG. 35, the boundary between the insulating portion 5d and the corner portion 5e coincides with the extended surface of the lower surface 24 of the memory gate electrode MG in the vicinity of the corner portion 5e, and the gate insulating film portion 5c and the corner portion 5e are separated from each other. The boundary coincides with the extended surface of the side surface 25 of the memory gate electrode MG in the vicinity of the corner portion 5e.

  In the present embodiment, of the insulating film 5, the gate insulating film portion 5c located between the lower surface 24 of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1) is formed of silicon oxide films 6a and 6c. By having the silicon nitride film 6b sandwiched between the layers, charges can be accumulated in the silicon nitride film 6b, whereby information can be stored in the memory transistor.

  In the present embodiment, among the insulating film 5, the insulating portion 5d located between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG is formed of the silicon oxide films 6a and 6c and the silicon oxide film. By having the cavity CAV sandwiched between 6a and 6c and not having the silicon nitride film 6b, the breakdown voltage (insulation breakdown voltage) between the memory gate electrode MG and the control gate electrode CG can be improved. . That is, the insulating portion 5d located between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG does not have the insulating film 6b, and instead has a cavity CAV. Compared to the semiconductor device of the example, the breakdown voltage between the memory gate electrode MG and the control gate electrode CG can be improved. That is, the first problem can be solved or improved.

  Specifically, as described with reference to the semiconductor device of the comparative example, when the thickness of the insulating film 105 between the memory gate electrode MG101 and the control gate electrode CG101 is increased, the nonvolatile memory A decrease in read current (a current value flowing between the source and drain during reading) or a decrease in writing speed may be caused, and the performance of a semiconductor device having a nonvolatile memory may be deteriorated. On the other hand, in the present embodiment, even if the thickness of the insulating portion 5d between the memory gate electrode MG and the control gate electrode CG is not increased, the presence of the cavity CAV causes the memory gate electrode MG and the control gate electrode CG to be separated. Therefore, the breakdown voltage between the memory gate electrode MG and the control gate electrode CG is improved, and the insulating film 5 between the memory gate electrode MG and the control gate electrode CG (that is, the insulating portion 5d). ) Can be achieved at the same time. In the present embodiment, since the thickness of the insulating film 5 (that is, the insulating portion 5d) between the memory gate electrode MG and the control gate electrode CG can be suppressed, the distance L1 between the memory gate electrode MG and the control gate electrode CG. , The dimension in the gate length direction of the region corresponding to the region 121 can be reduced, the read current of the memory cell of the nonvolatile memory can be increased, and the writing speed can be improved. Therefore, the performance of a semiconductor device having a nonvolatile memory can be improved. Note that the distance L1 is shown in FIG. 2, and the thickness of the insulating portion 5d corresponds to the distance L1. In addition, the region corresponding to the region 121 is located below the insulating portion 5d and the corner portion 5e, and the substrate is difficult to form an electric field by the memory gate electrode MG or the control gate electrode CG and the channel region is not easily formed. Corresponds to the region.

  In the present embodiment, the upper part of the cavity CAV is closed (covered) by the insulating film portion 10a sandwiched between the silicon oxide film 6a and the silicon oxide film 6c. The insulating film portion 10a is preferably made of silicon oxide and is formed by a part of the insulating film 10 for forming the side wall spacer SW2. Since the upper part of the cavity CAV is closed by the insulating film portion 10a sandwiched between the silicon oxide films 6a and 6c, it is unnecessary in the cavity CAV during and after the manufacture of the semiconductor device. The material can be prevented from entering, and the cavity CAV can be accurately formed and maintained.

  Further, in the present embodiment, when the insulating film 5 is formed (specifically, step 7 above), the insulating film 5 is formed as a stacked film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c. Then, since the cavity CAV is formed by etching the silicon nitride film 6b thereafter (specifically, in step S14), the cavity CAV can be formed easily and accurately. Therefore, since the cavity CAV is a region where the silicon nitride film 6b is removed, in the manufactured semiconductor device, the end 23 of the silicon nitride film 6b is adjacent to the cavity CAV.

  In the present embodiment, a portion 5d (that is, the insulating portion 5d) between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG in the insulating film 5 has the silicon nitride film 6b. The lack of it is also one of the main characteristics.

  36 to 40 are explanatory views (main part sectional view, partially enlarged sectional view) for explaining the formation region of the cavity CAV and the silicon nitride film 6b in the insulating film 5, and a part of FIG. 2 is enlarged. It corresponds to what you did.

  36 to 40, the end portion 23 of the silicon nitride film 6b is adjacent to (the end portion of) the cavity CAV, and the end portion 6b of the silicon nitride film 6b covers a part of the inner wall of the cavity CAV. Forming. The position of the end portion 23 of the silicon nitride film 6b adjacent to the cavity CAV is different in each of FIGS.

  In the case of FIG. 36, the end 23 of the silicon nitride film 6b is located in the insulating portion 5d. For this reason, in the case of FIG. 36, both the cavity CAV and the silicon nitride film 6b exist in the insulating portion 5d.

  As in the case of FIG. 36, when the silicon nitride film 6b extends also into the insulating portion 5d between the side surface of the control gate electrode CG and the side surface of the memory gate electrode MG, the silicon nitride film 6b is The insulation part 5d in the existing part has a lower breakdown voltage between the control gate electrode CG and the memory gate electrode MG than the insulation part 5d in the part where the cavity CAV exists.

  Therefore, in the present embodiment, in the insulating film 5, the silicon nitride film 6b is prevented from extending in the insulating portion 5d between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG. It is preferable that FIGS. 37 to 40 satisfy this condition. 37 to 40, the silicon nitride film 6b does not extend in the insulating portion 5d between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG, and instead, the cavity CAV extends. Therefore, the breakdown voltage between the control gate electrode CG and the memory gate electrode MG can be improved accurately.

  37 to 40, the silicon nitride film 6b does not extend in the insulating portion 5d between the side surface 26 of the control gate electrode CG and the side surface 25 of the memory gate electrode MG. Instead, the cavity CAV extends in common, and is substantially the same in terms of the breakdown voltage improvement effect between the control gate electrode CG and the memory gate electrode MG due to the provision of the cavity CAV. However, in order to solve or improve the second problem, the position of the end 23 of the silicon nitride film 6b is important.

  In the case of FIG. 37, the end 23 of the silicon nitride film 6b is located at the same height as the lower surface 24 of the memory gate electrode MG. That is, the end 23 of the silicon nitride film 6b is located at the boundary between the insulating portion 5d and the corner portion 5e. Therefore, in the case of FIG. 37, the gate insulating film portion 5c and the corner portion 5e of the insulating film 5 have a laminated structure in which the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are laminated. is doing.

  In the case of FIG. 37, the effect which can solve or improve the said 1st subject as mentioned above is acquired, The effect is substantially equivalent to the case of FIGS. 38-40. However, in the case of FIGS. 38 to 40, it is possible to further obtain an effect capable of solving or improving the second problem.

  In the case of FIG. 38, the silicon nitride film 6b extends to the corner portion 5e of the insulating film 5, but the length of the silicon nitride film 6b extending to the corner portion 5e of the insulating film 5 is as shown in FIG. It is shorter than the case of FIG. In the case of FIGS. 39 and 40, the silicon nitride film 6 b does not extend at the corner portion 5 e of the insulating film 5.

  In order to solve or improve the second problem, it is effective to reduce the silicon nitride film 6b present at the corner portion 5e of the insulating film 5, and the silicon nitride film 6b is formed at the corner portion 5e of the insulating film 5. More preferably, it does not exist. The reason is as follows.

  In the semiconductor device of the comparative example of FIGS. 33 and 34, as described in relation to the second problem, in the case of the operation method A and the operation method C, the silicon nitride film 106b in the insulating film 105 is used. , The position where electrons are likely to be injected at the time of writing and the position where holes are likely to be injected at the time of erasing are misaligned, so that unerased charges are generated after the erasing operation, and the memory is caused by the unerased electrons. There is a risk that the threshold voltage of the transistor may fluctuate. This is because electrons are injected into the silicon nitride film 106b in the region 122 surrounded by the dotted line in FIG. 34 at a higher density than other regions at the time of writing, and into the silicon nitride film 106b in the region 122 at the time of erasing. This is because holes are hard to be injected, so that after erasing, the remaining electrons are easily left in the silicon nitride film 106b in the region 122.

  The insulating film 105 in the region 122 corresponds to the corner portion 5e of the insulating film 5 in this embodiment. For this reason, when the silicon nitride film 6b is present at the corner portion 5e of the insulating film 5, unerased charges after the erasing operation are likely to occur in the silicon nitride film 6b, resulting in the threshold voltage of the memory transistor. Variations can occur. Therefore, in the present embodiment, the silicon nitride film 6b existing in the corner portion 5e of the insulating film 5 is reduced as compared with the semiconductor device of the comparative example shown in FIGS. The silicon nitride film 6b does not exist in the corner portion 5e.

  If the silicon nitride film 6b existing in the corner portion 5e of the insulating film 5 is reduced as compared with the semiconductor device of the comparative example shown in FIGS. 33 and 34, the silicon nitride film 6b existing in the corner portion 5e is injected at the time of writing. Since the amount of electrons to be reduced can be reduced, it is possible to suppress the remaining unerased electrons from remaining in the silicon nitride film 6b of the corner portion 5e after erasure.

  Then, if the silicon nitride film 6b does not exist in the corner portion 5e of the insulating film 5, at the time of writing, since the silicon nitride film 6b does not exist in the corner portion 5e, electrons are not injected, and the gate insulating film portion 5c is nitrided. Electrons are injected only into the silicon film 6b. During the erasing operation, holes are easily injected into the silicon nitride film 6b of the gate insulating film portion 5c, and the silicon nitride film 6b is not present in the corner portion 5e where it is difficult for holes to be injected. It is possible to more accurately suppress the remaining erased electrons from remaining in the silicon film 6b).

  That is, in the present embodiment, the erase operation is performed by reducing or eliminating the silicon nitride film 6b that traps charges in the corner portion 5e at a position where electrons are easily injected at the time of writing but holes are not easily injected at the time of erasing. It is possible to suppress or prevent the remaining charges from being erased later. For this reason, it is possible to suppress or prevent fluctuations in the threshold voltage of the memory transistor due to unerased charges. Therefore, the performance of a semiconductor device including a nonvolatile memory can be improved.

  In the semiconductor device of the comparative example of FIG. 33 and FIG. 34, as described in relation to the second problem, in the case of the operation method B and the operation method D, the corner portion of the memory gate electrode MG101. Due to the electric field concentration in the MG 101a, the silicon nitride film 106b in the insulating film 105 between the corner MG101a of the memory gate electrode MG101 and the semiconductor substrate 101 (corresponding to the silicon nitride film 106b in the region 122) is large. Charge is injected into the. For this reason, the insulating film 105 (corresponding to the insulating film 105 in the region 122) between the corner portion MG101a of the memory gate electrode MG101 and the semiconductor substrate 101 (p-type well PW101) is deteriorated, and the reliability of the insulating film 105 is improved. May decrease. The region where the insulating film 105 is likely to deteriorate corresponds to the corner portion 5e of the insulating film 5 in the present embodiment. For this reason, if the silicon nitride film 6b exists in the corner portion 5e of the insulating film 5, a large amount of charge is injected into the silicon nitride film 6b, the corner portion 5e deteriorates and the reliability of the insulating film 5 decreases. there's a possibility that. Therefore, in the present embodiment, the silicon nitride film 6b existing in the corner portion 5e of the insulating film 5 is reduced as compared with the semiconductor device of the comparative example shown in FIGS. The silicon nitride film 6b does not exist in the corner portion 5e.

  If the silicon nitride film 6b present in the corner portion 5e of the insulating film 5 is reduced as compared with the semiconductor device of the comparative example of FIGS. 33 and 34, the silicon nitride film 6b present in the corner portion 5e is implanted. Since the amount of charge can be reduced, it is possible to suppress the deterioration of the corner portion 5e of the insulating film 5.

  If the silicon nitride film 6b does not exist in the corner portion 5e of the insulating film 5, no charge is injected into the corner portion 5e of the insulating film 5 because the silicon nitride film 6b does not exist, and the corner portion 5e of the insulating film 5 is not injected. Can be more accurately suppressed.

  That is, in the present embodiment, the corner portion 5e of the insulating film 5 is deteriorated by reducing or eliminating the silicon nitride film 6b that traps the charge in the corner portion 5e at a position where a large amount of charge is easily injected. Can be suppressed or prevented. For this reason, since it can suppress or prevent that the insulating film 5 deteriorates, the reliability of the insulating film 5 can be improved. Therefore, the performance of a semiconductor device including a nonvolatile memory can be improved.

  When the end 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG, the silicon nitride film 6b does not exist at the corner portion 5e of the insulating film 5. 39 and 40, the end portion 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG, and the silicon nitride film 6b is present at the corner portion 5e of the insulating film 5. Absent. With such a configuration, when the operation method of the nonvolatile memory is either the operation method A or the operation method C, as described above, the charge remaining after erasing can be suppressed, and the charge remaining unerased. It is possible to suppress or prevent fluctuations in the threshold voltage of the memory transistor due to the above. Further, when the operation method of the nonvolatile memory is either the operation method B or the operation method D, as described above, the deterioration of the insulating film 5 can be suppressed or prevented, and the reliability of the insulating film 5 is improved. Can do. Therefore, the performance of the semiconductor device including the nonvolatile memory can be improved regardless of whether the operation method of the nonvolatile memory is any of the operation method A, the operation method B, the operation method C, or the operation method D.

  When the end portion 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG (corresponding to FIG. 39 or FIG. 40), the corner portion 5e of the insulating film 5 has the silicon nitride film 6b. In other words, the cavity CAV extends to the corner portion 5e.

  The case where the end 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG is classified into the case of FIG. 39 and the case of FIG.

  In the case of FIG. 39, the end portion 23 of the silicon nitride film 6b is located immediately below the side surface 25 of the memory gate electrode MG, and the gate insulating film portion 5c (more specifically, the entire gate insulating film portion 5c) is The silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are stacked.

  In the case of FIG. 40, the end portion 23 of the silicon nitride film 6b is located farther (away from) the control gate electrode CG (that is, closer to the source region) than the position directly below the side surface 25 of the memory gate electrode MG. is doing. Therefore, in the case of FIG. 40, the gate insulating film portion 5c includes a portion (fourth portion) 5f in which the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are stacked, and the silicon oxide film 6a. A portion (fifth portion) 5g including the cavity CAV and the silicon oxide film 6c and not including the silicon nitride film 6b is provided, and the portion 5g is located between the portion 5f and the corner portion 5e. . More specifically, the gate insulating film portion 5c includes a portion 5f in which a silicon oxide film 6a, a silicon nitride film 6b, and a silicon oxide film 6c are stacked, and a portion 5g having a cavity CAV instead of the silicon nitride film 6b. The portion 5g is adjacent to the corner portion 5e, and the end 23 of the silicon nitride film 6b is located at the boundary between the portion 5f and the portion 5g.

  39 and 40, the end 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG, and the corner portion 5e of the insulating film 5 has the silicon nitride film 6b. Therefore, the effect of suppressing or preventing the threshold voltage fluctuation of the memory transistor described above (in the case of the operation method A or the operation method C) or the effect of improving the reliability of the insulating film 5 described above (operation method B or In the case of the operation method D). However, in the case of FIG. 40, the following effects can be further obtained.

  That is, although the cavity CAV is formed by etching the silicon nitride film 6b in step S14, the position of the end portion 23 of the silicon nitride film 6b may slightly vary due to variations in etching conditions. . Therefore, as in the case of FIG. 40, the end 23 of the silicon nitride film 6b can be set farther (away from) the control gate electrode CG than the position directly below the side surface 25 of the memory gate electrode MG. For example, even if the position of the end portion 23 of the silicon nitride film 6b is slightly changed, the end portion 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG, and the corner portion 5e of the insulating film 5 is the silicon nitride film 6b. The state which does not have can be maintained. As a result, even if a process variation occurs (specifically, the process variation in step S14), the corner portion 5e of the insulating film 5 can be maintained in a state in which the silicon nitride film 6b is not provided. The effect of suppressing or preventing the fluctuation of the threshold voltage (in the case of operation method A or operation method C), or the effect of improving the reliability of the insulating film 5 described above (operation method B or operation) The case of method D) can be obtained more accurately. Therefore, the performance of the semiconductor device including the nonvolatile memory can be improved more accurately.

  On the other hand, in the case of FIG. 39 (also in the case of FIGS. 37 and 38), the entire gate insulating film portion 5c has a laminated structure in which a silicon oxide film 6a, a silicon nitride film 6b, and a silicon oxide film 6c are laminated. Therefore, it is advantageous in improving the writing speed.

  In order to solve or improve the second problem, it is extremely effective to prevent the silicon nitride film 6b from being present at the corner portion 5e of the insulating film 5, but the corner portion 5e of the insulating film 5 Even if the silicon nitride film 6b exists, if the silicon nitride film 6b in the corner portion 5e of the insulating film 5 is reduced as compared with the comparative example of FIGS. 33 and 34, the silicon nitride film 6b shown in FIGS. Compared to the comparative example, the second problem can be improved. An example in this case corresponds to FIG.

  That is, in the case of FIG. 38, the end portion 23 of the silicon nitride film 6b is lower than the lower surface 24 of the memory gate electrode MG and is lower than the position directly below the side surface 25 of the memory gate electrode MG. Located on the side close to In this case, the end portion 23 of the silicon nitride film 6b is located in the corner portion 5e, and the gate insulating film portion 5c (the entire gate insulating film portion 5c) includes the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide. It has a laminated structure in which the film 6c is laminated. With such a structure, the silicon nitride film 6b at the corner portion 5e of the insulating film 5 is reduced as compared with the comparative example of FIGS. 33 and 34. Therefore, the comparative example of FIGS. Compared to the case, the second problem can be improved. That is, as compared with the comparative example of FIG. 33 and FIG. 34 described above, an effect (operation method A) in which fluctuations in the threshold voltage of the memory transistor can be suppressed by suppressing unerased charges after erasure. Or in the case of the operation method C), or an effect (in the case of the operation method B or the operation method D) that can improve the reliability of the insulating film 5 by suppressing the deterioration of the insulating film 5 (corner portion 5e). be able to. Therefore, the performance of a semiconductor device including a nonvolatile memory can be improved.

  The position of the end 23 of the silicon nitride film 6b can be controlled by adjusting the etching conditions (for example, the etching time) in the etching process of step S14. For example, in order to obtain the structure of FIG. 39 or FIG. 40 (a structure in which the end portion 23 of the silicon nitride film 6b is located immediately below the memory gate electrode MG), it is adjacent to the cavity CAV in the etching process of step S14. The silicon nitride film 6b may be etched until the end 23 of the silicon nitride film 5 to be positioned is located immediately below the memory gate electrode MG. Further, in the etching process of step S14, the silicon nitride is continued until the end portion 23 of the silicon nitride film 6b adjacent to the cavity CAV is at the same height as the lower surface 24 of the memory gate electrode MG or at a lower position. If the film 6b is etched, one of the structures shown in FIGS. 36 to 40 can be obtained. However, if all of the silicon nitride film 6b is removed from the gate insulating film portion 5c, the charge storage portion does not exist. Therefore, in the etching process of step S14, all of the silicon nitride film 6b is removed from the gate insulating film portion 5c. The etching is finished before the removal, and at least a part of the silicon nitride film 6b is present (remains) in the gate insulating film portion 5c after the etching process of step S14. In the case of the structure of FIG. 40, in the gate insulating film portion 5c, the gate length direction (gate length direction of the memory gate electrode MG) of the portion 5f in which the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are stacked. The dimension is more preferably 10 nm or more, and thereby, the function as the charge storage unit can be more accurately exhibited.

(Embodiment 2)
This embodiment corresponds to a modification of the first embodiment.

  In the present embodiment, a case where the height of the memory gate electrode MG of the nonvolatile memory of the first embodiment is formed to be higher than the height of the control gate electrode CG will be described.

  41 and 42 are fragmentary cross-sectional views of the semiconductor device of the present embodiment. FIG. 41 corresponds to FIG. 1 of the first embodiment and shows a cross-sectional view of the main part of the memory cell region of the nonvolatile memory. FIG. 42 corresponds to FIG. 2 of the first embodiment, and a part of FIG. 41 is enlarged. 42, for easy understanding, in the structure of FIG. 1, the control gate electrode CG, the memory gate electrode MG, the insulating films 3 and 5, the side wall insulating film SW2, and the substrate region immediately below them ( Only a part of the semiconductor substrate 1 constituting the p-type well PW1 is illustrated.

  As shown in FIGS. 41 and 42, the memory cell of the nonvolatile memory in the present embodiment is formed such that the height of the control gate electrode CG is lower than the height of the memory gate electrode MG. A more specific configuration will be described below.

  The control gate electrode CG and the memory gate electrode MG extend along the main surface of the semiconductor substrate 1 and are arranged side by side with the insulating film 5 interposed between the opposing side surfaces (side walls). The control gate electrode CG and the memory gate electrode MG are adjacent to each other with the insulating film 5 interposed therebetween, and the memory gate electrode MG is disposed on the side wall of the control gate electrode CG via the insulating film 5 via the sidewall spacer. It is formed in a shape. However, as described above, the height of the memory gate electrode MG is formed higher than the height of the control gate electrode CG. That is, the height of the memory gate electrode MG (the height in the direction substantially perpendicular to the main surface of the semiconductor substrate 1) is higher than the height of the control gate electrode CG (the height in the direction substantially perpendicular to the main surface of the semiconductor substrate 1). ) Is higher.

  The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. . As in the case of the first embodiment, in the present embodiment, a portion of the insulating film 5 located between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) is formed on the silicon oxide films 6a and 6c. The silicon nitride film 6b is sandwiched, and this silicon nitride film 6b functions as a charge storage portion, while the insulating film 5 located between the memory gate electrode MG and the control gate electrode CG has a cavity CAV. I am doing so. That is, a portion of the insulating film 5 between the lower surface of the memory gate electrode MG and the upper surface of the semiconductor substrate 1 (p-type well PW1) is sandwiched between the silicon oxide films 6a and 6c and the silicon oxide films 6a and 6c. A portion of the insulating film 5 between the side surface of the control gate electrode CG and the side surface of the memory gate electrode MG is sandwiched between the silicon oxide films 6a and 6c and the silicon oxide films 6a and 6c. The cavity CAV is included and the silicon nitride film 6b is not included.

  The upper part of the cavity CAV is in a state (covered state) closed by an insulating film part (insulator part) 10a sandwiched between the silicon oxide film 6a and the silicon oxide film 6c. The insulating film portion 10a is formed by a part of an insulating film (corresponding to an insulating film 10 to be described later) for forming the sidewall spacer SW2, and is an insulator (of the same kind as at least a part of the sidewall spacer SW2). Insulator material), preferably silicon oxide. Therefore, the cavity CAV is surrounded by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a. The inner wall of the cavity CAV is surrounded by the silicon oxide films 6a and 6c, the silicon nitride film 6b, and the insulating film portion 10a. Is formed. However, in the present embodiment, as shown in FIG. 42, not only the cavity CAV is blocked by the insulating film portion 10a sandwiched between the silicon oxide film 6a and the silicon oxide film 6c, but also the control gate electrode Since the height of the CG is formed to be lower than the height of the memory gate electrode MG, the sidewall spacer SW2 is formed on the control gate electrode CG and also on the side wall of the memory gate electrode MG on the drain region side. Has been. Note that the side wall spacer SW2 formed above the control gate electrode CG and on the side wall on the drain region side of the memory gate electrode MG is referred to as a side wall spacer SW2a.

  In the present embodiment, the insulating film portion 10a is formed integrally with the sidewall spacer SW2a. That is, a part of the insulating film constituting the sidewall spacer SW2a penetrates between the control gate electrode CG and the memory gate electrode MG to form the insulating film portion 10a.

  In the present embodiment, as will be described later, the control gate electrode CG is first composed of a laminated film (laminated pattern, laminated structure) of the silicon film 4n and the insulating film 31, and a part of the insulating film 31 is removed. In this embodiment, the sidewall insulating film SW1 is also removed. However, although the sidewall insulating film SW1 may remain, the sidewall insulating film SW1 may remain.

  In the present embodiment, since the sidewall spacer SW2a is also formed on the control gate electrode CG, a portion of the control gate electrode CG on which the sidewall spacer SW2a is formed has a metal silicide. The layer 13 is not formed, and the metal silicide layer 13 is formed in a portion where the sidewall spacer SW2a is not formed. That is, the metal silicide layer 13 is not formed in the region covered with the sidewall spacer SW2a on the upper surface of the control gate electrode CG, and is not covered with the sidewall spacer SW2a on the upper surface of the control gate electrode CG. A metal silicide layer 13 is formed in the region. Therefore, a distance corresponding to the side wall spacer SW2a is secured between the metal silicide layer 13 formed on the control gate electrode CG and the metal silicide layer 13 formed on the memory gate electrode MG. Short circuit between the metal silicide layers 13 (that is, the metal silicide layer 13 on the control gate electrode CG and the metal silicide layer 13 on the memory gate electrode MG) can be effectively avoided. Therefore, the reliability of the semiconductor device can be further improved.

  Since the other configuration of the memory cell of this embodiment is the same as that of Embodiment 1, the description thereof is omitted here.

Next, the manufacturing process of the semiconductor device of this embodiment will be described. 43 to 49 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. 43 to 46, FIG. 43 to FIG. 46, FIG. 48, and FIG. 49 show substantially the same cross-sectional area as FIG. 6 to FIG. 15 in the first embodiment. 47 is a partially enlarged cross-sectional view of FIG. 46, in which a part of the memory cell region 1A in FIG. 46 is enlarged (in FIG. 47, the n ⁻ type semiconductor regions 9a and 9b are not shown). It is omitted and included in the p-type well PW1). Note that FIG. 45 shows the steps performed up to step S13 (the same process steps as in FIG. 20). 46 and 47 are cross-sectional views at the stage after performing step S14 (before performing step S15). FIG. 48 shows the stage where the above step S15 is performed (the same process stage as in FIG. 23), and FIG. 49 shows the stage where the above step S16 is performed (the same process stage as in FIG. 25). Yes.

  Since the manufacturing process of the semiconductor device according to the present embodiment is basically the same as the manufacturing process of the semiconductor device according to the first embodiment, differences from the manufacturing process according to the first embodiment will be mainly described below. explain.

  After obtaining the structure shown in FIG. 8 in the same manner as in the first embodiment, in this embodiment, the silicon film 4 (4n) is interposed between the step S5 and the step S6 as shown in FIG. ) A step of forming the insulating film 31 thereon is added. The insulating film 31 is composed of a laminated film (laminated film pattern) of an insulating film 31a on the silicon film 4n (4) and an insulating film 31b on the insulating film 31a. The insulating film 31a is thinner than the insulating film 31b. Is formed. The insulating film 31a is preferably made of a silicon oxide film, and the insulating film 31b is preferably made of a silicon nitride film. In this embodiment, the insulating film 31a is a silicon oxide film, and the insulating film 31b is a silicon nitride film. This will be described as a case where it is formed. The insulating film 31 forming step includes a step of forming the insulating film 31a on the silicon film 4 (4n) and a step of forming the insulating film 31b on the insulating film 31a.

  In step S6, the control gate electrode CG is formed by patterning the silicon film 4n in the first embodiment. However, in the present embodiment, the stacked film of the silicon film 4n and the insulating film 31 is patterned. Thus, as shown in FIG. 44, a control gate electrode CG having a laminated film pattern of the silicon film 4n and the insulating film 31 is formed. Then, between steps S6 and S7, the insulating film 31 is appropriately removed in a region where the insulating film 31 is to be removed (for example, the peripheral circuit region 1B).

  Thereafter, steps S7 to S14 are performed in the same manner as in the first embodiment. As can be seen from FIG. 45, until the stage of FIG. 45, the control gate electrode CG is formed by a laminated film of the silicon film 4n and the insulating film 31 on the silicon film 4n, and the silicon film 4n. A memory gate electrode MG is formed in the shape of a side wall spacer on the side wall of the control gate electrode CG made of a laminated film of the insulating film 31 and the insulating film 5. On the other hand, in step S14, as shown in FIGS. 46 and 47, the insulating film 31b is also etched and removed simultaneously by etching the silicon nitride film 6b. Further, the insulating film 31a is also removed by subsequent cleaning or the like. As described above, in this embodiment, the sidewall insulating film SW1 is also removed at that time (when the insulating film 31a is removed). 41, FIG. 42, and FIGS. 46 to 49 are described. Further, when the insulating film 31a and the side wall insulating film SW1 are removed, the silicon oxide films 6a and 6b located between the insulating film 31 and the memory gate electrode MG can also be removed.

  Further, since the insulating film 31b and the insulating film 31a are removed, as shown in FIGS. 46 to 49, the control gate electrode CG is not formed with the insulating films 31a and 31b on the upper portion, and the silicon film 4n. It will be in a state composed of. Since the memory gate electrode MG was formed at substantially the same height as the control gate electrode CG that was formed of the laminated film of the silicon film 4n and the insulating film 31, the insulating film 31 above the control gate electrode CG was removed. Thereafter, the height of the control gate electrode CG composed of the silicon film 4n is lower than the height of the memory gate electrode MG composed of the silicon film 7n.

  Thereafter, steps S15 to S17 are performed in the same manner as in the first embodiment. As can be seen from FIG. 48 and FIG. 49, in the present embodiment, in step S16, the side wall spacer SW2 is provided on the side wall opposite to the side adjacent to the control gate electrode CG and the memory gate electrode MG. In addition to the formation, a sidewall spacer SW2a is formed on the control gate electrode CG and on the sidewall of the memory gate electrode MG on the drain region side. This is because the height of the control gate electrode CG composed of the silicon film 4n is lower than the height of the memory gate electrode MG composed of the silicon film 7n.

  Since the subsequent steps are basically the same as those in the first embodiment, description thereof is omitted here.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained.

  In addition, in this embodiment, since the control gate electrode CG is first formed of a laminated film of the silicon film 4n and the insulating film 31 (more specifically, the insulating films 31a and 31b), the silicon film 4 ( Even when 4n) is formed thinner than that of the first embodiment, the height of the memory gate electrode MG formed in a sidewall spacer shape on the side wall of the control gate electrode CG can be ensured. Further, a distance corresponding to the side wall spacer SW2a is secured between the metal silicide layer 13 formed on the control gate electrode CG and the metal silicide layer 13 formed on the memory gate electrode MG. Short circuit between the metal silicide layers 13 (that is, the metal silicide layer 13 on the control gate electrode CG and the metal silicide layer 13 on the memory gate electrode MG) can be effectively avoided. Therefore, the reliability of the semiconductor device can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device and its manufacturing technology.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Memory cell area | region 1B Peripheral circuit area | region 2 Element isolation area | region 3 Insulating film 4, 4n Silicon film 5 Insulating film 5a Upper end part 5b End part 5c Gate insulating film part 5d Insulating part 5e Corner part 5f, 5g Part 6a, 6c Silicon oxide film 6b Silicon nitride film 7n Silicon film 8 Insulating films 9a, 9b, 9c n ⁻ type semiconductor region 10 Insulating film 10a Insulating film portions 11a, 11b, 11c n ⁺ type semiconductor regions 12 Metal film 13 Metal silicide layers 14, 15 , 16 Insulating film 23 End 24 Lower surface 25 Side surface 26 Side surface 31, 31a, 31b Insulating film 101 Semiconductor substrate 103 Insulating film 105 Insulating film 106a, 106c Silicon oxide film 106b Silicon nitride film 109a, 109b n ⁻ type semiconductor regions 111a, 111b n ⁺ -type semiconductor region 113 metal silicide layer 114, 115 absolute Film 121 region 122 region CAV cavity CG, CG101 control gate electrode CNT contact hole GE gate electrode L1, L2, L101 distance M1 wiring MC memory cell MD, MS semiconductor region MG, MG101 memory gate electrode MG101a corner PG plug SD semiconductor region SP1 Silicon spacer PW1, PW2, PW101 p-type well SW1 side wall insulating film SW2, SW2a, SW102 side wall spacer

Claims (22)

A semiconductor device including a memory cell of a nonvolatile memory,
A semiconductor substrate;
A first gate electrode forming the memory cell formed on the semiconductor substrate;
A second gate electrode formed on the semiconductor substrate, adjacent to the first gate electrode and constituting the memory cell;
A first gate insulating film formed between the first gate electrode and the semiconductor substrate;
An insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode;
Have
Of the insulating film, a first portion between the lower surface of the second gate electrode and the upper surface of the semiconductor substrate includes a first silicon oxide film, a second silicon oxide film, and the first and second silicon oxide films. And a silicon nitride film sandwiched between
The silicon nitride film functions as a charge storage portion of the memory cell,
Of the insulating film, a second portion between the side surface of the first gate electrode and the side surface of the second gate electrode includes the first silicon oxide film, the second silicon oxide film, the first and first A semiconductor device having a cavity sandwiched between silicon dioxide films and not having the silicon nitride film. The semiconductor device according to claim 1,
An upper portion of the cavity is closed by an insulating film portion sandwiched between the first silicon oxide film and the second silicon oxide film. The semiconductor device according to claim 2,
The semiconductor device, wherein the insulating film portion is made of silicon oxide. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the first end portion of the silicon nitride film is adjacent to the cavity. The semiconductor device according to claim 4.
The semiconductor device according to claim 1, wherein the first end portion of the silicon nitride film is located immediately below the second gate electrode. The semiconductor device according to claim 5.
Of the insulating film, a third portion between the first portion and the second portion does not have the silicon nitride film, and the cavity extends to the third portion. A semiconductor device characterized by that. The semiconductor device according to claim 6.
The first end portion of the silicon nitride film is located on a side farther from the first gate electrode than a position directly below the side surface of the second gate electrode,
The first portion includes a fourth portion in which the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are stacked, the first silicon oxide film, the cavity, and the second oxide. A fifth portion including a silicon film and not including the silicon nitride film,
The semiconductor device, wherein the fifth portion is located between the fourth portion and the third portion. The semiconductor device according to claim 6.
The first end of the silicon nitride film is located immediately below the side surface of the second gate electrode,
The semiconductor device according to claim 1, wherein the first portion has a stacked structure in which the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are stacked. The semiconductor device according to claim 4.
The first end of the silicon nitride film is at a position lower than the lower surface of the second gate electrode and closer to the first gate electrode than a position directly below the side surface of the second gate electrode. Position to,
The semiconductor device according to claim 1, wherein the first portion has a stacked structure in which the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are stacked. The semiconductor device according to claim 4.
The first end of the silicon nitride film is positioned at the same height as the lower surface of the second gate electrode;
Of the insulating film, a third part between the first part and the second part, and the first part include the first silicon oxide film, the silicon nitride film, and the second part. A semiconductor device having a stacked structure in which a silicon oxide film is stacked. The semiconductor device according to claim 1,
Writing the memory cell by injecting hot electrons into the silicon nitride film,
A semiconductor device, wherein the memory cell is erased by injecting hot holes into the silicon nitride film. The semiconductor device according to claim 1,
Writing the memory cell by injecting hot electrons into the silicon nitride film,
A semiconductor device, wherein the memory cell is erased by injecting holes into the silicon nitride film by an FN tunnel effect. The semiconductor device according to claim 1,
The memory cell is written by injecting electrons into the silicon nitride film by the FN tunnel effect,
A semiconductor device, wherein the memory cell is erased by injecting hot holes into the silicon nitride film. The semiconductor device according to claim 1,
The memory cell is written by injecting electrons into the silicon nitride film by the FN tunnel effect,
A semiconductor device, wherein the memory cell is erased by injecting holes into the silicon nitride film by an FN tunnel effect. A method of manufacturing a semiconductor device including a memory cell of a nonvolatile memory,
(A) preparing a semiconductor substrate;
(B) forming a first gate electrode constituting the memory cell on the main surface of the semiconductor substrate via a first gate insulating film;
(C) forming an insulating film made of a laminated film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film on the main surface of the semiconductor substrate and the side surface of the first gate electrode;
(D) forming a second gate electrode adjacent to the first gate electrode via the insulating film on the insulating film and constituting the memory cell;
(E) removing the portion of the insulating film not covered with the second gate electrode;
(F) After the step (e), forming a side wall insulating film on the side wall of the second gate electrode opposite to the side adjacent to the first gate electrode;
(G) After the step (f), a step of removing the silicon nitride film in a portion between the side surface of the first gate electrode and the side surface of the second gate electrode in the insulating film to form a cavity. ,
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 15,
In the step (g), the silicon nitride film is removed by wet etching. In the manufacturing method of the semiconductor device according to claim 16,
After the step (f), an end portion of the insulating film sandwiched between the second gate electrode and the semiconductor substrate is covered with the sidewall insulating film and is not exposed. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 17.
In the step (g), the etching of the silicon nitride film proceeds from the upper end side of the insulating film sandwiched between the upper part of the first gate electrode and the upper part of the second gate electrode. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 18.
After the step (g),
(H) forming a first insulating film on the semiconductor substrate so as to cover the first and second gate electrodes;
(I) After the step (h), the first insulating film is anisotropically etched to form a side wall spacer on the side wall opposite to the side adjacent to the first and second gate electrodes. Process,
Further comprising
A method of manufacturing a semiconductor device, wherein after the step (i), a part of the first insulating film remains above the cavity. In the manufacturing method of the semiconductor device according to claim 19,
The silicon nitride film that remains between the second gate electrode and the semiconductor substrate without being removed in the step (e) functions as a charge storage portion of the memory cell. Method. The method of manufacturing a semiconductor device according to claim 20,
In the step (g),
The silicon nitride film is etched until the end of the silicon nitride film adjacent to the cavity is at the same height as the lower surface of the second gate electrode or at a lower position. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 20,
In the step (g),
The method of manufacturing a semiconductor device, wherein the silicon nitride film is etched until an end portion of the silicon nitride film adjacent to the cavity is located immediately below the second gate electrode.

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