TW202032794A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device including a substrate of a first conductivity type, at least one gate structure combination, an inner doped region of a second conductivity type, two outer doped regions of the second conductivity type, and two lightly doped regions of the second conductivity type. Each of the gate structure combination including a first gate structure and a second gate structure. The gate structure combination is located on the substrate. The inner doped region is located in the substrate, and is sandwiched between the first gate structure and the second gate structure. The two outer doped regions are located in the substrate. The two outer doped regions are located in the substrate which outside the inner doped region, the first gate structure, and the second gate structure. The two lightly doped regions are located in the substrate. The lightly doped region covers a sidewall and a bottom surface of the outer doped region, and a sidewall and a bottom surface of the inner doped region are not covered by the lightly doped region.

Description

Semiconductor components

The present invention relates to an integrated circuit, and particularly relates to a semiconductor element.

With the trend of science and technology, it is desirable to manufacture semiconductor devices with lower device specific on-resistance (Ron-sp), and how to shorten the gate length to obtain lower device specific on-resistance will become an important issue.

The present invention provides a semiconductor element, which can effectively shorten the gate length of the semiconductor element while maintaining certain electrical characteristics.

The invention provides a semiconductor element including a substrate with a first conductivity type, at least one gate structure combination, an inner doped region with a second conductivity type, two outer doped regions with a second conductivity type, and a second conductivity type. Type of two lightly doped regions. Each gate structure combination includes a first gate structure and a second gate structure. The gate structure is assembled on the substrate. The inner doped region is located in the substrate and sandwiched between the first gate structure and the second gate structure. Two outer doped regions are located in the substrate. The two outer doped regions are located in the substrate outside the inner doped region, the first gate structure and the second gate structure. Two lightly doped regions are located in the substrate. The lightly doped region covers the sidewall and bottom surface of the outer doped region, and the sidewall and bottom surface of the inner doped region are not covered by the lightly doped region.

The invention provides a semiconductor element including a substrate with a first conductivity type, at least one gate structure combination, an inner doped region with a second conductivity type, two outer doped regions with a second conductivity type, and a second conductivity type. Type of lightly doped area. The two gate structures are arranged on the substrate. The inner doped region is located in the substrate. The inner doped region is sandwiched between the first gate structure and the second gate structure. Two outer doped regions are located in the substrate. The two outer doped regions are located in the substrate outside the inner doped region, the first gate structure and the second gate structure. The lightly doped region is located in the substrate. The lightly doped region covers the sidewall and bottom surface of the inner doped region, and the sidewall and bottom surface of the outer doped region are not covered by the lightly doped region.

Based on the above, the present invention uses a single semiconductor device with an inner doped region sandwiched between two gate structures, and two outer doped regions are located in the substrate outside the inner doped region and the two gate structures. The doped region covers the sidewall and bottom surface of the outer doped region, but does not cover the sidewall and bottom surface of the inner doped region, or the lightly doped region covers the sidewall and bottom surface of the inner doped region; The sidewall and bottom surface of the miscellaneous region prevent two adjacent inner doped regions and outer doped regions from being in contact with each other due to lateral diffusion of the two lightly doped regions, thereby causing breakdown leakage current, which can effectively shorten the semiconductor The gate length of the element while maintaining certain electrical characteristics.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A, this embodiment provides a method for manufacturing a semiconductor device 100, the steps of which are as follows. First, a substrate 102 having a first conductivity type is provided. The substrate 102 is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The substrate 102 may also be, for example, an epitaxial layer (EPI), a non-epitaxial layer (non-EPI), a silicon-on-insulator (SOI) substrate, or a combination thereof. In this embodiment, the first conductivity type is, for example, a P-type, and the substrate 102 is, for example, a P-type substrate. The P-type dopant is boron, for example.

In some embodiments, as shown in FIG. 1F, the substrate 102 may have four non-uniform doped regions PW1, PW2, PW3, and PW4 in sequence from the bottom surface 102b to the top surface 102a. In other embodiments, it may also It is a plurality of wells diffused by high temperature thermal annealing or rapid thermal annealing. The doped region PW1 is, for example, located at a position of 1 micrometer (μm) to 3 μm from the top surface 102a of the substrate 102; the doped region PW2 is, for example, located at a position of 0.5 μm to 2 μm from the top surface 102a of the substrate 102; PW3 is, for example, located at a position of 0.2 μm to 1 μm from the top surface 102 a of the substrate 102; and the doped region PW4 is, for example, located at a position of 0 μm to 0.6 μm from the top surface 102 a of the substrate 102. In some embodiments, the doping concentration range in the doped region PW1 is, for example, between 10 ¹⁶ /cm ³ to 10 ¹⁸ /cm ³ ; the doping concentration range in the doping region PW2 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; the doping concentration range in the doped region PW3 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; and the doping concentration in the doped region PW4 The range is, for example, between 10 ¹⁶ /cm ³ and 10 ¹⁸ /cm ³ , where the doped region PW4 has the greatest impact on the threshold voltage. In this embodiment, by doping different regions in the substrate 102 with different concentration ranges, the threshold voltage of the semiconductor device 100 (FIG. 1E) can be directly adjusted, so there is no need to use an additional process to control the threshold voltage. For example, the present invention does not need to form additional pocket implant regions to effectively control the threshold voltage. The pocket implant regions cover the first lightly doped regions 122 and the second lightly doped regions as shown in FIG. 1E. The dotted area at the corners of the lightly doped region 124 and the inner doped region 140.

Please continue to refer to FIG. 1A, and then, an isolation structure 104 is formed in the substrate 102 to define the active area AA. The material of the isolation structure 104 is, for example, doped or undoped silicon oxide, low-stress silicon nitride, silicon oxynitride, or a combination thereof. The formation method thereof can be, for example, local area thermal oxidation (LOCOS), shallow trench isolation, or Deep trench isolation method. In an embodiment, the isolation structure 104 may be, for example, a field oxide structure (FOX), a shallow trench isolation structure (STI), a deep trench isolation structure (DTI), or a combination thereof.

1B, after the isolation structure 104 is formed, a gate structure assembly 110 is formed on the substrate 102. The gate structure assembly 110 includes a first gate structure 112 and a second gate structure 114. The gate structure assembly 110 is not limited to a set of the first gate structure 112 and the second gate structure 114, but includes a plurality of sets of the first gate structure 112 and the second gate structure 114. In this embodiment, the first gate structure 112 and the second gate structure 114 may be the same type of gate structure. The first gate structure 112 includes, for example, a gate dielectric layer 12a and a conductor layer 12b sequentially stacked on the substrate 102; and the second gate structure 114 includes, for example, a gate dielectric layer sequentially stacked on the substrate 102. Layer 14a and conductor layer 14b. The material of the gate dielectric layers 12a, 14a may include silicon oxide, silicon oxynitride, silicon nitride, and combinations thereof. In addition, multilayer materials can also be used as the gate dielectric layers 12a, 14a. In this embodiment, the material of the conductive layers 12b, 14b is, for example, doped polysilicon. The dopant of the doped polysilicon may be of P type conductivity, such as boron. The dopant concentration range of the doped polysilicon is, for example, 10 ¹⁷ /cm ³ to 10 ¹⁹ /cm ³ .

The formation method of the gate dielectric layers 12a, 14a and the conductor layers 12b, 14b is, for example, chemical vapor deposition (CVD) or furnace tube oxidation. In some embodiments, the manufacturing steps of the first gate structure 112 and the second gate structure 114 may be as follows. First, a gate dielectric material layer and a conductive material layer are formed on the substrate 102, and then the material layer is patterned by a lithography and etching process.

In some embodiments, the gate length L1 of the first gate structure 112 is, for example, 0.1 μm to 1 μm; and the gate length L2 of the second gate structure 114 is, for example, 0.1 μm to 1 μm. The gate length L1 of the first gate structure 112 and the gate length L2 of the second gate structure 114 may be the same. In other embodiments, the gate length L1 of the first gate structure 112 and the gate length L2 of the second gate structure 114 may be different.

1B and FIG. 2A at the same time, after forming the first gate structure 112 and the second gate structure 114, a patterned photoresist layer 16 is formed on the substrate 102. The patterned photoresist layer 16 has two openings O1. The photoresist layer 16 covers the isolation structure 104, the first gate structure 112, the second gate structure 114, and a portion of the substrate 102 between the first gate structure 112 and the second gate structure 114. In other words, the opening O1 exposes a portion of the substrate 102 of the active area AA. In some embodiments, the opening O1 not only exposes a portion of the substrate 102 of the active area AA, but also exposes a portion of the isolation structure 104, the first gate structure 112, and the second gate structure 114, as shown in FIGS. 1B and 2A. Show.

Next, an ion implantation process is performed to form a lightly doped region 120 in a portion of the substrate 102 exposed by the opening O1. The lightly doped region 120 includes a first lightly doped region 122 and a second lightly doped region 124. In other embodiments, based on process requirements, other photoresist pattern designs or other doping steps may be used to perform multiple ion implantation processes to form the first lightly doped region 122 and the second lightly doped region 124 . Next, the patterned photoresist layer 16 is removed.

The first lightly doped region 122 is adjacent to the first gate structure 112, and the second lightly doped region 124 is adjacent to the second gate structure 114. The first lightly doped region 122 and the second lightly doped region 124 may be lightly doped regions having the second conductivity type. In other words, the first lightly doped region 122 and the second lightly doped region 124 have the same conductivity type doping. The second conductivity type is different from the first conductivity type. In this embodiment, the second conductivity type is, for example, N-type, and the first lightly doped region 122 and the second lightly doped region 124 are, for example, N-type lightly doped regions. The N-type dopant is, for example, phosphorus or arsenic. The concentration range of the first lightly doped region 122 and the second lightly doped region 124 is, for example, 10 ¹⁸ /cm ³ to 10 ²⁰ /cm ³ .

The first gate structure 112 has an outer side wall 112 a and an inner side wall 112 b; and the second gate structure 114 has an outer side wall 114 a and an inner side wall 114 b. The outer sidewall 112a of the first gate structure 112 and the outer sidewall 114a of the second gate structure 114 are closer to the isolation structure 104 than the inner sidewalls 112b and 114b; and the inner sidewall 112b of the first gate structure 112 and the second gate structure 114 The inner side walls 114b are adjacent to each other. In some embodiments, the first lightly doped region 122 is located in the substrate 102 next to the outer sidewall 112a of the first gate structure 112; the second lightly doped region 124 is located next to the outer sidewall 114a of the second gate structure 114 In the substrate 102; and the inner sidewall 112b of the first gate structure 112 and the inner sidewall 114b of the second gate structure 114 do not have a concentration similar to the first lightly doped region 122 and the second lightly doped region 124 Lightly doped area.

1C, after forming the first lightly doped region 122 and the second lightly doped region 124, a spacer 130 is formed on the sidewall of the gate structure assembly 110. In some embodiments, the spacer 130 is located on the outer sidewall 112a and the inner sidewall 112b of the first gate structure 112; and on the outer sidewall 114a and the inner sidewall 114b of the second gate structure 114. In some embodiments, the top surfaces of the first gate structure 112 and the second gate structure 114 are exposed. In other embodiments, the spacer 130 may further cover the top surfaces of the first gate structure 112 and the second gate structure 114. The material of the spacer 130 may be a dielectric material. The material of the spacer 130 is, for example, silicon nitride or silicon oxide, and the method of formation thereof is, for example, a chemical vapor deposition method. The spacer 130 may be a single layer or multiple layers. The step of forming the spacer 130 is, for example, first depositing a dielectric material layer on the substrate 102, and then performing anisotropic etching on the dielectric material layer.

Referring to FIGS. 1D, 1E and 2B at the same time, after the spacer 130 is formed, a patterned photoresist layer 18 is formed on the substrate 102. The patterned photoresist layer 18 has an opening O2. The photoresist layer 18 covers the isolation structure 104. In some embodiments, the opening O2 exposes the substrate 102 of the active area AA, the spacer 130, the first gate structure 112 and the second gate structure 114. In other embodiments, the opening O2 not only exposes the substrate 102, the spacer 130, the first gate structure 112 and the second gate structure 114 of the active area AA, but also exposes the isolation structure 104 around the active area AA. , As shown in Figure 1D and Figure 2B.

Next, an ion implantation process is performed to form an inner doped region 140 and an outer doped region 150 of the second conductivity type in a portion of the substrate 102 of the active region AA exposed by the opening O2. The outer doped region 150 having the second conductivity type includes a first outer doped region 152 and a second outer doped region 154. In other embodiments, based on process requirements, other photoresist pattern designs or other doping steps may be used to perform multiple ion implantation processes to form the inner doped region 140 and the first outer doped region 152 and the second doped region. Two outer doped regions 154. Next, the patterned photoresist layer 18 is removed.

The first outer doped region 152 is adjacent to the first gate structure 112, and the second outer doped region 154 is adjacent to the second gate structure 112. The first outer doped region 152 and the second outer doped region 154 may be the same type of outer doped region. The inner doped region 140 is, for example, sandwiched in the substrate 102 between the first gate structure 112 and the second gate structure 114; and the first outer doped region 152 and the second outer doped region 154 are located in the inner doped region 140. In the substrate 102 outside the first gate structure 112 and the second gate structure 114.

Specifically, the inner doped region 140 is sandwiched in the substrate 102 between the inner sidewall 112b of the first gate structure 112 and the inner sidewall 114b of the second gate structure 114, for example. In other words, the first gate structure 112 and the second gate structure 114 share the inner doped region 140. The first outer doped region 152 is, for example, in the substrate 102 adjacent to the outer sidewall 112a of the first gate structure 112; and the second outer doped region 154 is, for example, adjacent to the outer sidewall of the second gate structure 114 In the base 102 next to 114a.

In some embodiments, the sidewalls 152a and bottom surface 152b of the first outer doped region 152 are covered by the first lightly doped region 122; the sidewalls 154a and bottom surface 154b of the second outer doped region 154 are covered by the second lightly doped region 124 covered. The sidewall 140a and the bottom surface 140b of the inner doped region 140 are not covered by the lightly doped region. In other words, each lightly doped region 120 separates the corresponding outer doped region 150 from the substrate 102, so that the corresponding outer doped region 150 does not directly contact the substrate 102; while the inner doped region 140 directly contacts the substrate 102 . In some embodiments, the first outer doped region 152 and the second outer doped region 154 may be electrically connected to each other through subsequent formation of interconnections, as shown in FIG. 1E.

In some embodiments, the inner doped region 140 has a width W1; and the first outer doped region 152 and the second outer doped region 154 have a width W2. The width W1 of the inner doped region 140 is, for example, greater than or equal to the width W2 of the outer doped region 150, but the present invention is not limited thereto.

In this embodiment, the second conductivity type is, for example, N-type, and the inner doped region 140, the first outer doped region 152 and the second outer doped region 154 are, for example, N-type doped regions. The N-type dopant is, for example, phosphorus or arsenic. The doping concentration range of the inner doped region 140, the first outer doped region 152, and the second outer doped region 154 is, for example, 10 ²⁰ /cm ³ to 10 ²² /cm ³ .

In some embodiments, the doping concentration of the inner doping region 140 and the doping concentration of the first outer doping region 152 and the second outer doping region 154 may be the same; the inner doping region 140, the first outer doping region The doping concentration of the region 152 and the second outer doped region 154 and the doping concentration of the first lightly doped region 122 and the second lightly doped region 124 may be different. In some embodiments, the doping concentration of the inner doped region 140 is equal to the doping concentration of the first outer doped region 152 and the second outer doped region 154; the inner doped region 140, the first outer doped region 152 and The doping concentration of the second outer doped region 154 is greater than the doping concentration of the lightly doped region 120. In some embodiments, the doping concentration of the first lightly doped region 122 and the second lightly doped region 124 is the doping of the inner doped region 140, the first outer doped region 152 and the second outer doped region 154 1/1000 to 1/10 of the concentration.

In some embodiments, the inner doped region 140 is used as a source region; and the first outer doped region 152 and the second outer doped region 154 are used as drain regions, so the second lightly doped region The doped region 122 covers the sidewalls 152a and bottom surface 152b of the first outer doped region 152; the second lightly doped region 124 covers the sidewalls 154a and bottom surface 154b of the second outer doped region 154, which can reduce the source of the inner doped region ( The hot carrier effect caused by the electron flow of the source region 140 on the two outer doped regions (drain regions) 150 to protect the two first outer doped regions 152 and the second outer doped regions 152 Miscellaneous area (drain area) 154. The semiconductor device 100 is completed here.

In this embodiment, the first conductivity type is, for example, P type; the second conductivity type is, for example, N type. The semiconductor device 100 formed by the first gate structure 112, the second gate structure 114, the inner doped region 140, the first outer doped region 152, and the second outer doped region 154 is called an NMOS semiconductor device.

In this embodiment, by having an inner doped region 140 in a single semiconductor device 100 sandwiched between the first gate structure 112 and the second gate structure 114, the first outer doped region 152 and the second outer doped region The region 154 is located in the substrate outside the inner doped region 140 and the two gate structures 112, 114. The first lightly doped region 122 covers the sidewalls 152a and bottom surface 152b of the first outer doped region 152; The doped region 124 covers the sidewalls 154a and bottom surface 154b of the second outer doped region 154; and the sidewalls 140a and bottom surface 140b of the inner doped region 140 are not covered by the lightly doped regions, so that two adjacent inner doped regions 140 and the first outer doped region 152 or the second outer doped region 154 will not cause punch-through leakage current due to the lateral diffusion of two lightly doped regions 120 in contact with each other, Furthermore, the gate length of the semiconductor device 100 can be effectively shortened.

It must be noted here that the following embodiments use the component numbers and part of the content of the above embodiments, wherein the same or similar reference numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

3A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 3B is a diagram of the relationship between the thickness direction of the substrate and the doping concentration of FIG. 3A.

Please refer to FIGS. 3A and 3B at the same time. The semiconductor device 200 in FIG. 3A is similar to the semiconductor device 100 in FIG. 1E. The difference is that the first conductivity type of the semiconductor device 200 is, for example, N type; the second conductivity type is, for example, P type. The substrate 202 is, for example, an N-type substrate. The lightly doped region 220 is, for example, a P-type lightly doped region, where the lightly doped region 220 includes a first lightly doped region 222 and a second lightly doped region 224; the inner doped region 240 is, for example, a P-type doped region; The outer doped region 250 is, for example, a P-type doped region, where the outer doped region 250 includes a first outer doped region 252 and a second outer doped region 254. In this embodiment, the semiconductor device 200 formed by the first gate structure 112, the second gate structure 114, the inner doped region 240, the first outer doped region 252 and the second outer doped region 254 is called PMOS semiconductor components.

In some embodiments, as shown in FIG. 3B, the substrate 202 may have four non-uniform doped regions NW1, NW2, NW3, and NW4 in sequence from the bottom surface 202b to the top surface 202a. In other embodiments, it may also be a plurality of well regions diffused by high temperature thermal annealing or rapid thermal annealing. The doped region NW1 is, for example, located at a position of 1 μm~3 μm from the top surface 202a of the substrate 202; the doped region NW2 is, for example, located at a position of 0.5 μm~2 μm from the top surface 202a of the substrate 202; The top surface 202 a of 202 is at a position of 0.2 μm to 1 μm; and the doped region NW4 is, for example, located at a position of 0 μm to 0.6 μm from the top surface 202 a of the substrate 202. In some embodiments, the doping concentration range in the doped region NW1 is, for example, between 10 ¹⁴ /cm ³ and 10 ¹⁷ /cm ³ ; the doping concentration range in the doped region NW2 is, for example, between 10 ¹⁶ /cm ³ to 10 ¹⁸ /cm ³ ; the doping concentration range in the doped region NW3 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; and the doping concentration in the doped region NW4 The range is, for example, between 10 ¹⁶ /cm ³ and 10 ¹⁸ /cm ³ . In this embodiment, by doping different regions in the substrate 202 with different concentration ranges, the deeper doped regions NW1 and NW2 can reduce the resistance of the well region, and improve the latch up effect (latch up) to slow down the parasitic The turn-on phenomenon of the bi-carrier junction transistor (BJT); the doped regions NW2 and NW3 in the middle of the depth can not only complement the resistance distribution of the well in the deeper doped region, but also reduce the source /Drain from the breakdown phenomenon generated during the bias voltage to reduce the depletion phenomenon and improve the leakage current; and the shallowest doped region NW4 can adjust the threshold voltage of the semiconductor device, so there is no need to use an additional process to control the threshold voltage.

Please refer to FIG. 4, the semiconductor device 300 in FIG. 4 is similar to the semiconductor device 100 in FIG. 1D, except that the semiconductor device 300 has only one lightly doped region 320 with the second conductivity type, and the lightly doped region 320 Only the sidewall 140a and the bottom surface 140b of the inner doped region 140 are covered. In other words, the lightly doped region 320 separates the inner doped region 140 from the substrate 102, so that the inner doped region 140 does not directly contact the substrate 102; and the lightly doped region 320 does not separate the first outer doped region 152 from The second outer doped region 154 makes the first outer doped region 152 and the second outer doped region 154 directly contact the substrate 102.

Hereinafter, the effect of the semiconductor device of the embodiment of the present application will be explained through experiments.

<Example 1>

Conduct an electrical test on a semiconductor element 100 with a gate length (L) of 0.4μm. The electrical test items include critical voltage (V _T ), characteristic on-resistance (R _on ), drain-source current (I _DS ), Breakdown voltage (BVD) and leakage current (I _OF ), the results are shown in Table 1 and Figure 5.

<Comparative example 1>

A semiconductor element A is provided, wherein the semiconductor element A is an NMOS semiconductor element. The difference between the semiconductor device A and the semiconductor device 100 is: the semiconductor device A has only one gate structure, one source region and one drain region, and its gate length (L) is 0.6 μm. The semiconductor device A was tested for electrical properties, and the results are shown in Table 1 and FIG. 5.

＜Comparative example 2＞

A semiconductor element B is provided, wherein the semiconductor element B is an NMOS semiconductor element. The difference between the semiconductor device B and the semiconductor device 100 is that the semiconductor device B has only one gate structure, one source region and one drain region, and its gate length (L) is 0.55 μm. The semiconductor device B was subjected to electrical testing, and the results are shown in Table 1 and FIG. 5.

<Comparative Example 3>

A semiconductor element C is provided, wherein the semiconductor element C is an NMOS semiconductor element. The difference between the semiconductor device C and the semiconductor device 100 is that the semiconductor device C has only one gate structure, one source region and one drain region, and its gate length (L) is 0.5 μm. The semiconductor device C was subjected to electrical testing, and the results are shown in Table 1 and FIG. 5.

Table 1 L (μm) V _T (V) R _on (mohm-mm ² ) I _DS (μA/μm) BVD (V) I _OF (pA/μm) Example 1 0.4 1 1.86 401 12.3 0.6 Comparative example 1 0.5 0.7 1.43 680 10.5 37.5 Comparative example 2 0.55 0.7 1.98 622 12.2 1.1 Comparative example 3 0.6 0.8 2.31 572 12.3 0.07

The results from Table 1 and Figure 5 show that the electrical performance of the device of Example 1 with a gate length of 0.4μm can maintain the level of the devices of Comparative Examples 1 to 3 with a gate length of 0.6μm, 0.55μm and 0.5μm , It represents that the semiconductor device 100 of the present invention can still maintain certain electrical characteristics when the gate length is shortened and the specific on-resistance is reduced.

<Example 2>

The semiconductor device 200 with a gate length (L) of 0.4 μm was subjected to electrical testing, and the results are shown in Table 2 and FIG. 6.

<Comparative Example 4>

A semiconductor element D is provided, wherein the semiconductor element D is a PMOS semiconductor element. The difference between the semiconductor device D and the semiconductor device 200 is that the semiconductor device D has only one gate structure, one source region and one drain region, and its gate length (L) is 0.5 μm. The semiconductor device D was subjected to electrical testing, and the results are shown in Table 2 and FIG. 6.

Table 2 L (μm) V _T (V) R _on (mohm-mm ² ) I _DS (μA/μm) BVD (V) I _OF (pA/μm) Example 2 0.4 0.84 4.46 321 9 0.15 Comparative example 4 0.5 0.82 8 290 9 0.25

The results from Table 2 and Figure 6 show that the electrical performance of the device of Example 2 with a gate length of 0.4 μm can maintain the level of the device of Comparative Example 4 with a gate length of 0.5 μm, which represents the semiconductor device 200 of the present invention. When shortening the gate length and reducing the specific on-resistance, certain electrical characteristics can still be maintained.

In summary, the present invention uses a single semiconductor device with an inner doped region sandwiched between two gate structures, and two outer doped regions are located in the substrate outside the inner doped region and the two gate structures. , The lightly doped region covers the sidewall and bottom surface of the outer doped region, but does not cover the sidewall and bottom surface of the inner doped region, or the lightly doped region covers the sidewall and bottom surface of the inner doped region; The sidewalls and bottom surface of the outer doped region prevent two adjacent inner doped regions and outer doped regions from being in contact with each other by lateral diffusion of the two lightly doped regions, thereby causing breakdown leakage current. Shorten the gate length of semiconductor components while maintaining certain electrical characteristics.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

16, 18: Patterned photoresist layer 100, 200, 300, A, B, C, D: semiconductor components 102, 202: base 102a, 202a: the top surface of the substrate 102b, 202b: the bottom of the substrate 104: Isolation structure 110: Gate structure combination 112, 114: Gate structure 12a, 14a: gate dielectric layer 12b, 14b: Conductor layer 120, 122, 124, 220, 222, 224, 320: lightly doped area 112a, 114a: outer wall 112b, 114b: inner wall 130: Clearance Wall 140, 240: inner doped area 150, 152, 154, 250, 252, 254: outer doped area 140a: sidewall of the inner doped region 140b: bottom surface of inner doped region 152a, 154a: sidewalls of the outer doped region 152b, 154b: the bottom surface of the outer doped region AA: active area L1, L2: gate length O1, O2: opening PW1, PW2, PW3, PW4, NW1, NW2, NW3, NW4: doped area W1, W2: width

1A to 1E are schematic cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the invention. FIG. 1F is a diagram of the relationship between the thickness direction of the substrate and the doping concentration of FIG. 1A. FIG. 2A is a schematic top view of the semiconductor device according to FIG. 1B. FIG. 2B is a schematic top view of the semiconductor device according to FIG. 1D. 3A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 3B is a diagram of the relationship between the thickness direction of the substrate and the doping concentration of FIG. 3A. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. 5 is a graph showing the electrical characteristics of the semiconductor device in FIG. 1E and the semiconductor device in the comparative example. 6 is a graph showing the electrical characteristics of the semiconductor device according to FIG. 3A and the semiconductor device of the comparative example.

100: Semiconductor components

102: Base

104: Isolation structure

110, 112, 114: gate structure

12a, 14a: gate dielectric layer

12b, 14b: Conductor layer

120, 122, 124: lightly doped area

112a, 114a: outer wall

112b, 114b: inner wall

130: Clearance Wall

140: inner doped area

150, 152, 154: outer doped area

140a: sidewall of the inner doped region

140b: bottom surface of inner doped region

152a, 154a: sidewalls of the outer doped region

152b, 154b: the bottom surface of the outer doped region

AA: active area

W1, W2: width

Claims (10)

A semiconductor component, including: The substrate has a first conductivity type; At least one gate structure combination, each of the gate structure combinations includes a first gate structure and a second gate structure, and the gate structure combination is disposed on the substrate; The semiconductor element including each of the gate structure combinations includes: The inner doped region has a second conductivity type, wherein the inner doped region is located in the substrate, and the inner doped region is sandwiched between the first gate structure and the second gate structure ； Two outer doped regions having the second conductivity type, wherein the two outer doped regions are located in the substrate, and the two outer doped regions are located in the inner doped regions, the second A gate structure and the substrate outside the second gate structure; and Two lightly doped regions having the second conductivity type, wherein the two lightly doped regions are located in the substrate, and the lightly doped regions cover the sidewalls and the bottom surface of the outer doped region, and The sidewalls and bottom surface of the inner doped region are not covered by the lightly doped region. The semiconductor device according to the first item of the patent application, wherein the inner doped region is a source region, and the outer doped region is a drain region. The semiconductor device described in item 2 of the scope of patent application, wherein the two drain regions are electrically connected to each other. The semiconductor device according to item 1 of the scope of patent application, wherein the doping concentration of the outer doped region is greater than the doping concentration of the lightly doped region. The semiconductor device according to the first item of the patent application, wherein the inner doped region is in direct contact with the substrate. According to the semiconductor device described in item 1 of the scope of patent application, each of the lightly doped regions separates the corresponding outer doped region and the substrate. A semiconductor component, including: The substrate has a first conductivity type; At least one gate structure combination, each of the gate structure combinations includes a first gate structure and a second gate structure, and the gate structure combination is disposed on the substrate; The semiconductor element including each of the gate structure combinations includes: The inner doped region has a second conductivity type, wherein the inner doped region is located in the substrate, and the inner doped region is sandwiched between the first gate structure and the second gate structure ； Two outer doped regions having the second conductivity type, wherein the two outer doped regions are located in the substrate, and the two outer doped regions are located in the inner doped regions, the second A gate structure and the substrate outside the second gate structure; and The lightly doped region has the second conductivity type, wherein the lightly doped region is located in the substrate, the lightly doped region covers the sidewall and the bottom surface of the inner doped region, and the outer doped region The sidewall and bottom surface of the impurity region are not covered by the lightly doped region. The semiconductor device according to item 7 of the scope of patent application, wherein the doping concentration of the inner doped region is greater than the doping concentration of the lightly doped region. According to the semiconductor device described in claim 7, wherein the outer doped region is in direct contact with the substrate. According to the semiconductor device described in item 7 of the scope of patent application, the inner doped region is a source region, and the outer doped region is a drain region.

Images