KR20100013946A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20100013946A
KR20100013946A KR1020080075710A KR20080075710A KR20100013946A KR 20100013946 A KR20100013946 A KR 20100013946A KR 1020080075710 A KR1020080075710 A KR 1020080075710A KR 20080075710 A KR20080075710 A KR 20080075710A KR 20100013946 A KR20100013946 A KR 20100013946A
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KR
South Korea
Prior art keywords
film
tungsten
manufacturing
semiconductor device
gate
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KR1020080075710A
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Korean (ko)
Inventor
김수진
박은실
홍권
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주식회사 하이닉스반도체
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Priority to KR1020080075710A priority Critical patent/KR20100013946A/en
Publication of KR20100013946A publication Critical patent/KR20100013946A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

PURPOSE: A manufacturing method of a semiconductor device is provided to improve a retention characteristic of a device by preventing generation of a residue including tungsten generated in the sidewall of an insulating film when etching a gate. CONSTITUTION: A gate insulating film, a polysilicon film(104a), tungsten film and hard mask film(114) are successively formed in a semiconductor substrate(100). A hard mask film and a tungsten film are patterned. A protective film(116) is formed in the whole surface including the tungsten film exposed. The protective film remains in the sidewall of the tungsten film by pattering the polysilicon film and the bottom side of the protection film. The protection film is formed into the lamination film of an oxide film and a nitride film, or the oxide film.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a semiconductor capable of improving retention characteristics of a device by preventing the generation of tungsten-containing residues that may occur on the sidewalls of the dielectric layer and the tunnel insulation layer during tungsten gate etching. A method for manufacturing a device.

Recently, the development of semiconductor devices has been focused on high integration. As a part of this, development of a flash device having high integration and low manufacturing cost has been actively conducted.

The flash cell is operated by applying a bias to the control gate, which is operated by a potential induced in the floating gate. Since the potential of the floating gate is determined by the potential of the peripheral electrode and its own trap charge amount, the charge retention capability of the floating gate becomes a very important factor.

In general, when a gate of a flash memory device is manufactured, a tunnel insulating film, a floating gate conductive film, a dielectric film, a control gate conductive film, and a hard mask film are formed, followed by an exposure and etching process to form a gate line. However, as the flash memory device is highly integrated, the gate line width is reduced, and when the tungsten silicide (WSix) film used as the control gate electrode is used as it is, the resistance of the control gate increases and the RC delay increases, resulting in deterioration of device characteristics. . Accordingly, recently, in order to lower the resistance of a flash memory device, tungsten having a lower specific resistance than tungsten silicide (WSix) has been adopted as a control gate electrode.

In the conventional tungsten gate etching process of a flash memory device, the tungsten film is patterned by plasma etching using a combination of HBr / N 2 / Cl 2 gas. However, plasma etching using a combination of HBr / N 2 / Cl 2 gases during tungsten film etching may result in excessive polymerisation reactions resulting in a tungsten-containing residue or a tungsten-containing polymer on the tungsten film sidewalls of the control gate. Generates. Since this material is not removed in a subsequent cleaning process, it affects the dielectric film or the tunnel insulating film, causing charge loss, thereby lowering retention characteristics. This affects the program and erase in the gate operation, causing problems in the operation of the device.

The present invention forms a protective film on the exposed sidewall of the tungsten film after etching the tungsten film to prevent exposure of the tungsten film during subsequent gate etching, thereby suppressing the generation of residues of tungsten containing on the sidewalls of the dielectric film and the tunnel insulation film. It is to provide a method of manufacturing a semiconductor device that can prevent the loss to improve the retention characteristics of the device.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device may include providing a semiconductor substrate on which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask film are sequentially formed, patterning the hard mask film and the tungsten film, and exposing the same. Forming a protective film on the entire surface including the tungsten film and patterning the bottom surface of the protective film and the polysilicon film between the protective film sidewalls.

In the above, a part of the polysilicon film is etched during the tungsten film patterning.

The protective film is formed of an oxide film. The oxide film is formed by any one of Low Pressure Chemical Vapor Deposition (LPCVD), Radial Oxidation, and Plasma Enhanced CVD (PECVD) methods.

The LPCVD oxide film is formed of a TEOS (Tetra Ethyl Ortho Silicate) film or a DCS-HTO (Dichlorosilane-High Temperature Oxide) film.

The radical oxidation method deposits SiO 2 or Si 3 N 4 together at the bottom and oxidizes it.

The protective film is formed in a laminated structure of an oxide film and a nitride film.

The oxide film is formed by a CVD method, in which case the CVD method is loaded at a temperature of 200 to 400 ° C, In a DCS and N 2 O gas atmosphere at a temperature of 700 to 900 ° C. and a pressure of 0.1 to 1.OTorr.

The nitride film is formed by a CVD method, in which case the CVD method is performed at a temperature of 600 to 800 ° C. and a pressure of 0.1 to 1.OTorr under a DCS and NH 3 gas atmosphere.

After the polysilicon film patterning, the protective film remains on the side wall of the tungsten film.

A laminated film of the floating silicon polysilicon film and the dielectric film is further formed between the polysilicon film and the gate insulating film.

When the polysilicon film for floating gate is patterned, a part of the gate insulating film is etched.

After the polysilicon film patterning, the method may further include performing a reoxidation process on the gate pattern.

The reoxidation process is carried out at a temperature of 800 to 950 ° C. in an O 2 gas atmosphere.

The present invention has the following effects.

First, after the tungsten film is etched, a protective film is formed on the exposed sidewall of the tungsten film so that the tungsten film is completely protected by the protective film during the subsequent gate etching process, thereby essentially suppressing the generation of tungsten-containing residues on the sidewalls of the dielectric film and the tunnel insulating film. As a result, charge loss can be prevented to improve retention characteristics of the device.

Second, it is possible to mass-produce a gated flash device using tungsten and to use tungsten as a gate electrode to mass-produce a fast product.

Third, since the tungsten film is not exposed, a re-oxidation process for mitigating damage during the gate line etching may be performed without restriction of tungsten abnormal oxidation.

Fourth, when the double film of the oxide film and the nitride film laminated structure is used as the protective film of the tungsten film, it is possible to reduce the stress that may occur when proceeding to a single film of the nitride film.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, the tunnel insulating film 102, the floating silicon polysilicon film 104, the dielectric film 106, the control gate conductive film 108, and the hard mask film 114 are sequentially formed by a known method. Provided is a semiconductor substrate 100 formed. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO 2 ), and in this case, may be formed by an oxidation process. In a DRAM manufacturing process, the tunnel insulating film 102 is used as a gate insulating film. The floating gate polysilicon film 104 is used as a gate electrode in a floating gate and a DRAM manufacturing process of a NAND flash memory device.

After the floating gate polysilicon layer 104 is formed, the floating gate polysilicon layer 104, the tunnel insulating layer 102, and the semiconductor substrate 100 are etched by an etching process using a mask (not shown). And a trench (not shown) is formed. Subsequently, an isolation material is deposited on the floating gate polysilicon film 104 including the trench and then planarized to form an isolation layer (not shown) in the region where the trench is formed.

The dielectric film 106 is formed on the floating silicon polysilicon film 104 and the device isolation film, and may be formed of a laminated film of an oxide film, a nitride film, and an oxide film (Oxide-Nitride-Oxide; ONO). The control gate conductive film 108 is used as a gate electrode in a control gate and DRAM manufacturing process of a NAND flash memory device, and may be formed of a polysilicon film, a metal layer, or a stacked film thereof. In order to implement a high speed device, the polysilicon film 110 and the tungsten (W) film 112 are preferably stacked. The tungsten film 112 may be formed by a chemical vapor deposition (CVD) method. In this case, the CVD method may be performed at 1500 to 2000 W power and Ar atmosphere using WF 6 as a reaction gas.

On the other hand, when the control gate conductive film 108 is formed of a laminated structure of the polysilicon film 110 and the tungsten film 112, a tungsten nitride film WN (not shown) is further deposited below the tungsten film 112. Can be formed. The hard mask layer 114 may be formed by including an oxide-based or nitride-based material. For example, the hard mask layer 114 may be formed of a laminated film such as a SiON / TEOS (Tetra Ethyl Ortho Silicate) oxide film or an amorphous carbon film. Can be.

Subsequently, a first gate etching process is performed to pattern the hard mask film 114 and the tungsten film 112 in an etching process using a mask (not shown). The primary gate etching process is performed by a dry etch process. The etching process of the tungsten film 112 is performed on N 2 and Cl 2 in HBr gas to prevent anisotropic etching of the polysilicon film 110. This can be carried out using a plasma of a mixed gas to which a gas is added. At this time, added N 2 and Cl 2 The gas serves to prevent anisotropic etching of the polysilicon film 110 formed under the tungsten film 112.

The primary gate etching process stops etching in a state where a part of the polysilicon film 110 is etched so that the tungsten film 112 can be fully patterned. As a result, the polysilicon film 110 is partially etched.

Although not shown in the drawings, the first gate etching process may be performed by patterning the hard mask layer 114 and the tungsten layer 112 by an etching process using a mask, and stopping the etching on the upper surface of the polysilicon layer 110. have.

However, the primary gate etching process does not stop the etching in the ONO dielectric film 106 and stops the etching in a state where a part of the polysilicon film 110 is etched or etched up to the tungsten film 112. This is because a residue containing tungsten, which is formed once on the sidewall of the dielectric film 106, is not completely removed.

When the tungsten film 112 is etched using the above-described method, a polymer is attached to the sidewall of the partially patterned polysilicon film 110 due to a polymerization reaction, so that the anisotropy of the polysilicon film 110 is applied. Etching is prevented. However, due to excessive polymerization, tungsten-containing residues or tungsten-containing polymers are also generated on the sidewalls of the tungsten film 112.

Thereafter, a cleaning process for removing the tungsten-containing residue or the tungsten-containing polymer is performed. Some are removed by the cleaning process but are not completely removed and remain. If the material is not removed in the cleaning process and affects the dielectric film 106 or the tunnel insulating film 102, a solution is required because it causes charge loss and degrades retention characteristics. This will be described later.

Referring to FIG. 1B, the passivation layer 116 is formed on the entire surface including the exposed polysilicon layer 110. The passivation layer 116 may be formed as a single layer or a double layer. First, in the case of forming a single layer, the protective layer 116 may be formed of an oxide layer to secure an etch margin during subsequent gate etching. In this case, the oxide layer may be formed of low pressure chemical vapor deposition. It is preferable to form using any one of Deposition (LPCVD), Radial Oxidation and Plasma Enhanced CVD (PECVD). The LPCVD oxide film may be formed of a TEOS (Tetra Ethyl Ortho Silicate) film or a DCS-HTO (Dichlorosilane-High Temperature Oxide) film.

On the other hand, since the radical oxidation method is to oxidize a portion of silicon (Si), silicon oxide film (SiO 2 ) or silicon nitride film (Si 3 N 4 ), to form a radical oxide film, a silicon oxide film (SiO 2 ) is formed underneath. Or a silicon nitride film (Si 3 N 4 ) is deposited together.

On the other hand, when the double layer is formed, the passivation layer 116 may have a stacked structure of an oxide layer and a nitride layer to secure an etching margin for the passivation layer 116 in a subsequent gate etching process, and may occur when the nitride layer is formed as a single layer. Can alleviate stress. In this case, the oxide film may be formed by a CVD method, in which case the CVD method is loaded at a temperature of 200 to 400 ° C. so that tungsten oxidation does not occur, and dichlorosilane (SiH 2 Cl 2 , Dichlorosilane; And a temperature of 700 to 900 ° C. and a pressure of 0.1 to 1.OTorr under an N 2 O gas atmosphere. The nitride film may be formed by a CVD method, in which case the CVD method may be performed at a temperature of 600 to 800 ° C. and a pressure of 0.1 to 1.OTorr under a DCS and NH 3 gas atmosphere.

Referring to FIG. 1C, a second gate etching process is performed to pattern the polysilicon film 110, the dielectric film 106, and the polysilicon film 104 for floating gate. The secondary gate etching process is performed by a dry etching process, and the bottom surface of the protective film 116 between the sidewalls of the protective film 116, the polysilicon film 110, the dielectric film 106, and the polysilicon film 104 for the floating gate are formed. Etch sequentially.

The polysilicon film 110 for the control gate and the polysilicon film 104 for the floating gate are O 2 in HBr gas. Etching may be performed by using a plasma of a mixed gas or HBr single gas added with a gas. The dielectric film 106 is formed of CxFy (1 ≦ x ≦ 6, such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , C 5 F 8 , C 4 F 6 , C 6 F 6, etc.). 4≤y≤8) and at least one of CHxFy (1≤x≤4, 0≤y≤3) series gases such as CHF 3 , CH 2 F 2 , CH 3 F, CH 4 The etching may be performed using plasma etching using a single gas or a mixed gas as a stock angle gas. In order to control the etch stop, the etching rate, or the plasma uniformity, the stock angle gas may further include at least one additional gas of HBr, O 2 , N 2 , He, Ne, and Ar.

In this case, the secondary gate etching process stops the etching in a state where a part of the tunnel insulating layer 102 is etched so that the patterning of the floating silicon polysilicon layer 104 is performed intact. As a result, a portion of the tunnel insulating film 102 is etched. The tunnel insulating layer 102 may be partially used to prevent attack of the semiconductor substrate 100 or may be used as a buffer layer in a subsequent ion implantation process.

In particular, in the second gate etching process, the passivation layer 116 on the upper surface and the upper sidewall is removed, and a portion of the passivation layer 116 on the sidewall of the tungsten layer 112 also has a selectivity ratio to the gate etch dry chemisty. It is etched by the difference. However, since the protective film 116 is formed of a single layer of an oxide film having a selectivity to the gate etch dry chemistry, or a stacked structure of an oxide film / nitride film, an etching margin is secured, so that a part of the protective film 116 is formed of a tungsten film ( 112 remains on the sidewalls and the sidewalls of the tungsten film 112 are completely protected. Thus, after the second gate etching, a part of the passivation layer 116 is left in the form of a spacer on the edges of both sidewalls from the partial thickness of the polysilicon layer 110 to the hard mask layer 114. In addition, in the second gate etching process, the hard mask layer 114 may be etched together to be lowered by some thickness.

Thereby, the control gate 108a which consists of the floating gate 104a which consists of the polysilicon film 104 for floating gates, and the control film conductive layer 108 which laminated | stacked the polysilicon film 110 and tungsten film 112 is Is formed. At this time, the thickness of the tunnel insulating film 102, the floating gate 104a, the dielectric film 106, the control gate 108a, the hard mask film 114, and the polysilicon film 110 to the hard mask film 114 may be varied. A gate pattern 118 is formed that includes the passivation layer 116 remaining at edges of both sidewalls of the gate.

However, when only the tungsten film 112 is patterned in the primary gate etching process, the tunnel insulating film 102, the floating gate 104a, the dielectric film 106, the control gate 108a, and the hard mask film 114 are formed. And a protective film 116 remaining at the edges of both side walls from the tungsten film 112 to the hard mask film 114.

As described above, according to an embodiment of the present invention, by forming a protective film 116 on the side wall of the tungsten film 112 exposed after the primary gate etching process, the protective film 116 during the subsequent secondary gate etching process As a result, the side wall of the tungsten film 112 is completely protected. Therefore, the generation of tungsten-containing residues that may occur on the sidewalls of the dielectric film 106 and the tunnel insulating film 102 may be essentially suppressed to prevent loss of electric charges, thereby improving retention characteristics of the device.

Thereafter, a cleaning process is performed to remove poly residues or oxide residues generated during the secondary gate etching process. Poly residues or oxide residues generated during the secondary gate etching process include a mixed solution of H 2 SO 4 and H 2 O 2 , buffered oxide etchant (BOE) and SC-1 (NH 4 OH, H 2 O 2 and Since it is sufficiently removed with a cleaning liquid such as H 2 0 mixed solution, it is possible to fundamentally solve a charge loss problem.

Referring to FIG. 1D, a re-oxidation process is performed to mitigate damage generated during gate etching after the gate etching process. The reoxidation process may proceed at a temperature of 800 to 950 ° C. in an O 2 gas atmosphere. Here, the reoxidation process may be performed by a selective oxidation process. As a result, a selective oxide layer 120 is formed on the entire surface of the gate pattern 118 by the reoxidation process.

Conventionally, in the selective oxidation process performed to reduce the damage after the gate etching, sufficient curing was not performed because the conditions were limited to prevent abnormal oxidation of tungsten. However, in one embodiment of the present invention, since the tungsten film 112 is not exposed, a re-oxidation process for alleviating damage during gate line etching may be performed without restriction of tungsten abnormal oxidation.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1D are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: polysilicon film for floating gate 104a: floating gate

106 dielectric film 108 conductive film for control gate

108a: control gate 110: polysilicon film

112: tungsten film 114: hard mask film

116: protective film 118: gate pattern

120: selective oxide film

Claims (17)

Providing a semiconductor substrate on which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask film are sequentially formed; Patterning the hard mask film and the tungsten film; Forming a protective film on the entire surface including the exposed tungsten film; And And patterning the bottom surface of the protective film and the polysilicon film between sidewalls of the protective film. The method of claim 1, wherein in the tungsten film patterning, A method of manufacturing a semiconductor device for etching a portion of the polysilicon film. The method of claim 1, The protective film is a method of manufacturing a semiconductor device formed of an oxide film. The method of claim 3, wherein The oxide film is a method of manufacturing a semiconductor device is formed by any one of the LPCVD method, radical oxidation method and PECVD method. The method of claim 4, wherein And the oxide film of the LPCVD method is formed of a TEOS film or a DCS-HTO film. The method of claim 4, wherein The radical oxidation method is a method of manufacturing a semiconductor device by depositing SiO 2 or Si 3 N 4 together at the bottom, and oxidizing it. The method of claim 1, The protective film is a method of manufacturing a semiconductor device formed of a laminated structure of an oxide film and a nitride film. The method of claim 7, wherein A method of manufacturing a semiconductor device formed by the oxide film CVD method. The method of claim 8, The CVD method is a method of manufacturing a semiconductor device is loaded at a temperature of 200 to 400 ℃. The method of claim 8, The CVD method is a method of manufacturing a semiconductor device is carried out at a temperature of 700 to 900 ℃ and a pressure of 0.1 to 1. Otor in a DCS and N 2 O gas atmosphere. The method of claim 7, wherein The nitride film is a method of manufacturing a semiconductor device formed by a CVD method. The method of claim 11, The CVD method is a method of manufacturing a semiconductor device is carried out at a temperature of 600 to 800 ℃ and a pressure of 0.1 to 1. Otor in a DCS and NH 3 gas atmosphere. The method of claim 1, wherein after the polysilicon film patterning, And the protective film is left on the sidewall of the tungsten film. The method of claim 1, And a stacked layer of a floating gate polysilicon film and a dielectric film is further formed between the polysilicon film and the gate insulating film. 15. The method of claim 14, wherein in the polysilicon film patterning for the floating gate, A method of manufacturing a semiconductor device to etch a portion of the gate insulating film. The method of claim 1, After the polysilicon film patterning, performing a reoxidation process on the gate pattern. The method of claim 16, The reoxidation process is a method of manufacturing a semiconductor device is carried out at a temperature of 800 to 950 ℃ in O 2 gas atmosphere.
KR1020080075710A 2008-08-01 2008-08-01 Method of manufacturing a semiconductor device KR20100013946A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8754464B2 (en) 2011-06-13 2014-06-17 Samsung Electronics Co., Ltd. Non-volatile memory devices including gates having reduced widths and protection spacers and methods of manufacturing the same
US9378977B2 (en) 2010-12-13 2016-06-28 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378977B2 (en) 2010-12-13 2016-06-28 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of fabricating the same
US8754464B2 (en) 2011-06-13 2014-06-17 Samsung Electronics Co., Ltd. Non-volatile memory devices including gates having reduced widths and protection spacers and methods of manufacturing the same

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