KR20120003692A - Method for manufacturing semiconductor device with buried gate - Google Patents

Method for manufacturing semiconductor device with buried gate Download PDF

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Publication number
KR20120003692A
KR20120003692A KR1020100064437A KR20100064437A KR20120003692A KR 20120003692 A KR20120003692 A KR 20120003692A KR 1020100064437 A KR1020100064437 A KR 1020100064437A KR 20100064437 A KR20100064437 A KR 20100064437A KR 20120003692 A KR20120003692 A KR 20120003692A
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South Korea
Prior art keywords
film
substrate
layer
ferry
region
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KR1020100064437A
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Korean (ko)
Inventor
신승아
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주식회사 하이닉스반도체
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Priority to KR1020100064437A priority Critical patent/KR20120003692A/en
Publication of KR20120003692A publication Critical patent/KR20120003692A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can prevent deterioration of characteristics and deterioration of reliability of semiconductor devices due to barriers formed at boundary regions of cell and ferry regions in a semiconductor device having a buried gate. The present invention includes forming a plurality of buried gates in the cell region substrate of the substrate having a cell region and a ferry region; Forming an insulating film on the entire surface of the substrate; Exposing a substrate of the ferry region using a ferry mask; Forming a ferrite gate conductive film and a protective film on the entire surface of the substrate; Forming a sacrificial layer on the passivation layer such that an upper surface thereof is flat; Etching the sacrificial layer and the passivation layer until the ferrite conductive layer of the cell region is exposed; Performing a planarization process until the insulating film of the cell region is exposed; And removing the remaining protective film.

Description

Method for manufacturing semiconductor device with buried gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a buried gate (BG).

As micronization progresses in the semiconductor process, various device characteristics and process implementations are becoming difficult. In particular, the formation of the gate structure, the bit line structure, and the contact structure is showing a limit as it goes below 40 nm. Difficulties exist. Recently, the buried gate (BG) process, in which the gate is buried in the active region, is introduced to reduce parasitic capacitance, increase process margin, and minimize the formation of a smallest cell transistor. .

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to the prior art.

As shown in FIG. 1A, the sealing film 15 and the insulating film 16 are sequentially formed on the entire surface of the substrate 11 having the cell region in which the plurality of buried gates 100 are formed and the ferry region (or the peripheral circuit region). do. Here, the buried gate 100 formed in the cell region may include a trench 12, a cell gate insulating film 13 formed on the surface of the trench 12, and a cell gate electrode partially filling the trench 12 on the cell gate insulating film 13. 14), the sealing film 15 has a structure covering the entire surface of the substrate 11 while filling the remaining trench 12.

Next, after the insulating film 16 and the sealing film 15 of the cell region are selectively etched to form the bit line contact hole 17 exposing the substrate 11 between the buried gate 100, the substrate front surface 11 is formed. The plug conductive film 18 is deposited so as to fill the bit line contact hole 17.

Next, after the first photoresist layer pattern 19 is formed on the plug conductive layer 18 by using a peri open mask, the first photoresist layer pattern 19 may be formed as an etch barrier. The conductive film 18, the insulating film 16, and the sealing film 15 are sequentially etched to expose the substrate 11 of the ferry region.

As shown in FIG. 1B, after the first photoresist layer pattern 19 is removed, the ferrite gate insulating layer 20 and the ferrite gate conductive layer 21 are sequentially formed on the entire surface of the substrate 11.

Next, the second photoresist layer pattern 22 is formed on the ferrite gate conductive layer 21 by using a cell open mask.

As shown in FIG. 1C, the ferrite gate 21, the ferrite gate 20, and the plug conductive layer 18 in the cell region are sequentially etched using the second photoresist layer 22 as an etch barrier. After the contact plugs 18A are formed, the second photoresist pattern 22 is removed. Hereinafter, the reference numeral of the etched ferrite gate conductive film 21 is changed to '21A'.

Here, when the etching process for forming the bit line contact plug 18A is completed due to the region where the cell open mask and the ferry open mask overlap each other, a barrier A occurs in the boundary region where the cell region and the ferry region are in contact with each other. .

As shown in FIG. 1D, a planarization process is performed to remove the barrier A formed at the boundary between the cell region and the ferry region. At this time, the planarization process is carried out using chemical mechanical polishing (CMP). Hereinafter, the reference numeral of the ferrite gate conductive film 21A from which the barrier is removed is denoted by '21B'.

As shown in FIG. 1E, the conductive film 23 and the hard mask film 24 are sequentially formed on the entire surface of the substrate 11, and then the hard mask film 24 and the conductive film 23 are sequentially formed in the cell region. Etching to form a bit line 26 in contact with the bit line contact plug 18A, the hard mask film 24, the conductive film 23, the ferrite gate conductive film 21B and the ferry gate insulating film 20 in the ferry region. ) Is sequentially etched to form the ferrigate 25. Hereinafter, the reference numerals of the etched ferrite gate conductive film 21B and the ferrite gate insulating film 20 are changed to '21C' and '20A', respectively.

However, in the prior art, a problem arises that the structure formed in the cell region and the ferry region is damaged during the planarization process for removing the barrier A formed at the boundary region where the cell region and the ferry region are in contact. Specifically, as the barrier A is separated during the planarization process, the structure formed under the barrier A is lost (see reference numeral 'B' in FIG. 1D), or the ferrigate conductive film 21B of the ferry region is lost. Problem occurs (see reference numeral 'C' in FIG. 1D).

As described above, defects caused during the planarization process to remove the barrier A cause problems such as the loss of the substrate 11 during the subsequent process of forming the ferrite 25 (see reference numeral 'D' in FIG. 1E). Therefore, problems such as deterioration of characteristics of the semiconductor device and deterioration of reliability occur.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and in the semiconductor device having a buried gate, it is possible to prevent deterioration of characteristics and deterioration of characteristics of the semiconductor device due to a barrier formed at a boundary region of a cell region and a ferry region. A semiconductor device manufacturing method can be provided.

According to an aspect of the present invention, there is provided a method including: forming a plurality of buried gates in a cell region substrate of a substrate having a cell region and a ferry region; Forming an insulating film on the entire surface of the substrate; Exposing a substrate of the ferry region using a ferry mask; Forming a ferrite gate conductive film and a protective film on the entire surface of the substrate; Forming a sacrificial layer on the passivation layer such that an upper surface thereof is flat; Etching the sacrificial layer and the passivation layer until the ferrite conductive layer of the cell region is exposed; Performing a planarization process until the insulating film of the cell region is exposed; And removing the remaining protective film.

The passivation layer is formed of a material having an etching selectivity with respect to the ferrite gate conductive layer and the insulating layer. Specifically, the passivation layer may include a nitride layer, the ferrite gate conductive layer may include a polysilicon layer, and the insulating layer may include an oxide layer.

The sacrificial film may be formed as a photosensitive film. Etching the sacrificial layer and the passivation layer until the ferrite conductive layer of the cell region is exposed may be performed under an etching condition in which an etching selectivity ratio of the sacrificial layer to the passivation layer is 1: 1. The planarization process may be performed using chemical mechanical polishing or etch back. The removing of the protective layer may be performed by using a wet etching method.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of sequentially forming a conductive film and a hard mask film on the entire surface of the substrate; And selectively etching the conductive layer and the hard mask layer of the cell region to form a bit line, and simultaneously etching the hard mask layer, the conductive layer, and the ferrite gate conductive layer of the ferry region to form a ferrite gate. can do.

The semiconductor device manufacturing method of the present invention may further include forming a bit line contact hole by selectively etching the insulating film of the cell region before exposing the substrate of the ferry region by using the perimeter mask; And forming a plug conductive layer on an entire surface of the substrate to fill the bit line contact hole. In this case, in the performing of the planarization process, the plug conductive layer may be etched to form a bit line contact plug to fill the bit line contact hole.

The present invention based on the above-described problem solving means, by using a cell-open mask and a cell-open mask alternately by not using a cell-open mask during the etching process for forming a bit line contact plug in the cell region, It is possible to prevent the occurrence of barriers at the boundary area of the ferry area at the source. Through this, problems occurring in the process of removing the barrier may also be prevented at the source.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to the prior art.
2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention, which will be described later, in the manufacture of a semiconductor device capable of preventing deterioration of characteristics and deterioration of the reliability of the semiconductor device due to a barrier formed in a boundary region of a cell region and a ferry region in a semiconductor device having a buried gate (BG). Provide a method.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

As shown in FIG. 2A, an isolation layer (not shown) is formed on the substrate 31 in which a cell region and a ferry region (or a peripheral circuit region) are defined to define a plurality of active regions (not shown). In this case, a silicon substrate may be used as the substrate 31.

Next, the substrate 31 is selectively etched to form a plurality of trenches 12 in the cell region. In this case, the trench 32 is provided to provide a space in which the buried gate 200 is to be formed, and may be formed in a line pattern that simultaneously crosses an isolation layer (not shown) and an active region (not shown). .

Next, a cell gate insulating film 33 is formed on the trench 32 surface. The cell gate insulating film 33 may be formed of an oxide film. For example, the cell gate insulating film 33 may be formed of a silicon oxide film (SiO 2 ) using thermal oxidation.

Next, a cell gate electrode 34 is formed on the cell gate insulating film 33 to partially fill the trench 32. The cell gate electrode 34 may be formed of a metal film.

The buried gate 200 having a structure buried in the substrate 31 may be formed through the above-described process.

Next, a sealing film 35 covering the entire surface of the substrate 31 and filling the remaining trenches 32 is formed, and an insulating film 36 is formed on the sealing film 35. The sealing film 35 may be formed of a single film made of an oxide film or a nitride film or a laminated film in which an oxide film and a nitride film are laminated. The insulating film 36 can be formed of an oxide film, for example, a TEOS film.

Next, the insulating film 36 and the sealing film 35 are selectively etched to form bit line contact holes 37 exposing the substrate 31 between the buried gates 200.

Next, a plug conductive film 38 is deposited on the entire surface of the substrate 31 to fill the bit line contact hole 37. The plug conductive film 38 may be formed of a polysilicon film.

Next, the first photoresist layer pattern 39 is formed on the plug conductive layer 38 by using a peri open mask.

Next, the plug conductive layer 38, the insulating layer 36, and the sealing layer 35 of the ferry region are sequentially etched using the first photoresist layer pattern 39 as an etch barrier to expose the substrate 31 of the ferry region.

As shown in FIG. 2B, after the first photoresist layer pattern 39 is removed, the ferrite gate insulating layer 40 is formed on the substrate 31 of the ferry region. The ferry gate insulating film 40 may be formed of an oxide film. For example, the ferrite gate insulating film 40 may be formed of a silicon oxide film using a thermal oxidation method.

Next, the ferrite gate conductive film 41 is formed over the entire surface of the substrate 31. The ferrogate conductive film 41 may be formed of a polysilicon film.

Next, in order to protect the ferrite gate conductive film 41 which will remain in the ferry region during the subsequent process, the passivation film 42 is formed on the ferrite gate conductive film 41. The passivation layer 42 is formed of a material having an etching selectivity with the insulating layer 36 and the ferrite gate conductive layer 41. For example, the protective film 42 may be formed of a nitride film, and a silicon nitride film may be used as the nitride film.

Next, the photosensitive film 43 is formed on the protective film 42. Since the photoresist layer 43 is formed through spin coating, the photoresist layer 43 may be formed to have a flat top surface regardless of the level difference of the lower structure.

As shown in FIG. 2C, an etching process is performed until the ferrite conductive layer 41 of the cell region is exposed. At this time, the photosensitive film 43 and the protective film 42 remain in the ferry region. Hereinafter, when the etching process is completed, the reference numerals of the photosensitive film 43 and the protective film 42 are changed to '43A' and '42A', respectively.

In order to leave the photoresist 43A and the passivation layer 42A in the ferry region, the etching process is performed using an etching gas having an etching selectivity of 1: 1 to 43A, that is, a photoresist 43A to nitride. It is desirable to. Specifically, the etching process may be performed using a mixed gas in which CHF 3 and CF 4 are mixed at a ratio of 200: 10 (CHF 3 : CF 4 ). In this case, the bias power may use a range of 50W to 300W. In this case, SF 6 may be used instead of CF 4 . For reference, the photosensitive layer 43A may be etched with a gas such as O 2 , Cl 2 , CF 4 / CHF 3, and the main component is carbon polymer. In this case, the CF 4 / CHF 3 mixed gas etches the photoresist 43A and at the same time the hydrogen component from the CHF 3 reacts with the etching by-product CN (non-volatile at room temperature) formed during the etching of the nitride film to form HCN. It is effective to increase the etching speed of. Therefore, a CF 4 / CHF 3 mixed gas is suitable as a gas for simultaneously etching the photosensitive film 43A and the protective film 42A.

As shown in FIG. 2D, the planarization process is performed until the top surface of the insulating film 36 is exposed. In this case, the planarization process may be performed using an etch back or chemical mechanical polishing. Through the planarization process, a bit line contact plug 38A is formed in the cell region to fill the bit line contact hole 37. Hereinafter, the reference numerals of the protective film 42A and the ferrite gate conductive film 41 remaining after the planarization process are changed to '42B' and '41A', respectively.

Here, as the upper surface of the entire structure is formed to be flat during the etching process performed before the planarization process, the planarization process may be stably performed. In addition, due to the protective film 42B remaining on the ferrite gate 41A, it is possible to prevent the loss of (or damage) the ferrite gate 41A remaining in the ferry region until the planarization process is completed. .

As shown in Fig. 2E, the protective film 42B remaining in the ferry region is removed. At this time, the protective film 42B is removed using a wet etching method to prevent damage to the formed structure in the process of removing the protective film 42B. For example, when the protective film 42B is formed of a nitride film, the protective film 42B can be removed using a phosphoric acid solution.

As shown in FIG. 2F, the conductive film 44 and the hard mask film 45 are sequentially formed on the entire surface of the substrate 31. At this time, the conductive film 44 may be formed of a metal film. The hard mask film 45 may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked.

Next, the conductive layer 44 and the hard mask layer 45 of the cell region are sequentially etched to form a bit line 46 electrically connected to the bit line contact plug 38A. At the same time, the ferry gate 47 is formed by sequentially etching the hard mask layer 45, the conductive layer 44, the ferrite gate conductive layer 41A, and the ferrite gate insulating layer 40 in the ferry region. Hereinafter, the reference numerals of the etched ferrite gate insulating film 40 and the ferrite gate conductive film 41A are changed to '40A' and '41B', respectively.

According to the exemplary embodiment of the present invention, the cell open mask is not used during the etching process for forming the bit line contact plug 38A in the cell region, and thus the cell open mask is alternately used. It is possible to prevent the occurrence of barriers at the boundary area between the area and the ferry area. Through this, problems occurring in the process of removing the barrier may be prevented at the source.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

31 substrate 32 trench
33: cell gate insulating film 34: cell gate electrode
35 sealing film 36 insulating film
37: bit line contact hole 38: plug conductive film
38A: Bit line contact plug 39: First photoresist pattern
40, 40A: ferrite gate insulating film 41, 41A, 41B: ferrite gate conductive film
42, 42A, 42B: Protective film 43, 43A: Photosensitive film
44: conductive film 45: hard mask film
46: bit line 47: ferry gate
200: landfill gate

Claims (10)

Forming a plurality of buried gates in the cell region substrate of the substrate having a cell region and a ferry region;
Forming an insulating film on the entire surface of the substrate;
Exposing a substrate of the ferry region using a ferry mask;
Forming a ferrite gate conductive film and a protective film on the entire surface of the substrate;
Forming a sacrificial layer on the passivation layer such that an upper surface thereof is flat;
Etching the sacrificial layer and the passivation layer until the ferrite conductive layer of the cell region is exposed;
Performing a planarization process until the insulating film of the cell region is exposed; And
Removing the remaining protective film
Semiconductor device manufacturing method comprising a.
The method of claim 1,
And the passivation layer is formed of a material having an etch selectivity with respect to the ferrite gate conductive layer and the insulating layer.
The method of claim 2,
The protective film includes a nitride film, the ferrite gate conductive film includes a polysilicon film, and the insulating film includes an oxide film.
The method of claim 1,
And the sacrificial film is formed of a photosensitive film.
The method of claim 1,
Etching the sacrificial layer and the passivation layer until the ferrite conductive layer of the cell region is exposed, wherein the etch selectivity of the sacrificial layer and the passivation layer is 1: 1.
The method of claim 1,
And the planarization step is performed using chemical mechanical polishing or etch back.
The method of claim 1,
Removing the protective film is a semiconductor device manufacturing method using a wet etching method.
The method of claim 1,
Sequentially forming a conductive film and a hard mask film over the entire surface of the substrate; And
Selectively etching the conductive layer and the hard mask layer of the cell region to form a bit line and simultaneously etching the hard mask layer, the conductive layer, and the ferrite gate conductive layer of the ferry region to form a ferrite gate.
A semiconductor device manufacturing method further comprising.
The method of claim 1,
Prior to exposing the substrate of the ferry region using the ferry mask.
Selectively etching the insulating film of the cell region to form a bit line contact hole; And
Forming a plug conductive film on the entire surface of the substrate to fill the bit line contact hole
A semiconductor device manufacturing method further comprising. 10. The method of claim 9,
And forming a bit line contact plug to bury the bit line contact hole by etching the plug conductive layer in the planarization process.
KR1020100064437A 2010-07-05 2010-07-05 Method for manufacturing semiconductor device with buried gate KR20120003692A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10553800B2 (en) 2016-01-05 2020-02-04 Samsung Display Co., Ltd. Condensed cyclic compound and an organic light-emitting device including the same
US11670591B2 (en) 2021-02-15 2023-06-06 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10553800B2 (en) 2016-01-05 2020-02-04 Samsung Display Co., Ltd. Condensed cyclic compound and an organic light-emitting device including the same
US10580999B2 (en) 2016-01-05 2020-03-03 Samsung Display Co., Ltd. Condensed cyclic compound and an organic light-emitting device including the same
US11107999B2 (en) 2016-01-05 2021-08-31 Samsung Display Co., Ltd. Condensed cyclic compound and an organic light-emitting device including the same
US11276827B2 (en) 2016-01-05 2022-03-15 Samsung Display Co., Ltd. Condensed cyclic compound and an organic light-emitting device including the same
US11670591B2 (en) 2021-02-15 2023-06-06 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating same
US12009299B2 (en) 2021-02-15 2024-06-11 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating same

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