KR100967023B1 - Method for Manufacturing Semiconductor Device - Google Patents
Method for Manufacturing Semiconductor Device Download PDFInfo
- Publication number
- KR100967023B1 KR100967023B1 KR1020080036634A KR20080036634A KR100967023B1 KR 100967023 B1 KR100967023 B1 KR 100967023B1 KR 1020080036634 A KR1020080036634 A KR 1020080036634A KR 20080036634 A KR20080036634 A KR 20080036634A KR 100967023 B1 KR100967023 B1 KR 100967023B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- etching
- film
- gate
- semiconductor device
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 랜딩플러그 에치백 후, 손상된 실리콘을 큐어링(Curing)하기 위해 LET(Light etch treatment) 공정을 실시하되, LET 공정 후에 클리닝 공정을 추가함으로써, 퓸(Fume)을 제거하여 후속 공정의 이온 주입 공정 중 투사 범위를 균일하게 하여 반도체 디바이스(Device) 특성을 향상시키는 기술을 개시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. After etching a landing plug, a LET (Light etch treatment) process is performed to cure damaged silicon. Disclosed is a technique of improving a semiconductor device characteristic by removing a fume to make the projection range uniform during an ion implantation process of a subsequent process.
Description
도 1은 종래 기술에 따른 반도체 소자의 형성 방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming a semiconductor device according to the prior art.
도 1a 내지 도 1i는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도.1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
<도면의 주요 부분에 대한 부호 설명> <Description of the symbols for the main parts of the drawings>
100: 반도체 기판 110: 게이트100: semiconductor substrate 110: gate
120: 제 1 절연막 130: 하드마스크층 120: first insulating film 130: hard mask layer
140: 제 2 절연막 150: 감광막 패턴 140: second insulating film 150: photosensitive film pattern
160: 랜딩플러그 콘택홀 170: 산화막160: landing plug contact hole 170: oxide film
180: 스페이서 190: 퓸(Fume) 180: spacer 190: Fume
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 랜딩플러그 에치백 후, 손상된 실리콘을 큐어링(Curing)하기 위해 LET(Light etch treatment) 공정을 실시 하되, LET 공정 후에 클리닝 공정을 추가함으로써, 퓸(Fume)을 제거하여 후속 공정의 이온 주입 공정 중 투사 범위를 균일하게 하여 반도체 디바이스(Device) 특성을 향상시키는 기술을 개시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. After landing plug etch back, a LET (Light etch treatment) process is performed to cure damaged silicon, but after the LET process, a cleaning process is added, Disclosed is a technique of improving a semiconductor device characteristic by removing a fume to make the projection range uniform during an ion implantation process of a subsequent process.
최근, 반도체 장치의 제조 기술의 발달과 메모리 소자의 응용분야가 확장 되어 감에 따라, 집적도는 향상되면서 전기적 특성은 저하되지 않는 대용량의 메모리 소자를 제조하기 위한 기술 개발이 절실히 요구되고 있다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, there is an urgent need to develop a technology for manufacturing a large-capacity memory device in which the degree of integration is improved while the electrical characteristics thereof are not degraded.
이에 따라, 포토리소그래피(Photo-lithography) 공정, 셀 구조 및 배선 형성 물질과 절연막 형성 물질의 물성 한계 등을 개선하여 안정한 공정 조건을 얻기 위한 연구가 다각적으로 이루어지고 있다.Accordingly, various studies have been conducted to obtain stable process conditions by improving photolithography processes, cell structures, physical property limitations of wiring forming materials and insulating film forming materials, and the like.
이 가운데, 상기 포토리소그래피 공정은 소자를 구성하는 여러 층들을 연결해 주는 콘택 형성 공정이나 패턴 형성 공정 시에 적용되는 필수 기술로서, 상기 포토리소그래피 공정 기술의 향상이 고집적화 반도체 소자의 성패를 가름하는 관건이 된다.Among these, the photolithography process is an essential technology applied in the contact forming process or the pattern forming process for connecting the various layers constituting the device, and the improvement of the photolithography process technology determines the success or failure of the highly integrated semiconductor device. do.
현재 상용화되고 있는 포토리소그래피 공정은 KrF 및 ArF와 같은 단파장 광원을 사용하는 노광 장비를 이용하고 있으나, 이러한 단파장 광원으로부터 얻어지는 패턴의 해상도는 0.1㎛ 정도로 한정되어 있다. The photolithography process currently commercialized uses exposure equipment using short wavelength light sources such as KrF and ArF, but the resolution of the pattern obtained from such short wavelength light sources is limited to about 0.1 μm.
따라서, 이보다 적은 크기의 패턴을 형성하여 고집적화된 반도체 소자를 제조하는 것에 어려움이 따른다.Therefore, there is a difficulty in manufacturing a highly integrated semiconductor device by forming a pattern having a smaller size than this.
이와 같은 문제점을 개선하고, 상기 포토리소그래피 공정상에 콘택홀 패턴의 한계 해상력을 높여 노광 장비의 이상의 해상도를 가지는 미세 콘택홀을 얻어내기 위한 공정 기술로 레지스트 플로우 공정(Resist Flow Process; 이하 "RFP")이 도입되었다.A resist flow process ("RFP") is a process technology for improving such a problem and obtaining a fine contact hole having an abnormal resolution of an exposure apparatus by increasing the limit resolution of a contact hole pattern on the photolithography process. ) Was introduced.
여기서, 종래에는 랜딩플러그 에치백 식각 후, 손상된 실리콘을 큐어링(Curing)하기 위해 LET(Light Etch Treatment) 공정을 진행하게 된다. Here, conventionally, after landing plug etch back etching, a light etching treatment (LET) process is performed to cure damaged silicon.
하지만, LET 공정 후에 발생하는 퓸(Fume)으로 인해 후속 이온주입의 Rp점이 웨이퍼 위치별로 달라서 셀 저항의 균일성이 현저히 저하되는 문제가 있다.However, due to the fume generated after the LET process, there is a problem that the uniformity of the cell resistance is significantly lowered because the Rp point of subsequent ion implantation is different for each wafer position.
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 랜딩플러그 에치백 후, 손상된 실리콘을 큐어링(Curing)하기 위해 LET(Light etch treatment) 공정을 실시하되, LET 공정 후에 클리닝 공정을 추가함으로써, 퓸(Fume)을 제거하여 후속 공정의 이온 주입 공정 중 투사 범위를 균일하게 하여 반도체 디바이스(Device) 특성을 향상시키는 반도체 소자의 형성 방법을 제공하는 것을 목적으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. After etching a landing plug, a LET (Light etch treatment) process is performed to cure damaged silicon. It is an object of the present invention to provide a method of forming a semiconductor device which removes the fume to make the projection range uniform during the ion implantation step of the subsequent step to improve semiconductor device characteristics.
본 발명에 따른 반도체 소자의 형성 방법은, The method for forming a semiconductor device according to the present invention,
반도체 기판상에 게이트를 형성하는 단계와,Forming a gate on the semiconductor substrate,
상기 게이트를 포함한 전체 표면상에 제 1 절연막을 형성하는 단계와,Forming a first insulating film on the entire surface including the gate;
상기 제 1 절연막을 평탄화 식각하여 게이트를 노출하는 단계와,Planarization etching the first insulating layer to expose a gate;
상기 제 1 절연막 상에 하드마스크층 및 제 2 절연막을 형성하는 단계와,Forming a hard mask layer and a second insulating film on the first insulating film;
상기 제 2 절연막 상에 랜딩플러그 콘택홀을 정의하는 마스크로 제 2 절연막, 하드마스크층 및 제 1 절연막을 식각하여 랜딩플러그 콘택홀을 형성하는 단계 와,Etching the second insulating film, the hard mask layer, and the first insulating film with a mask defining a landing plug contact hole on the second insulating film to form a landing plug contact hole;
상기 게이트 상에 산화막 및 스페이서를 형성하는 단계와,Forming an oxide film and a spacer on the gate;
상기 랜딩플러그 콘택홀을 식각하여 반도체 기판을 노출하는 단계와,Etching the landing plug contact hole to expose a semiconductor substrate;
상기 반도체 기판에 LET(Light Etch Treatment) 공정을 실시하는 단계 및Performing a light etching treatment (LET) process on the semiconductor substrate; and
전체 표면에 클리닝 공정을 실시하여 퓸을 제거하는 단계를 포함하는 것을 특징으로 한다.Performing a cleaning process on the entire surface to remove the fume.
여기서, 상기 제 2 절연막은 PETEOS막으로 형성하는 것과,Here, the second insulating film is formed of a PETEOS film,
상기 산화막은 USG(Undoped Silicate Glass) 산화막으로 형성하는 것과,The oxide film is formed of a USG (Undoped Silicate Glass) oxide film,
상기 스페이서(Spacer)는 질화막으로 형성하는 것과,The spacer is formed of a nitride film,
상기 랜딩플러그 콘택홀은 에치백(Etchback)공정으로 식각하는 것과,The landing plug contact hole is etched by an etchback process,
상기 클리닝 공정은 황산과 과수를 50:1로 희석시킨 용액을 이용하여 90℃에서 퓸을 제거하는 것과, The cleaning process is to remove the fume at 90 ℃ using a solution diluted 50: 1 sulfuric acid and fruit water,
상기 퓸을 제거한 후, 암모니아, 과수 및 물을 1:4:20으로 혼합한 용액을 이용하여 25℃에서 남은 파티클을 제거하는 것을 더 포함하는 것을 특징으로 한다.After removing the fume, it is characterized in that it further comprises removing the remaining particles at 25 ℃ using a solution of 1: 4: 20 mixed with ammonia, fruit water and water.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부한 도면을 참조하여 설명한다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.
또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장 된 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급된 경우에 그것은 다른 층 또는 기판상에 직접 형성될 수 있거나, 또는 그들 사이에 제 3의 층이 개재될 수도 있다. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween.
또한, 명세서 전체에 걸쳐서 동일한 참조 번호가 표시된 부분은 동일한 구성요소들을 나타낸다.Also, the same reference numerals throughout the specification represent the same components.
도 1a 내지 도 1i는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도이다.1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.
도 1a를 참조하면, 반도체 기판(100)상에 게이트(110)를 형성한다.Referring to FIG. 1A, a
다음에는, 게이트(110)를 포함한 전체 표면상에 제 1 절연막(120)을 형성한 후, 어닐링(Annealing) 공정을 통해 제 1 절연막(120)을 고르게 다진다. Next, after the first
이때, 제 1 절연막(120)은 BPSG(Boro-Phospho-Silicate Glass)막이 바람직하다.In this case, the first
도 1b를 참조하면, 제 1 절연막(120)을 평탄화 식각(Chemical Mechanical Polishing; CMP)하여 게이트(110)를 노출한다.Referring to FIG. 1B, the first
도 1c 및 도 1d를 참조하면, 제 1 절연막(120) 상에 하드마스크층(130)을 형성한 후, 하드마스크층(130) 상에 제 2 절연막(140)을 형성한다.1C and 1D, after forming the
이때, 제 2 절연막(140)은 PETEOS(Plasma Enhanced Tetraethylosilicate)막이 바람직하다.In this case, the second
도 1e를 참조하면, 제 2 절연막(140) 상에 반사방지막(미도시) 및 감광막을 형성한다.Referring to FIG. 1E, an anti-reflection film (not shown) and a photoresist film are formed on the second
다음에는, 랜딩플러그 콘택홀 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(150)을 형성한다.Next, the
도 1f를 참조하면, 감광막 패턴(150)을 마스크로 반사방지막, 제 2 절연막(140), 하드마스크층(130) 및 제 1 절연막(120)을 식각하여 랜딩플러그 콘택홀(160)을 형성한다.Referring to FIG. 1F, the landing
다음에는, 감광막 패턴(150)을 제거한다.Next, the
도 1g를 참조하면, 게이트(110) 상에 게이트(110)를 보호하기 위한 산화막(170)을 형성한 후, 스페이서(180)를 전체 표면상에 형성한다.Referring to FIG. 1G, after forming an
이때, 산화막(170)은 USG(Undoped Silicate Glass) 산화막(Oxide)으로 형성하며, 스텝커버리지(step coverage)가 좋지않은 산화막(170)을 이용하여 게이트(110) 상측부를 덮는 형태로 형성한다.In this case, the
여기서, USG 산화막은 CVD를 이용하여 증착하는 종류로서, 가스 유량비 및 파워를 조절하여 스텝 커버리지를 조절할 수 있다. Here, the USG oxide film is a type deposited by CVD, and the step coverage may be adjusted by adjusting the gas flow rate ratio and power.
또한, 스페이서(Spacer; 180)는 질화막(Nitride)으로 형성하는 것이 바람직하다.In addition, the
도 1h 및 도 1i를 참조하면, 반도체 기판(100)이 노출될 때까지 랜딩플러그 콘택홀(160) 사이의 산화막(170) 및 스페이서(180)를 식각한다.1H and 1I, the
이때, 산화막(170) 및 스페이서(180)를 식각하는 방법은 에치백(Etchback) 공정을 이용하여 식각하는 것이 바람직하다.In this case, the method of etching the
다음에는, 손상된 반도체 기판(100)을 큐어링(Curing)하기 위해 LET(Light Etch Treatment) 공정을 실시한다.Next, a light etching treatment (LET) process is performed to cure the damaged
여기서, LET 공정은 손상된 실리콘 격자를 CF4 및 O2를 이용한 플라즈마(Plasma)를 이용하여 큐어링(Curing)함으로써 셀 저항을 조절할 수 있다.Here, the LET process may control the cell resistance by curing the damaged silicon lattice using plasma using CF 4 and O 2 .
이때, LET 공정은 반도체 기판(100)상에 퓸(fume; 190)을 잔류시킨다.In this case, the LET process leaves
그 다음에는, LET 공정 후, 반도체 기판(100)상에 잔류하고 있는 퓸(190)을 제거하기 위해 클리닝(Cleaning) 공정을 실시한다.Next, after the LET process, a cleaning process is performed to remove the
특히, 남은 퓸(190)은 F(플루오린)을 포함한 퓸(190)이기 때문에, 상기 퓸(190)을 제거하기 위한 클리닝 공정을 실시하되, 황산과 과수를 50:1로 희석시킨 용액을 이용하여 90℃에서 퓸(190)을 제거한다. 더불어, 암모니아, 과수 및 물을 1:4:20으로 혼합한 용액을 이용하여 25℃에서 클리닝 공정을 실시하여 나머지 잔류 파티클을 제거한다.In particular, since the remaining
후속 공정으로, 노출된 랜딩플러그 콘택홀에 도전 물질을 형성한다. In a subsequent process, a conductive material is formed in the exposed landing plug contact holes.
이때, 도전 물질은 폴리실리콘으로 형성하는 것이 바람직하며, 상기 도전 물질을 에치백(Etchback) 또는 CMP(Chemical Mechanical Polishing) 공정을 수행하여 콘택 플러그(미도시)를 형성한다.In this case, the conductive material is preferably formed of polysilicon, and a contact plug (not shown) is formed by performing an etchback or chemical mechanical polishing (CMP) process on the conductive material.
본 발명은 반도체 소자의 형성 방법에 관한 것으로, 랜딩플러그 에치백 후, 손상된 실리콘을 큐어링(Curing)하기 위해 LET(Light etch treatment) 공정을 실시하되, LET 공정 후에 클리닝 공정을 추가함으로써, 퓸(Fume)을 제거하여 후속 공정의 이온 주입 공정 중 투사 범위를 균일하게 하여 반도체 디바이스(Device) 특성을 향상시키는 효과를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. After etching a landing plug, a LET (Light etch treatment) process is performed to cure damaged silicon. Fume) is removed to uniformize the projection range during the ion implantation process of the subsequent process, thereby providing an effect of improving semiconductor device characteristics.
아울러 본 발명의 바람직한 실시 예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080036634A KR100967023B1 (en) | 2008-04-21 | 2008-04-21 | Method for Manufacturing Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080036634A KR100967023B1 (en) | 2008-04-21 | 2008-04-21 | Method for Manufacturing Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20090111061A KR20090111061A (en) | 2009-10-26 |
| KR100967023B1 true KR100967023B1 (en) | 2010-06-30 |
Family
ID=41538859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080036634A KR100967023B1 (en) | 2008-04-21 | 2008-04-21 | Method for Manufacturing Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100967023B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060076556A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Semiconductor device with double layer landing plug contact |
| KR20070063672A (en) * | 2005-12-15 | 2007-06-20 | 주식회사 하이닉스반도체 | Method for forming storagenode contact in semiconductor device |
| KR20070074175A (en) * | 2006-01-06 | 2007-07-12 | 주식회사 하이닉스반도체 | Method for manufacturing storagenode contact in semiconductor device |
-
2008
- 2008-04-21 KR KR1020080036634A patent/KR100967023B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060076556A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Semiconductor device with double layer landing plug contact |
| KR20070063672A (en) * | 2005-12-15 | 2007-06-20 | 주식회사 하이닉스반도체 | Method for forming storagenode contact in semiconductor device |
| KR20070074175A (en) * | 2006-01-06 | 2007-07-12 | 주식회사 하이닉스반도체 | Method for manufacturing storagenode contact in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090111061A (en) | 2009-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10049919B2 (en) | Semiconductor device including a target integrated circuit pattern | |
| KR101004691B1 (en) | Method for forming micropattern in semiconductor device | |
| JP4619839B2 (en) | Pattern formation method | |
| US9466486B2 (en) | Method for integrated circuit patterning | |
| KR20180121327A (en) | Patterning Method for Semiconductor Device and Structures resulting therefrom | |
| TW200307986A (en) | Semiconductor device and method for forming transistors having a reduced pitch | |
| KR20090022667A (en) | Method for forming micropattern in semiconductor device | |
| KR102159209B1 (en) | Chemical composition for tri-layer removal | |
| KR20090027430A (en) | Method for forming micropattern in semiconductor device | |
| KR20010106923A (en) | A manufacturing method for semiconductor device | |
| KR100843899B1 (en) | Method for manufacturing of semiconductor device | |
| KR100967023B1 (en) | Method for Manufacturing Semiconductor Device | |
| KR20070113604A (en) | Method for forming micro pattern of semiconductor device | |
| KR100715600B1 (en) | Method of fabricating the fine pattern | |
| KR20090027431A (en) | Method for forming micropattern in semiconductor device | |
| KR100944344B1 (en) | Manufacturing method for semiconductor device | |
| KR20090044855A (en) | Method for manufacturing semiconductor device | |
| KR20070006052A (en) | Method of making non-salicide of semiconductor device | |
| KR20060115136A (en) | Method for fabricating flash memory device | |
| KR20030058573A (en) | Manufacturing method for semiconductor device | |
| KR20050064652A (en) | Method of manufacturing a flash memory device | |
| KR100513798B1 (en) | Fabricating method of semiconductor device with good planarization of flow dielectrics | |
| KR100685618B1 (en) | Methoe for fabricating of semiconductor device | |
| KR100390999B1 (en) | A method for forming of a semiconductor device | |
| TW202133225A (en) | Method for forming semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |