KR20080088275A - Method for fabricating contact plug in semiconductor device - Google Patents

Method for fabricating contact plug in semiconductor device Download PDF

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Publication number
KR20080088275A
KR20080088275A KR1020070031073A KR20070031073A KR20080088275A KR 20080088275 A KR20080088275 A KR 20080088275A KR 1020070031073 A KR1020070031073 A KR 1020070031073A KR 20070031073 A KR20070031073 A KR 20070031073A KR 20080088275 A KR20080088275 A KR 20080088275A
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South Korea
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semiconductor device
contact plug
insulating layer
manufacturing
contact hole
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KR1020070031073A
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Korean (ko)
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이정석
남기원
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주식회사 하이닉스반도체
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Priority to KR1020070031073A priority Critical patent/KR20080088275A/en
Publication of KR20080088275A publication Critical patent/KR20080088275A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Abstract

A method for manufacturing a contact plug of a semiconductor device is provided to form a reliable element by preventing an attack of a bit line hard mask and improving a contact area margin with a storage node. An insulating layer is formed on an upper surface of a substrate(31). A contact hole(41) is formed by etching the insulating layer. A protective layer is buried into the contact hole. The protective layer is lower than a surface of the insulating layer. An upper width of the contact hole is increased by performing an isotropic etch process. The protective layer is removed. The insulating layer is composed of an oxide layer. A CF-based gas as a main gas and oxygen and Ar gases as additional gases are used in the process for forming the contact hole.

Description

반도체 소자의 콘택 플러그 제조방법{METHOD FOR FABRICATING CONTACT PLUG IN SEMICONDUCTOR DEVICE}Method for manufacturing contact plug of semiconductor device {METHOD FOR FABRICATING CONTACT PLUG IN SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자의 콘택 플러그를 나타내는 단면도,1 is a cross-sectional view showing a contact plug of a semiconductor device according to the prior art;

도 2a 내지 도 2f는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 플러그 제조방법을 설명하기 위한 공정 단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to a preferred embodiment of the present invention.

* 공정의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the process

31 : 기판 32 : 게이트패턴31 substrate 32 gate pattern

33 : 게이트측벽보호막 34 : 제1절연층33: gate side wall protective film 34: first insulating layer

35 : 랜딩 플러그 콘택 36 : 제2절연층35 landing plug contact 36 second insulating layer

37 : 비트라인패턴 38 : 비트라인측벽보호막37: bit line pattern 38: bit line sidewall protection film

39 : 제3절연층 40 : 마스크패턴39: third insulating layer 40: mask pattern

41 : 콘택홀 42 : 보호막41: contact hole 42: protective film

43A : 스토리지 노드 콘택 플러그43A: Storage Node Contact Plug

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 콘택 플러그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method for manufacturing contact plugs in semiconductor devices.

반도체 소자의 집적화에 따라 라인(Line) 및 폭(Spacing)이 감소되고 이로 인해 스토리지 노드 콘택홀(Storage Node Contact Hole) 오픈(Open) 및 스토리지 노드와 스토리지 노드 콘택 플러그(Storage Node Contact Plug)간의 접촉 면적 마진(Margin)이 감소함에 따라 기존의 홀(Hole) 타입의 스토리지 노드 콘택 대신에 라인타입(Line Type)의 스토리지 노드 콘택을 적용하고 있다.Line and spacing is reduced due to the integration of semiconductor devices, which leads to the opening of the storage node contact hole and the contact between the storage node and the storage node contact plug. As the area margin decreases, line type storage node contacts are applied instead of the conventional hole type storage node contacts.

도 1은 종래 기술에 따른 반도체 소자의 콘택 플러그를 나타내는 단면도이다. 도면의 좌측은 비트라인패턴과 교차하는 방향으로 절취한 도면이고, 우측은 비트라인패턴과 나란한 방향으로 절취한 도면이다. 이하, 자세한 설명을 위해 두 방향에서의 공정 단면도를 함께 보여준다.1 is a cross-sectional view showing a contact plug of a semiconductor device according to the prior art. The left side of the figure is a diagram cut in the direction crossing the bit line pattern, and the right side is a figure cut in the direction parallel to the bit line pattern. Hereinafter, the cross-sectional views of the process in two directions are shown together for detailed description.

도 1에 도시된 바와 같이, 반도체 기판(11) 상에 게이트패턴(12)을 형성하고, 게이트패턴(12)의 측벽에 게이트측벽보호막(13)을 형성한다. 여기서, 게이트패턴(12)은 폴리실리콘전극(12A), 텅스텐전극(12B) 및 게이트하드마스크질화막(12C)의 적층구조이고, 게이트측벽보호막(13)은 질화막이다.As shown in FIG. 1, a gate pattern 12 is formed on a semiconductor substrate 11, and a gate sidewall protective film 13 is formed on sidewalls of the gate pattern 12. Here, the gate pattern 12 is a laminated structure of the polysilicon electrode 12A, the tungsten electrode 12B, and the gate hard mask nitride film 12C, and the gate side wall protective film 13 is a nitride film.

이어서, 게이트패턴(12) 사이를 채우는 제1산화막(14)을 형성하고, 게이트패턴(12) 사이의 제1산화막(14)을 식각한 후 도전물질을 매립하여 랜딩 플러그 콘택(15, Landing Plug Contact)을 형성한다.Subsequently, a first oxide layer 14 is formed between the gate patterns 12, the first oxide layer 14 between the gate patterns 12 is etched, and a conductive material is embedded to fill the landing plug contacts 15. Form a contact.

이어서, 랜딩 플러그 콘택(15)을 포함하는 전면에 제2산화막(16)을 형성하고, 제2산화막(16) 상에 비트라인패턴(17)을 형성한 후 비트라인패턴(17)의 측벽에 비트라인측벽보호막(18)을 형성한다. 여기서, 비트라인패턴(17)은 폴리실리콘전극(17A), 텅스텐전극(17B) 및 비트라인하드마스크질화막(17C)의 적층구조이고, 비트라인측벽보호막(18)은 질화막이다.Subsequently, a second oxide layer 16 is formed on the entire surface including the landing plug contact 15, a bit line pattern 17 is formed on the second oxide layer 16, and then a sidewall of the bit line pattern 17 is formed. The bit line side wall protective film 18 is formed. Here, the bit line pattern 17 is a laminated structure of the polysilicon electrode 17A, the tungsten electrode 17B, and the bit line hard mask nitride film 17C, and the bit line side wall protective film 18 is a nitride film.

이어서, 비트라인패턴(17) 사이를 채우는 제3산화막(19)을 형성하고, 비트라인패턴(17) 사이의 제3산화막(19)을 식각하여 스토리지 노드 콘택홀(20, Storage Node Contact Hole)을 형성한다.Subsequently, a third oxide layer 19 is formed to fill the bit line patterns 17, and the third oxide layer 19 between the bit line patterns 17 is etched to form a storage node contact hole 20. To form.

위와 같이, 종래 기술은 스토리지 노드 콘택홀(20)을 형성할 때 스토리지 노드와 스토리지 노드 콘택 간의 접촉 면적 마진을 증가시키기 위해 제3산화막(19)의 상부를 일차 건식식각하고, 습식식각을 실시하여 스토리지 노드 콘택홀(30)의 상부 면적을 증가시킨 후, 추가로 이차 건식식각을 통해 랜딩 플러그 콘택(15)이 오픈되는 스토리지 노드 콘택홀(20)을 형성한다.As described above, in the prior art, when the storage node contact hole 20 is formed, the first dry etching and wet etching are performed on the upper portion of the third oxide layer 19 to increase the contact area margin between the storage node and the storage node contact. After the upper area of the storage node contact hole 30 is increased, the storage node contact hole 20 is further formed to open the landing plug contact 15 through secondary dry etching.

그러나, 일차 건식식각 및 습식식각을 통한 일정 부분의 하부막 식각으로 후속 이차 건식식각시 발생시킬 수 있는 폴리머(Polymer) 양이 감소하게 되고, 이로 인해 비트라인하드마스크질화막(17C)가 어택(Attack, 100)을 받아서 결국 자기정렬콘택 페일(Self Aligned Contact Fail)을 유발하는 문제점이 있다.However, a portion of the lower layer etching through primary dry etching and wet etching reduces the amount of polymer that can be generated during subsequent secondary dry etching, which causes the bit line hard mask nitride layer 17C to attack. , 100) and eventually cause a self-aligned contact fail.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 스토 리지 노드와 스토리지 노드 콘택 간의 접촉 면적 마진을 증가시키면서 비트라인하드마스크의 어택을 방지할 수 있는 반도체 소자의 콘택 플러그 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and a method of manufacturing a contact plug of a semiconductor device capable of preventing attack of a bit line hard mask while increasing a contact area margin between a storage node and a storage node contact. The purpose is to provide.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택 플러그 제조방법은 기판 상부에 절연층을 형성하는 단계, 상기 절연층을 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀에 상기 절연층의 표면보다 낮은 높이로 보호막을 매립하는 단계, 등방성식각으로 상기 콘택홀의 상부폭을 넓히는 단계, 상기 보호막을 제거하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a contact plug of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating layer on the substrate, etching the insulating layer to form a contact hole, rather than a surface of the insulating layer in the contact hole. Embedding the protective film at a low height, widening the upper width of the contact hole by isotropic etching, and removing the protective film.

특히, 절연층은 산화막이고, 콘택홀을 형성하는 단계는 CF계 가스를 메인가스로 사용하고 산소 및 아르곤(Ar) 가스를 첨가하여 실시하는 것을 특징으로 한다.In particular, the insulating layer is an oxide film, and the forming of the contact hole is performed by using CF gas as the main gas and adding oxygen and argon (Ar) gas.

또한, 등방성식각은 습식식각으로 실시하고, 습식식각은 BOE(Buffered Oxide Etchant) 또는 HF를 사용하여 실시하는 것을 특징으로 한다.In addition, isotropic etching is performed by wet etching, and wet etching is performed using BOE (Buffered Oxide Etchant) or HF.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2f는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 플러그 제조방법을 설명하기 위한 공정 단면도이다. 도면의 좌측은 비트라인패턴과 교차하는 방향으로 절취한 도면이고, 우측은 비트라인패턴과 나란한 방향으로 절취한 도면이다. 이하, 자세한 설명을 위해 두 방향에서의 공정 단면도를 함께 보여준다.2A to 2F are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to an exemplary embodiment of the present invention. The left side of the figure is a diagram cut in the direction crossing the bit line pattern, and the right side is a figure cut in the direction parallel to the bit line pattern. Hereinafter, the cross-sectional views of the process in two directions are shown together for detailed description.

도 2a에 도시된 바와 같이, 기판(31) 상에 게이트패턴(32)을 형성한다. 여기서, 기판(31)은 DRAM공정이 진행되는 반도체 기판일 수 있고, 게이트패턴(32)은 폴리실리콘전극(32A), 금속계전극(32B) 및 게이트하드마스크(32C)의 적층구조일 수 있다. 이때, 금속계전극(32B)은 금속 또는 금속실리사이드일 수 있고 금속은 텅스텐(Ｗ), 금속실리사이드는 텅스텐실리사이드(ＷSix)일 수 있다. 또한, 게이트하드마스크(32C)는 질화막일 수 있다.As shown in FIG. 2A, a gate pattern 32 is formed on the substrate 31. Here, the substrate 31 may be a semiconductor substrate in which a DRAM process is performed, and the gate pattern 32 may be a stacked structure of a polysilicon electrode 32A, a metal-based electrode 32B, and a gate hard mask 32C. In this case, the metal-based electrode 32B may be a metal or metal silicide, the metal may be tungsten, and the metal silicide may be tungsten silicide (Xix). In addition, the gate hard mask 32C may be a nitride film.

이어서, 게이트패턴(32)의 측벽에 측벽보호막(33)을 형성한다. 여기서, 측벽보호막(33)은 질화막일 수 있다.Subsequently, a sidewall protective film 33 is formed on the sidewall of the gate pattern 32. Here, the sidewall protection layer 33 may be a nitride film.

이어서, 게이트패턴(32) 사이를 채우도록 제1절연층(34)을 형성한다. 여기서, 제1절연층(34)은 게이트패턴(32) 사이의 절연을 위한 것으로, 게이트패턴(32) 사이를 채울때까지 산화막을 형성한 후, 게이트하드마스크(32C)를 타겟으로 평탄화하여 형성할 수 있다. Subsequently, the first insulating layer 34 is formed to fill the gap between the gate patterns 32. Here, the first insulating layer 34 is to insulate between the gate patterns 32. The first insulating layer 34 is formed by forming an oxide film until the gate patterns 32 are filled, and then planarizing the gate hard mask 32C as a target. can do.

이어서, 게이트패턴(32) 사이의 제1절연층(34)을 식각하여 랜딩 플러그 콘택홀(Landing Plug Contact Hole)을 형성한다. Next, the first insulating layer 34 between the gate patterns 32 is etched to form a landing plug contact hole.

이어서, 랜딩 플러그 콘택홀에 도전물질을 매립한 후 평탄화하여 랜딩 플러그 콘택(35, Landing Plug Contact)을 형성한다. 여기서, 도전물질은 폴리실리콘일 수 있고, 평탄화는 화학적기계적연마(Chemical Mechanical Polishing) 또는 에치 백(Etch back)으로 진행할 수 있다.Subsequently, the conductive material is embedded in the landing plug contact hole and then planarized to form a landing plug contact 35. Here, the conductive material may be polysilicon, and the planarization may be performed by chemical mechanical polishing or etch back.

이어서, 랜딩 플러그 콘택(35)을 포함하는 결과물의 전면에 제2절연층(34)을 형성한다. 여기서, 제2절연층(36)은 게이트패턴(32)과 후속 비트라인패턴 간의 층간절연을 위한 것으로, 산화막으로 형성할 수 있다.Next, the second insulating layer 34 is formed on the entire surface of the resultant product including the landing plug contact 35. Here, the second insulating layer 36 is for interlayer insulation between the gate pattern 32 and the subsequent bit line pattern, and may be formed of an oxide film.

이어서, 제2절연층(36) 상에 비트라인패턴(37)을 형성한다. 여기서, 비트라인패턴(37)은 폴리실리콘전극(37A), 금속계전극(37B) 및 비트라인하드마스크(37C)의 적층구조일 수 있다. 이때, 금속계전극(37B)은 금속 또는 금속실리사이드일 수 있고 금속은 텅스텐(Ｗ), 금속실리사이드는 텅스텐실리사이드(ＷSix)일 수 있다. 또한, 비트라인하드마스크(37C)는 질화막일 수 있다.Subsequently, a bit line pattern 37 is formed on the second insulating layer 36. The bit line pattern 37 may have a stacked structure of the polysilicon electrode 37A, the metal-based electrode 37B, and the bit line hard mask 37C. In this case, the metal-based electrode 37B may be a metal or metal silicide, the metal may be tungsten, and the metal silicide may be tungsten silicide (Xix). In addition, the bit line hard mask 37C may be a nitride film.

이어서, 비트라인패턴(37)의 측벽에 측벽보호막(38)을 형성할 수 있다. 이때, 측벽보호막(38)은 질화막일 수 있다.Subsequently, the sidewall protection layer 38 may be formed on the sidewall of the bit line pattern 37. In this case, the sidewall protection film 38 may be a nitride film.

이어서, 비트라인패턴(37) 사이를 모두 채우도록 제3절연층(39)을 형성한다. 여기서, 제3절연층(39)은 비트라인패턴(37) 사이의 절연을 위한 것으로, 비트라인패턴(37) 사이를 채울때까지 산화막을 형성한 후, 비트라인하드마스크(37C)를 타겟으로 평탄화하여 형성할 수 있다. 특히, 산화막은 HDP(High Density Plasma) 산화막일 수 있다.Subsequently, the third insulating layer 39 is formed to fill all of the bit line patterns 37. Here, the third insulating layer 39 is for insulation between the bit line patterns 37. After forming the oxide film until filling the bit line patterns 37, the third insulating layer 39 targets the bit line hard mask 37C. It can be formed by planarization. In particular, the oxide film may be an HDP (High Density Plasma) oxide film.

이어서, 제3절연층(39) 상에 마스크패턴(40)을 형성한다. 마스크패턴(40)은 스토리지 노드 콘택홀(Storage Node Contact Hole) 형성지역을 오픈시키기 위한 것으로, 특히 라인타입(Line Type)으로 형성할 수 있다.Subsequently, a mask pattern 40 is formed on the third insulating layer 39. The mask pattern 40 is to open a storage node contact hole forming area, and may be formed in a line type.

도 2b에 도시된 바와 같이, 마스크패턴(40)을 식각배리어로 제3 및 제2절연 층(39, 36)을 식각하여 스토리지 노드 콘택홀(41)을 형성한다. 이때, 제3 및 제2절연층(39, 36)을 한번에 식각하기 때문에 폴리머(Polymer)의 생성정도를 증가시킴으로써 종래 기술에서 이차 건식식각시 초기 식각되어야 할 막의 부족으로 인해 발생하는 자기정렬콘택 특성 약화를 방지할 수 있다. 즉, 이차 건식식각시 폴리머 부족으로 인해 비트라인하드마스크(37C)가 어택을 받아 손실되는 것을 방지할 수 있다.As illustrated in FIG. 2B, the third and second insulating layers 39 and 36 are etched using the mask pattern 40 as an etch barrier to form the storage node contact holes 41. At this time, since the third and second insulating layers 39 and 36 are etched at one time, the degree of generation of polymers is increased, so that the self-aligned contact characteristics caused by the lack of a film to be initially etched during the secondary dry etching in the prior art. Weakening can be prevented. That is, it is possible to prevent the bit line hard mask 37C from being attacked and lost due to the lack of polymer during the secondary dry etching.

이를 위해, 제3 및 제2절연층(39, 36)은 CF계 가스를 메인가스로 사용하고 산소 및 아르곤(Ar) 가스를 첨가하여 실시하는데, CF계 가스는 C4F6 또는 C4F8일 수 있다.To this end, the third and second insulating layers 39 and 36 are formed by using CF gas as the main gas and adding oxygen and argon (Ar) gas. The CF gas is C 4 F 6 or C 4 F Can be eight .

마스크패턴(40)이 라인타입으로 형성되었기 때문에 비트라인패턴과 교차하는 방향으로 절취한 좌측 단면도에서는 제3절연층(39)이 모두 식각되어 도시되지 않는다.Since the mask pattern 40 is formed in a line type, all of the third insulating layers 39 are not etched in the left cross-sectional view cut along the bit line pattern.

이어서, 도 2c에 도시된 바와 같이, 스토리지 노드 콘택홀(41)에 제3절연층(39)의 표면보다 낮은 높이로 보호막(42)을 매립한다. 여기서, 보호막(42)은 후속 습식식각에 의해 스토리지 노드 콘택홀(41) 하부가 손상되는 것을 방지하기 위한 것으로, 산화막과 선택비를 갖는 유동성이 좋은 물질로 형성하되 바람직하게는 감광막(Photoresist)으로 형성할 수 있다.Subsequently, as shown in FIG. 2C, the protective layer 42 is buried in the storage node contact hole 41 at a height lower than the surface of the third insulating layer 39. Here, the protective layer 42 is to prevent the lower portion of the storage node contact hole 41 from being damaged by subsequent wet etching. The protective layer 42 is formed of a material having good fluidity having an oxide film and a selectivity, but preferably a photoresist. Can be formed.

도 2d에 도시된 바와 같이, 등방성식각(200)을 실시하여 스토리지 노드 콘택홀(41)의 상부폭을 넓힌다. 여기서, 등방성식각은 습식식각으로 실시할 수 있고, 습식식각은 산화막과 질화막 및 감광막과의 식각선택비를 갖는 물질로 실시하되 바 람직하게는 BOE(Buffered Oxide Etchant) 또는 HF를 사용하여 실시할 수 있다.As shown in FIG. 2D, an isotropic etching 200 is performed to widen the upper width of the storage node contact hole 41. Here, the isotropic etching may be performed by wet etching, and the wet etching may be performed using a material having an etching selectivity ratio between the oxide film, the nitride film, and the photoresist film. have.

습식식각으로 스토리지 노드 콘택홀(41)의 상부폭을 넓히는 공정에서 스토리지 노드 콘택홀(41) 하부는 보호막(42)이 채우고 있기 때문에 손상을 받지 않는다. 또한, BOE 또는 HF가 질화막과 식각선택비를 갖기 때문에 질화막질의 비트라인하드마스크(37C) 및 비트라인측벽보호막(38)은 손상되지 않는다.In the process of expanding the upper width of the storage node contact hole 41 by wet etching, the lower portion of the storage node contact hole 41 is not damaged because the protective layer 42 fills the lower portion. In addition, since the BOE or HF has an etching selectivity with the nitride film, the bit line hard mask 37C and the bit line side wall protective film 38 of the nitride film quality are not damaged.

따라서, 상부폭이 넓은 스토리지 노드 콘택홀(41A)이 형성된다.Thus, the storage node contact hole 41A having a wide upper portion is formed.

도 2e에 도시된 바와 같이, 보호막(42)을 제거한다. 보호막(42)이 감광막일 경우 산소스트립으로 제거할 수 있다.As shown in FIG. 2E, the protective film 42 is removed. When the protective film 42 is a photosensitive film, the protective film 42 may be removed by an oxygen strip.

이어서, 스토리지 노드 콘택홀(41)을 모두 채울때까지 도전물질(43)을 형성한다. 여기서, 도전물질(43)은 폴리실리콘일 수 있다.Next, the conductive material 43 is formed until all the storage node contact holes 41 are filled. Here, the conductive material 43 may be polysilicon.

도 2f에 도시된 바와 같이, 도전물질(43)에 평탄화를 실시하여 스토리지 노드 콘택홀(41) 내부에 잔류하는 스토리지 노드 콘택 플러그(43A)를 형성한다. 평탄화는 마스크패턴(41)이 모두 제거되도록 비트라인하드마스크(37A)가 드러나는 타겟으로 실시할 수 있다.As illustrated in FIG. 2F, the conductive material 43 is planarized to form the storage node contact plug 43A remaining inside the storage node contact hole 41. The planarization may be performed with a target in which the bit line hard mask 37A is exposed so that the mask pattern 41 is completely removed.

따라서, 상부폭이 넓은 스토리지 노드 콘택 플러그(43A)를 형성함으로써 후속 스토리지 노드와의 접촉 면적 마진을 향상시킬 수 있다.Therefore, by forming the upper storage node contact plug 43A having a wider width, the contact area margin with subsequent storage nodes can be improved.

본 발명은 제3 및 제2절연층(39, 36)을 한번의 식각으로 스토리지 노드 콘택홀(41)을 형성한 후, 보호막(42)을 형성하고 등방성 습식식각으로 스토리지 노드 콘택홀(41A)의 상부폭을 증가시킴으로써 비트라인하드마스크(37C)의 손상을 방지하 면서 동시에 후속 스토리지 노드와의 접촉 면적 마진을 향상시킬 수 있는 장점이 있다.In the present invention, after the storage node contact holes 41 are formed by etching the third and second insulating layers 39 and 36 once, the protective layer 42 is formed and the storage node contact holes 41A are formed by isotropic wet etching. By increasing the upper width of the bit line hard mask (37C) to prevent damage while at the same time has the advantage of improving the contact area margin with subsequent storage nodes.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상기한 본 발명에 의한 반도체 소자의 콘택 플러그 제조방법은 비트라인하드마스크의 어택을 방지하면서 후속 스토리지 노드와의 접촉 면적 마진을 향상시켜 신뢰성 있는 소자를 형성할 수 있는 효과가 있다.The method of manufacturing a contact plug of a semiconductor device according to the present invention has an effect of forming a reliable device by preventing a bit line hard mask attack and improving a contact area margin with a subsequent storage node.

Claims (11)

기판 상부에 절연층을 형성하는 단계;Forming an insulating layer on the substrate; 상기 절연층을 식각하여 콘택홀을 형성하는 단계;Etching the insulating layer to form a contact hole; 상기 콘택홀에 상기 절연층의 표면보다 낮은 높이로 보호막을 매립하는 단계;Embedding a protective film in the contact hole at a height lower than a surface of the insulating layer; 등방성식각으로 상기 콘택홀의 상부폭을 넓히는 단계; 및Widening the upper width of the contact hole by isotropic etching; And 상기 보호막을 제거하는 단계Removing the protective film 를 포함하는 반도체 소자의 콘택 플러그 제조방법.Contact plug manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 절연층은 산화막인 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The insulating layer is a contact plug manufacturing method of a semiconductor device, characterized in that the oxide film. 제2항에 있어서,The method of claim 2, 상기 콘택홀을 형성하는 단계는,Forming the contact hole, CF계 가스를 메인가스로 사용하고 산소 및 아르곤(Ar) 가스를 첨가하여 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.A method of manufacturing a contact plug for a semiconductor device comprising using a CF gas as a main gas and adding oxygen and argon (Ar) gas. 제3항에 있어서,The method of claim 3, 상기 CF계 가스는 C4F6 또는 C4F8인 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The CF-based gas is a C 4 F 6 or C 4 F 8 Contact plug manufacturing method of a semiconductor device, characterized in that. 제1항에 있어서,The method of claim 1, 상기 보호막은 감광막인 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The protective film is a contact plug manufacturing method of a semiconductor device, characterized in that the photosensitive film. 제1항에 있어서,The method of claim 1, 상기 등방성식각은 습식식각으로 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The isotropic etching is a contact plug manufacturing method of a semiconductor device, characterized in that the wet etching. 제1항에 있어서,The method of claim 1, 상기 습식식각은 BOE(Buffered Oxide Etchant) 또는 HF를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The wet etching method of manufacturing a contact plug of a semiconductor device, characterized in that performed using BOE (Buffered Oxide Etchant) or HF. 제5항에 있어서,The method of claim 5, 상기 보호막을 제거하는 단계는,Removing the protective film, 산소스트립으로 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The method of manufacturing a contact plug of a semiconductor device, characterized in that the oxygen strip. 제1항에 있어서,The method of claim 1, 상기 보호막을 제거하는 단계 후,After removing the protective film, 상기 콘택홀을 모두 매립하도록 도전물질을 형성하는 단계; 및Forming a conductive material to fill all of the contact holes; And 평탄화를 실시하여 상기 도전물질을 콘택홀 내부에 잔류시키는 단계Planarization to leave the conductive material inside the contact hole 를 포함하는 반도체 소자의 콘택 플러그 제조방법.Contact plug manufacturing method of a semiconductor device comprising a. 제9항에 있어서,The method of claim 9, 상기 도전물질은 폴리실리콘인 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The conductive material is a contact plug manufacturing method of a semiconductor device, characterized in that the polysilicon. 제9항에 있어서,The method of claim 9, 상기 평탄화는 에치백 또는 화학적기계적연마(Chemical Mechanical Polishing)으로 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 제조방법.The planarization is a method of manufacturing a contact plug of a semiconductor device, characterized in that performed by etch back or chemical mechanical polishing (Chemical Mechanical Polishing).
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113707663A (en) * 2021-08-26 2021-11-26 长江存储科技有限责任公司 Semiconductor structure, three-dimensional memory and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113707663A (en) * 2021-08-26 2021-11-26 长江存储科技有限责任公司 Semiconductor structure, three-dimensional memory and preparation method thereof
CN113707663B (en) * 2021-08-26 2024-04-05 长江存储科技有限责任公司 Semiconductor structure, three-dimensional memory and preparation method thereof

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