KR20110000203A - Method of fabricating semiconductor device having recess gate - Google Patents

Method of fabricating semiconductor device having recess gate Download PDF

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Publication number
KR20110000203A
KR20110000203A KR1020090057599A KR20090057599A KR20110000203A KR 20110000203 A KR20110000203 A KR 20110000203A KR 1020090057599 A KR1020090057599 A KR 1020090057599A KR 20090057599 A KR20090057599 A KR 20090057599A KR 20110000203 A KR20110000203 A KR 20110000203A
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South Korea
Prior art keywords
pattern
sidewall
gate
forming
recess
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KR1020090057599A
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Korean (ko)
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유재선
이강복
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주식회사 하이닉스반도체
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Priority to KR1020090057599A priority Critical patent/KR20110000203A/en
Publication of KR20110000203A publication Critical patent/KR20110000203A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A manufacturing method of a semiconductor device having a recess gate is provided to prevent the occurrence of bowing profile on a side wall of a second recess pattern by distinguishing the second recess pattern formed on a component partitioning layer into first and second patterns. CONSTITUTION: An element isolation film(105) is formed on a substrate(100). A recess pattern(107) is formed on the element isolation film. A sidewall of a gate(113) contacts the sloped sidewall of the recess pattern. A gate spacer(114) is formed on both side walls of the gate. The gate spacer fills the space between the sidewall of the recess pattern and the sidewall of the gate.

Description

A method of manufacturing a semiconductor device having a recess gate {METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING RECESS GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device. In particular, a short defect occurs between a landing plug and a gate electrode in a semiconductor device having a recess gate (RG). The present invention relates to a semiconductor device and a method for manufacturing the same, which can be prevented.

As the integration degree of the semiconductor device increases, the channel area becomes smaller and the impurity doping concentration of the impurity regions (for example, the channel region, the source and drain regions, etc.) increases. As a result, it is difficult to secure characteristics required by a highly integrated semiconductor device with a conventional Planar Gate (PG).

Therefore, recently, a recess gate (RG) has been introduced and applied to secure characteristics required by highly integrated semiconductor devices. The recess gate has an advantage of increasing the channel area and reducing the doping concentration of the impurity region by recessing the substrate under the gate to form a channel in three dimensions. The recess gate structure includes a polygon, a bulb type, a fin type, and a saddle-fin type. Among the above-described recess gate structures, the characteristics of the saddle fin type recess gate structure are different. It is known to be the best.

1A and 1B are diagrams illustrating a semiconductor device having a saddle fin-type recess gate according to the prior art, and FIGS. 2A and 2B are images illustrating problems according to the prior art. Here, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A.

Referring to FIGS. 1A and 1B, a method of fabricating a semiconductor device having a saddle fin recess gate according to the related art may be performed by selectively selecting a substrate 11 having an active region 13 defined by an isolation layer 12. By etching, a saddle pin pattern 14 crossing the device isolation layer 12 and the active region 13 at the same time is formed. In this case, the saddle pin pattern 14 is formed on the first recess pattern 14A and the device isolation layer 12 formed in the active region 13 and exposes the bottom and bottom sidewalls of the first recess pattern 14A. It includes two recess patterns 14B.

Next, after performing the first cleaning process to remove the by-products (or residues) generated in the process of forming the saddle pin pattern 14, the saddle pin pattern 14 is buried and a part protrudes onto the substrate 11 Formed gate 18. In this case, the gate 18 is a stacked structure in which the gate insulating film 15, the gate electrode 16, and the gate hard mask film 17 are sequentially stacked.

Next, after the gate spacers 19 are formed on both side walls of the gate 18, an interlayer insulating layer 21 is formed to fill the gates 18, and then self-aligned contact etching is performed to contact holes for landing plugs. (Not shown) is formed.

Next, after the second cleaning process for removing the by-products (or residues) generated in the contact hole forming process, the landing material 20 is embedded by filling a conductive material in the contact hole. In this case, the landing plug 20 includes a hole type first plug 20A in contact with both edges of the active region 13 and a second plug 20B in contact with the center of the active region 13. The second plug 20B has a form of a line type extending from the active region 13 to the device isolation layer 12 in order to improve contact characteristics with the bit lines to be formed through subsequent processes.

However, in the related art, as shown by reference numeral 'A', the line width of the second recess pattern 14B formed in the device isolation film 12 is increased while the device isolation film 12 is partially lost during the first cleaning process, or the gate ( 18) There is a problem in that the misalignment occurs during formation, and the gate electrode 16 passing through the device isolation layer 12 is exposed when the contact hole forming process is completed. In addition, as shown by reference numeral 'B', the device isolation layer 12 is partially buried under the contact hole for the second plug 20B during the contact hole forming process and the second cleaning process, and thus the second recess pattern 14B is embedded in the second recess pattern 14B. There is a problem that the gate electrode 16 is exposed. For this reason, there is a problem that a short circuit defect occurs between the gate electrode 16 and the landing plug (see reference numeral 'C' in FIG. 2B).

The problem described above is that since the device isolation layer 12 and the interlayer insulating layer 21 are made of the same series of materials, that is, oxide-based materials, the etching selectivity between them is low during the contact hole forming process, and the primary and secondary cleaning processes are performed. Occurs because it is carried out using a cleaning solution having an oxide etching property such as hydrofluoric acid solution (HF) or buffered oxide etchant (BOE) solution. In addition, as shown in FIG. 2A, in order to form the saddle fin type recess gate, an etching depth (or height) of the second recess pattern 14B formed in the device isolation layer 12 is greater than that of the first recess pattern 14A. Since it must be larger than the etching depth, a boeing profile is formed on the upper sidewall of the second recess pattern 14B having the high aspect ratio, and the gate electrode 16 embedded in the second plug 20B and the second recess pattern 14B is formed. It occurs because the physical distance between them decreases.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and a semiconductor device capable of preventing short circuit defects between a landing plug and a gate electrode in a semiconductor device having a recess gate and a manufacturing method thereof. The purpose is to provide.

According to one aspect of the present invention, a semiconductor device includes a substrate having an isolation layer; A recess pattern formed in the device isolation layer and having a sidewall partially inclined; A plurality of gates whose sidewalls contact the inclined sidewalls of the recess pattern; A gate spacer formed on both sidewalls of the gate and filling a space between the sidewall of the recess pattern and the gate sidewall; And a plug filling the gap between the gates.

According to another aspect of the present invention, a semiconductor device includes: a substrate in which an active region is defined by an isolation layer; A first recess pattern having a substrate formed in the active region and having a vertical sidewall; A second recess pattern formed on the device isolation layer and having a portion of the sidewall inclined; A plurality of gates crossing the device isolation layer and the active region at the same time and having a sidewall contacting the inclined sidewall of the second recess pattern; A gate spacer formed on both sidewalls of the gate and filling a space between the inclined sidewall of the second recess pattern and the gate sidewall; And a landing plug to fill the gap between the gates.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a device isolation film including a laminated film in which first, second, and third insulating films are sequentially stacked on a substrate; Selectively etching the device isolation layer to form a recess pattern in which a portion of the sidewall is inclined; Forming a plurality of gates such that sidewalls contact the inclined sidewalls of the recess pattern; Forming gate spacers on both sides of the gate to fill a space between the inclined sidewall of the recess pattern and the gate sidewall; And forming a plug to fill the gap between the gates.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an isolation region formed of a laminated film in which first, second, and third insulating films are stacked on a substrate to define an active region; Selectively etching the substrate to form a first recess pattern having a vertical sidewall on the substrate of the active region, and forming a second recess pattern having a portion of the sidewall inclined on the device isolation layer; Forming a plurality of gates so as to cross the device isolation layer and the active region at the same time and the sidewalls contact the inclined sidewalls of the second recess pattern; Forming a gate spacer on both sidewalls of the gate to fill a space between the gate sidewall and an inclined sidewall of the second recess pattern; And forming a landing plug between the gate patterns.

The semiconductor device of the present invention based on the above-described problem solving means has a structure in which the gate sidewall is in contact with the sidewall of the first pattern formed in the device isolation film, and the gate spacer is embedded in the space between the sidewalls. There is an effect that can prevent the occurrence of short-circuit defect between the gate electrode.

In addition, according to the present invention, by forming the second recess pattern formed on the device isolation layer by dividing the first and second patterns, a bowing profile of the sidewalls of the second recess pattern may be prevented. In addition, since the sidewall of the first pattern has a negative slope, it is possible to more effectively prevent the generation of the bowing profile of the sidewall of the second recess pattern. As a result, the present invention has an effect of more effectively preventing the occurrence of short-circuit defects between the landing plug and the gate electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention, which will be described later, provides a semiconductor device capable of preventing short circuit defects between a landing plug and a gate electrode in a semiconductor device having a recess gate and a method of manufacturing the same. The recess gate structure includes a polygon, a bulb type, a fin type, and a saddle-fin type. Among the above-described recess gate structures, the most characteristic of the saddle fin type recess gate is shown. As is known to be excellent, embodiments of the present invention are described below by illustrating a semiconductor device having a saddle fin-type recess gate. This does not mean that the technical principle of the present invention is limited to the saddle fin type recess gate, and the technical principle of the present invention is that a recess pattern for the recess gate is formed in the device isolation layer and the landing plug is separated from the active region. It can be applied to all semiconductor devices having a line type extended to.

3A and 3B illustrate a semiconductor device having a recess gate according to a first embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is along the line X-X 'shown in FIG. 3A. It is sectional drawing.

As shown in FIGS. 3A and 3B, the semiconductor device of the present invention is activated by an isolation layer 105 formed of a laminated film in which first, second and third insulating films 102, 103, and 104 are sequentially stacked. A saddle pin pattern 200 and a saddle pin pattern 200 that simultaneously cross the device isolation layer 105 and the active region 101 are buried in the substrate 100 where the region 101 is defined, and a portion of the region is buried above the substrate 100. The first plug 116A and the active region 101 of the hole type formed on both side edges of the protruding gate 113, the gate spacer 114 formed on both side walls of the gate 113, and the active region 101. ) And a landing plug 116 formed of a line type second plug 116B extending on the center of the active region 101 and extending from the active region 101 to the device isolation layer 105.

The first insulating layer 102 of the device isolation layer 105 has a structure to partially fill the trench 117 for device isolation, and the third and second insulating layers 104 do not fill the first and second insulating layers 102 and 103. The remaining trench 117 is embedded. In this case, the first and third insulating layers 102 and 104 may be formed of a material of the same series, for example, an oxide layer. Specifically, the first insulating layer 102 may be a spin on dielectric (SOD) having excellent buried characteristics, and the third insulating layer 104 may have a high density plasma oxide (High Density) having excellent physical properties (especially strength). Plasma oxide, HDP).

The second insulating layer 103 of the device isolation layer 105 is used to form a second recess pattern 109 having a 'Y' shape in the device isolation layer 105, and as an etch stop layer between processes. Works. The second insulating layer 103 may be formed of a material having an etching selectivity with respect to the first and third insulating layers 102 and 104-an oxide layer, for example, a nitride layer. In detail, the second insulating layer 103 may be a silicon nitride layer (Si 3 N 4 ).

The saddle pin pattern 200 is formed in the first recess pattern 107 and the device isolation layer 105 formed on the substrate 100 of the active region 101 to have a 'Y' shape and the first recess pattern 107. And a second recess pattern 109 exposing the bottom and bottom sidewalls. In this case, the second recess pattern 109 may have a form in which the sidewalls are partially inclined. In detail, the second recess pattern 109 includes a first pattern 106 having an inclined sidewall and a second pattern 108 having a vertical sidewall under the first pattern 106.

The first recess pattern 107 is preferably formed such that the sidewall has a vertical profile in order to secure the maximum contact area between the junction region, that is, the source and drain region (not shown) and the landing plug 116. Do. In addition, the first recess pattern 107 may be formed to have a depth (or height) greater than that of the first pattern 106 with respect to the upper surface of the substrate 100. This is to secure the channel area required by the highly integrated semiconductor device.

In addition, the line width W2 of the first recess pattern 106 may be equal to the bottom line widths Bottom CD and W1 of the first pattern 106 of the second recess pattern 109 (W1 = W2). The second pattern 108 of the second recess pattern 109 may be the same as the line width W3 (W2 = W3) or smaller (W2 <W3).

The inclined sidewalls of the first pattern 106 constituting the second recess pattern 109 may have a negative slope. At this time, the first pattern 106 inclined so that the sidewall has a negative slope means that the line width of the pattern decreases from the upper region to the lower region. Therefore, the top line widths Top CD and W4 of the first pattern 106 are larger than the bottom line width W1 (W4> W1).

Since the sidewalls of the second pattern 108 of the second recess pattern 109 have a vertical profile, the bottom line width W1 of the first pattern 106 and the line width W3 of the second pattern 108 are mutually different. The line width W3 of the second pattern 108 may be larger (W1 <W3) or may be the same (W1 = W3), or due to inter-process losses (eg, between cleaning processes).

The gate 113 fills the gate insulating layer 110 and the saddle pin pattern 200 formed on the surface of the substrate 100 in the active region 101 and partially gates the gate electrode 111 and the gate hard over the substrate 100. The mask layer 112 may be a laminate structure in which the mask layers 112 are sequentially stacked.

Here, the present invention is formed so that the side wall of the gate 113 is in contact with the inclined side wall of the first pattern 106 in order to prevent the short-circuit defect between the landing plug 116 and the gate electrode 111. It is done. As the sidewall of the gate 113 contacts the sidewall of the first pattern 106, an insulating film, for example, the spacer 114, is formed in the space between the sidewall of the gate 113 and the sidewall of the first pattern 106 (see reference numeral 'D'). The gap between the landing plug 116 and the gate electrode 111 can be prevented from occurring. At this time, the line width of the gate 113 to provide a space between the sidewall of the gate 113 and the sidewall of the first pattern 106 to prevent short circuit between the landing plug 116 and the gate electrode 111. W5) is preferably smaller than the top line width W4 and larger than the bottom line width W1 of the first pattern 106 of the second recess pattern 109 (W1 <W5 <W4).

The gate spacer 114 formed on both sidewalls of the gate 113 may be formed on both sidewalls of the gate 113 and fill a space between the sidewall of the gate 113 and the sidewall of the first pattern 106. Accordingly, the gate spacer 114 serves to protect the inter-process gate 113 and also serves as a short prevention film for preventing occurrence of short-circuit defects between the landing plug 116 and the gate electrode 111. For this purpose, the gate spacer 114 may be formed of a material having an etch selectivity with respect to the third insulating layer 104-oxide layer and the interlayer insulating layer 115-oxide layer of the device isolation layer 105, for example, a nitride layer. In detail, the gate spacer 114 may be a silicon nitride film.

As described above, the present invention has a structure in which the sidewall of the gate 113 is in contact with the sidewall of the first pattern 106 formed in the device isolation film 105, and the gate spacer 114 fills the space between the sidewalls. The gate electrode embedded in the plug 116, in particular, the second plug 116B of the line type extending from the active region 101 to the device isolation film 105 and the second recess pattern 109 of the device isolation film 105. It is possible to prevent the occurrence of short defects between the 111).

In addition, according to the present invention, the first pattern 106 having the inclined sidewalls may be prevented, and thus, the landing plug 116 may be prevented from being formed on the sidewalls during the process of forming the second recess pattern 109. And short circuit defect between the gate electrode 111 can be prevented more effectively.

Hereinafter, a method of manufacturing a semiconductor device having a structure according to the first embodiment described above will be described in detail with reference to FIGS. 4A to 4G.

4A through 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with a second embodiment of the present invention, taken along the line X-X 'of FIG. 3A.

As shown in FIG. 4A, after the first hard mask pattern 42 is formed on the substrate 41, for example, the silicon substrate, device isolation may be performed using the first hard mask pattern 42 as an etch barrier. To form a trench 43. In this case, the first hard mask pattern 42 may be formed as a laminated film in which a pad oxide film and a pad nitride film are stacked.

Next, after the formation of a wall oxide (Wall Oxide) (not shown), a liner nitride (Liner Nitride, not shown) and a liner oxide (Liner Oxide) on the surface of the trench 43 in order to partially fill the trench 43 The first insulating film 44 is formed. The first insulating layer 44 may be formed of an oxide layer, and the first insulating layer 44 may be formed of a spin on dielectric film (SOD) having excellent buried characteristics to facilitate application to highly integrated semiconductor devices. .

The first insulating layer 44 which partially fills the trench 43 has a first insulating layer 44 formed on the entire surface of the substrate 41 to sufficiently fill the trench 43, and then the upper portion of the first hard mask pattern 42. After the planarization process is performed under the condition that the surface is exposed, the first insulating layer 44 may be formed through a series of processes of recessing a predetermined thickness. In this case, the planarization process may be performed using chemical mechanical polishing (CMP). The recess process may be performed using a wet etch, and the wet etching may be performed using a hydrofluoric acid solution (HF) or a buffered oxide etchant (BOE) solution.

Next, a second insulating layer 45 is formed along the surface of the structure including the first insulating layer 44. The second insulating layer 45 serves as an etch stop layer in the process of forming the first pattern of the second recess pattern in which the portion of the sidewall to be formed in the subsequent device isolation layer is inclined. Therefore, the second insulating layer 45 may be formed to have a thickness in the range of 20 kV to 300 kV so as to act as an adequate etch stop layer during the process.

In addition, the second insulating layer 45 may be formed of a material having a high etching selectivity with respect to an etchant (that is, an etching gas or an etching solution) for etching the first insulating layer 44 and the third insulating layer to be formed through a subsequent process. It is preferable to form. Therefore, the second insulating film 45 is preferably formed of a nitride film, and a silicon nitride film (Si 3 N 4 ) may be used as the nitride film.

As shown in FIG. 4B, a third insulating layer 46 is formed on the second insulating layer 45 to fill the remaining trench 43. The third insulating layer 46 may be formed of the same series of materials as that of the first insulating layer 44, for example, an oxide layer, and may have excellent film quality (especially strength) in order to minimize loss of the third insulating layer 46 during subsequent processes. It is preferable to form the third insulating film 46 with a high density plasma oxide film (HDP).

In the third insulating layer 46 filling the remaining trench 43, the third insulating layer 46 is formed on the entire surface of the substrate 41 to sufficiently fill the trench 43, and then the upper surface of the substrate 41 is exposed. Can be formed through a series of processes to perform the planarization process with a gun. In this case, the planarization process may be performed using chemical mechanical polishing (CMP).

Through the above-described process, the device isolation layer 47 having a structure in which the first, second, and third insulating layers 44, 45, and 46 are sequentially stacked may be formed. In this case, a region in which the device isolation layer 47 is not formed on the substrate 41 may be defined as the active region 48.

As shown in FIG. 4C, a second hard mask pattern 49 is formed on the substrate 41 on which the active region 48 is defined by the device isolation layer 47. In this case, the second hard mask pattern 49 may be formed as a laminated film in which an amorphous carbon layer (ACL) and a silicon oxynitride layer (SiON) are stacked. Here, the line widths of the openings 49A of the second hard mask pattern 49 are all the same. That is, the line width of the opening 49A of the second hard mask pattern 49 formed on the device isolation layer 47 and the line width of the opening 49A of the second hard mask pattern 49 formed on the active region 48 are the same. Do.

Next, the third insulating layer 46 of the device isolation layer 47 is etched using the second hard mask pattern 49 as an etch barrier to form a first pattern 50 having inclined sidewalls. At this time, the sidewall of the first pattern 50 is preferably formed to have a negative slope. Here, the first pattern 50 having the negative slope of the sidewalls means that the line width of the pattern decreases from the upper region to the lower region.

The process of forming the first pattern 50 may be performed by using a dry etch method. In order to selectively etch only the third insulating layer 46 of the device isolation layer 47, the substrate 41, the silicon substrate, and the like may be removed. Etch gas having a faster etching rate with respect to the third insulating layer 46 -oxide- of the device isolation film 47 than the etching rate with respect to the etching rate, for example, carbon fluoride gas (CxFy, x, y is a natural number except 0) can do. Therefore, in the process of forming the first pattern 50, the second insulating layer 45 of the device isolation layer 47 including the third insulating layer 46-an oxide layer-and a nitride layer having an etching selectivity acts as an etch stop layer. In the process of forming the pattern 50, the second and first insulating layers 45 and 44 are not etched.

Here, in order to form the sidewall of the first pattern 50 to have a negative inclination, the etching conditions in which the etching speed in the vertical direction is faster than the etching speed in the horizontal direction relative to the upper surface of the substrate 41 may be used. It is preferable to form one pattern 50. For example, as the bias power applied to the chamber is reduced, the etching speed in the vertical direction is increased rather than the horizontal direction, thereby forming the first pattern 50 having the negative sidewall.

Next, the active region 48 of the substrate 41 is etched using the second hard mask pattern 49 as an etch barrier to form a first recess pattern 51 having vertical sidewalls. In this case, the reason why the first recess pattern 51 is formed to have vertical sidewalls is to prevent a short circuit defect between the gate electrode and the landing plug to be buried in the first recess pattern 51 during the subsequent landing plug formation process. At the same time, the contact area between the junction regions (that is, the source and drain regions) and the landing plug to be formed on both substrates 41 of the first recess pattern 51 is secured to reduce the contact resistance therebetween.

The first recess pattern 51 may be formed using anisotropic dry etching to form sidewalls having a vertical profile, and the third insulating film 46 of the device isolation layer 47 may be formed of an oxide film. Etch gas having a faster etching rate with respect to the substrate 41-silicon substrate-than the etching rate with respect to the substrate 41, for example, chlorine gas (Cl 2 ), hydrogen bromide gas (HBr), boron trichloride gas (BCl 3 ) mixed gas It can be carried out using (Cl 2 / HBr / BCl 3 ). In this case, the first recess pattern 51 may be formed such that the etching depth of the first recess pattern 51 is similar to the etching depth of the first pattern 50 or the etching depths are the same by adjusting the etching time. Can be. This is to reduce the process burden applied to the pre-formed structure during the process of forming the first recess pattern 51, for example, to prevent the inclined sidewall profile of the pre-formed first pattern 50 from being damaged. In addition, to prevent the formation of a boeing profile on the sidewalls of the first recess pattern 51. In this case, since the depth (or height) of the first recess pattern 51 is increased through a subsequent process, Even if the depth of the first recess pattern 51 is formed to be similar to the depth of the first pattern 50, the channel area (especially the channel length) required by the semiconductor device can be sufficiently secured.

Meanwhile, in the above-described embodiment, after the first pattern 50 is formed in the device isolation layer 47, the process is performed in the order of forming the first recess pattern 51 in the active region 48. The first pattern 50 may be formed after first forming the recess pattern 51.

As shown in FIG. 4D, in the subsequent landing plug forming process, the first pattern 50 may be formed to secure a space in which an insulating film is buried to prevent a short circuit defect between the landing plug and the gate electrode formed on the device isolation layer 47. Increase line width At this time, even if the line width of the first pattern 50 increases, the sidewalls of the first pattern 50 still have a negative slope, and the bottom line width W1 and the first recess pattern 51 of the first pattern 50 are increased. Line widths W2 may be equal to each other. Hereinafter, the reference numeral of the first pattern 50 having the increased line width is changed to '50A' and described.

In order to increase the line width of the first pattern 50A while the sidewall of the first pattern 50A has a negative slope, it is preferable to increase the line width of the first pattern 50A by using an isotropic etching characteristic. Specifically, the etching process for increasing the line width of the first pattern 50A may be performed using any one method selected from the group consisting of wet etching, isotropic dry etching, and dry cleaning. At this time, even if the line width of the first pattern 50A is increased by etching the third insulating layer 46 -oxide- of the device isolation layer 47 by using the isotropic etching characteristic, the second insulating layer 45 of the device isolation layer 47 is formed. Since the nitride film acts as an etch stop film, the etching depth of the first pattern 50A does not increase.

Wet etching may be performed using hydrofluoric acid (HF) or BOE (Buffered Oxide Etchant) solutions. The isotropic dry etching method can be performed using carbon fluoride gas (C x F y , x, y are natural numbers except 0). In this case, the source power may be performed by applying only source power to the chamber, or the source power and the bias power may be simultaneously applied, but the low bias power of 1W to 100W may be used. The dry cleaning method may be performed by injecting a gas containing any one or more components selected from the group consisting of nitrogen (N), hydrogen (H), and fluorine (F) into the chamber in which the plasma is formed.

When the above-described process is completed, the top line widths Top CD and W4 of the first pattern 50A are larger than the line widths of the openings 49A of the second hard mask pattern 49, and preferably, It is preferable to form so that it may become larger than a line width. In addition, the bottom line widths Bottom CD and W1 of the first pattern 50A may be smaller than the line widths of the gates to be formed through subsequent processes. This is to form the sidewalls of the subsequent gates to be in contact with the inclined sidewalls of the first pattern 50A.

As shown in FIG. 4E, the substrate 41 of the active region 48 is etched using the second hard mask pattern 49 as an etch barrier, that is, the substrate 41 is added below the first recess pattern 51. By etching, the depth (or height) of the first recess pattern 51 is increased. This is to secure the channel area (especially the channel length) required by the highly integrated semiconductor device, and the depth of the first recess pattern 51 is preferably at least greater than the depth of the first pattern 50A. . Hereinafter, the reference numeral of the first recess pattern 51 having the increased depth is changed to '51A' and described.

An etching process for increasing the depth of the first recess pattern 51A may be performed using anisotropic dry etching to form the sidewall of the first recess pattern 51A to have a vertical profile. Etch gas faster than the etching rate for the separator 47-oxide film / nitride film / oxide film-for example, chlorine gas (Cl 2 ), hydrogen bromide gas (HBr), trichloride It can be carried out using a mixed gas (Cl 2 / HBr / BCl 3 ) mixed with boron gas (BCl 3 ).

Here, by forming the first recess pattern 51A through two etching processes, the depth of the first recess pattern 51A in order to secure the channel area (particularly, the channel length) required by the highly integrated semiconductor device is determined. Or increase the height) to minimize the formation of the bowing profile on the side wall.

Next, the second hard mask pattern 49 is sequentially etched to sequentially etch the second and first insulating layers 45 and 44 of the device isolation layer 47 under the first pattern 50A. A second pattern 52 exposing the bottom and bottom sides of 51A) is formed. In this case, the line width W3 of the second pattern 52 may be the same as the line width W2 of the first recess pattern 51A (W2 = W3).

The second pattern 52 exposes the bottom and bottom sides of the first recess pattern 51A of the active region 48, while maximizing the area of the bottom side of the exposed first recess pattern 51A. In order to control the area of the bottom side of the first recess pattern 51A exposed from the entire substrate 41 to be uniform, it is preferable to form the sidewalls to have a vertical profile. Therefore, the etching process for forming the second pattern 52 may be performed using an anisotropic dry etching method, and the etching rate with respect to the substrate 41-silicon substrate-to etch only the device isolation film 47. Etch gas having a faster etch acceleration with respect to the second and first insulating layers 45 and 44 -nitride layer / oxide layer- of the isolation layer 47, for example, carbon fluoride gas (C x F y , x, y are natural numbers except 0). ), Methane fluoride gas (C x H y F z , x, y, z is a natural water except 0), nitrogen trifluoride gas (NF 3 ), sulfur hexafluoride gas (SF 6 ) and chlorine gas (Cl 2 ) It can be carried out using a mixed gas mixture (C x F y / C x H y F z / NF 3 / SF 6 / Cl 2 ). In addition, in order to improve the etching characteristics in the above-described mixed gas selected from the group consisting of hydrogen gas (H 2 ), argon gas (Ar), helium gas (He), nitrogen gas (N 2 ) and oxygen gas (O 2 ). Any one or more gases may be added.

Through the above-described process, the second recess pattern 53 may be formed of the first recess pattern 51A and the first pattern 50A having the inclined sidewall and the second pattern 52 having the vertical sidewall. Can be. In addition, the saddle pin pattern 300 including the first and second recess patterns 51A and 53 may be formed. In this case, in the second recess pattern 53 of the present invention, a shortness defect between the landing plug formed on the device isolation layer 47 and the gate electrode embedded in the second recess pattern 53 may occur. It is characterized by having a 'Y' shape to prevent.

Here, in order to form the saddle pin pattern 300, the second recess pattern 53 having an etching depth greater than that of the first recess pattern 51A is also formed through a plurality of etching processes. 53) It is possible to minimize the formation of the bowing profile on the side wall. In addition, by forming the sidewall of the first pattern 50A of the second recess pattern 53 to have a negative slope, it is possible to more effectively prevent the formation of a boeing profile on the sidewall of the second recess pattern 53. .

Next, after removing the second hard mask pattern 49, a cleaning process for removing by-products or residues generated in the process of forming the saddle pin pattern 300 is performed. The washing process can be carried out using a wet cleaning method, specifically, using a hydrofluoric acid solution or a BOE solution. In this case, as some of the first and third insulating layers 44 and 46 made of the oxide film are lost, the line widths of the first and second patterns 50A and 52 may increase. For example, the line width W3 of the second pattern 52 may be larger than the line width W2 of the first recess pattern 51A (W3> W2).

As shown in FIG. 4F, the saddle pin pattern 53 is embedded on the substrate 41, and a gate 57 protrudes over the substrate 41. In this case, the gate 57 is a layer in which the gate insulating layer 54 and the saddle pin pattern 53 are buried and a portion of the gate electrode 55 and the gate hard mask layer 56 protruding from the substrate 41 are sequentially stacked. It can be formed into a structure.

The gate insulating film 54 may be formed of an oxide film, for example, silicon oxide film SiO 2 , and the silicon oxide film for the gate insulating film 54 may be formed using thermal oxidation. The gate electrode 55 may be formed of a single film made of a silicon film or a metallic film, or may be formed of a laminated film in which a silicon film and a metallic film are laminated. As the silicon film, a polysilicon film (poly-Si), a silicon germanium film (SiGe), or the like can be used. As the metallic film, tungsten film (W), titanium film (Ti), tungsten silicide film (WSi), and titanium nitride film (TiN) etc. can be used. The gate hard mask film 56 may be formed of a single film composed of one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which they are stacked.

Here, the gate 57 is an insulating film for preventing short-circuit defects between the gate electrode 55 and the landing plug due to loss of the device isolation film 47 during the subsequent process or misalignment during the process of forming the gate 57. For example, the sidewall of the gate 57 is preferably in contact with the sidewall of the inclined first pattern 50A in order to secure a space in which the anti-short film is to be filled (see reference numeral 'E').

Meanwhile, since the gate 57 has a structure in which a plurality of material films having different physical properties are stacked, a tail is formed at the end of the gate 57 that contacts the substrate 41 due to the difference in etching selectivity between the material films. It may occur. If a tail occurs at the end of the gate 57, there is a possibility that the process of embedding the insulating film for preventing short-circuit defects due to the tail may not be sufficiently secured. desirable.

Therefore, after the gate 57 is formed, the transient etching is performed to remove the tail and to secure a sufficient space between the sidewall of the gate 57 and the sidewall of the first pattern 50A. Referring to the case where the gate electrode 55 is formed of a polysilicon film, the transient etching process will be described in detail as follows.

The transient etching process for removing the end tail of the gate 57 and securing the space between the sidewall of the gate 57 and the sidewall of the first pattern 50A is preferably performed to have an isotropic etching characteristic. To this end, bias power is not applied to the chamber or low bias power in the range of 1W to 100W is applied, and the pressure in the chamber is adjusted to have a range of 2mTorr to 10mTorr. As the etching gas, a mixed gas of chlorine gas (Cl 2), oxygen gas (O 2), bromine hydroxide gas (HBr), nitrogen gas (N 2), nitrogen trifluoride gas (NF 3), CH 2 F 2 gas, and CHF 3 gas is used. Can be carried out.

Next, gate spacers 58 are formed on both side walls of the gate 57. In this case, the gate spacer 58 may be formed of a third insulating layer 46-an oxide layer of the device isolation layer 47 and a material having an etching selectivity and an interlayer insulating layer to be formed through a subsequent process, for example, a nitride layer. As the nitride film, a silicon nitride film can be used.

Here, the gate spacer 58 is formed so that the sidewall of the gate 57 is in contact with the inclined sidewall of the first pattern 50A, thereby sufficiently filling the space created between the sidewall of the gate 57 and the sidewall of the first pattern 50A. It is preferable to form so that it may be buried. Accordingly, the gate spacer 58 acts as a short prevention film that protects the gate 57 from a subsequent inter-process and prevents short circuit defects between the landing plug and the gate electrode 55.

As shown in FIG. 4G, an interlayer insulating film 60 is formed on the entire surface of the substrate 41 to fill the gates 57. The interlayer insulating film 60 may be formed of an oxide film.

Next, after forming a self-aligned contact mask (not shown) on the interlayer insulating film 60, the interlayer insulating film 60 is etched using the self-aligned contact mask as an etch barrier to form a contact hole (not shown) for the landing plug. do.

Next, the landing plug 59 is formed by embedding a conductive material in the contact hole after performing a cleaning process for removing by-products and residues generated during the contact hole forming process. In this case, the landing plug 59 is in contact with the hole-type first plug 59A in contact with both edges of the active region 48 and the center of the active region 48 and extends from the active region 48 to the device isolation layer 47. The second plug 59B of the line type. For reference, the first plug 59A is connected to the storage node through a subsequent process, and the second plug 59B is connected to the bit line.

Here, in the related art, since the interlayer insulating layer 60 and the third insulating layer 46 of the device isolation layer 47 are formed of the same series of materials, for example, an oxide layer, the device under the contact hole due to the low etching selectivity and the cleaning process therebetween. The separation of the separator 47 or the misalignment of the gate 57 caused the gate electrode 55 buried in the second recess pattern 53 to be partially exposed when the contact hole forming process and the cleaning process were completed. . However, according to the present invention, the second recess pattern 53 is formed when the contact hole forming process and the cleaning process are completed due to the gate spacer 58 embedded in the space between the sidewall of the gate 57 and the sidewall of the first pattern 50A. Exposed gate electrode 55 can be prevented. As a result, it is possible to prevent a short circuit from occurring between the landing plug 59 and the gate electrode 55 (see reference numeral 'F').

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A and 1B illustrate a semiconductor device having a saddle fin recess gate according to the prior art.

2a and 2b is an image showing a problem according to the prior art.

3A and 3B illustrate a semiconductor device having a recess gate according to a first embodiment of the present invention.

4A through 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with a second embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

100 substrate 101 active region

102: first insulating film 103: second insulating film

104: third insulating film 105: device isolation film

106: first pattern 107: first recess pattern

108: second pattern 109: second recess pattern

110: gate insulating film 111: gate electrode

112: gate hard mask film 113: gate

114: gate spacer 115: interlayer insulating film

116: landing plug 117: trench

Claims (38)

A substrate having an isolation layer; A recess pattern formed in the device isolation layer and having a sidewall partially inclined; A plurality of gates whose sidewalls contact the inclined sidewalls of the recess pattern; A gate spacer formed on both sidewalls of the gate and filling a space between the sidewall of the recess pattern and the gate sidewall; And A plug buried between the gates A semiconductor device comprising a. The method of claim 1, The recess pattern includes a first pattern having an inclined sidewall and a second pattern having a vertical sidewall under the first pattern. The method according to claim 1 or 2, And the inclined sidewall has a negative slope. The method of claim 1, The gate spacer includes a material having an etch selectivity with respect to the device isolation layer. The method of claim 4, wherein The device isolation film includes an oxide film, and the gate spacer includes a nitride film. A substrate in which an active region is defined by an isolation layer; A first recess pattern having a substrate formed in the active region and having a vertical sidewall; A second recess pattern formed on the device isolation layer and having a portion of the sidewall inclined; A plurality of gates crossing the device isolation layer and the active region at the same time and having a sidewall contacting the inclined sidewall of the second recess pattern; A gate spacer formed on both sidewalls of the gate and filling a space between the inclined sidewall of the second recess pattern and the gate sidewall; And Landing plug between the gates A semiconductor device comprising a. The method of claim 6, The second recess pattern may include a first pattern having an inclined sidewall and a second pattern having a vertical sidewall under the first pattern. The method according to claim 6 or 7, And the inclined sidewall has a negative slope. The method of claim 7, wherein The bottom line width of the first pattern and the line width of the second pattern are the same as or larger than the line width of the first recess pattern. The method of claim 7, wherein The depth of the first recess pattern is greater than the depth of the first pattern. The method of claim 6, The landing plug includes a hole-type first plug in contact with both edges of the active region and a line-type second plug in contact with a central portion of the active region and extending from the active region to the device isolation layer. The method of claim 6, The device isolation film, A first insulating layer partially filling the trench for device isolation; A second insulating film formed along a surface of the trench including the first insulating film; And A third insulating film filling the remaining trench on the second insulating film A semiconductor device comprising a. The method of claim 12, The gate spacer and the second insulating layer may include a material having an etch selectivity with respect to the first and third insulating layers. The method of claim 13, And the first and third insulating films include an oxide film, and the gate spacer and the second insulating film include a nitride film. Forming a device isolation film made of a stacked film in which first, second and third insulating films are sequentially stacked on a substrate; Selectively etching the device isolation layer to form a recess pattern in which a portion of the sidewall is inclined; Forming a plurality of gates such that sidewalls contact the inclined sidewalls of the recess pattern; Forming gate spacers on both sides of the gate to fill a space between the inclined sidewall of the recess pattern and the gate sidewall; And Forming a plug that fills between the gates Semiconductor device manufacturing method comprising a. The method of claim 15, The recess pattern includes a first pattern having an inclined sidewall and a second pattern having a vertical sidewall under the first pattern. The method of claim 15, Forming the recess pattern, Etching the third insulating layer using the hard mask pattern as an etch barrier to form a first pattern having an inclined sidewall; Selectively etching the third insulating layer to extend a line width of the first pattern; And Sequentially etching the second and first insulating layers under the first pattern using the hard mask pattern as an etch barrier to form a second pattern having a vertical sidewall. Semiconductor device manufacturing method comprising a. The method according to any one of claims 15 to 17, And said inclined sidewall has a negative slope. The method of claim 17, Forming the first pattern, A semiconductor device manufacturing method performed under etching conditions in which the etching speed in the vertical direction is faster than the etching speed in the horizontal direction. The method of claim 17, Extending the line width of the first pattern, A method of manufacturing a semiconductor device using the isotropic etching characteristic. The method of claim 17, Forming the second pattern, A method of manufacturing a semiconductor device using anisotropic dry etching method. The method of claim 15, After forming the gate, And performing excessive etching to prevent a tail from occurring in the gate sidewall that is in contact with the inclined sidewall of the recess pattern. The method of claim 15, Forming the device isolation film, Forming a trench in the substrate for device isolation; Forming a first insulating layer partially filling the trench; Forming a second insulating film along the trench surface including the first insulating film; And Forming a third insulating layer filling the second trench on the second insulating layer Semiconductor device manufacturing method comprising a. 24. The method of claim 23, The gate spacer and the second insulating layer are formed of a material having an etching selectivity with the first and third insulating layer. Defining an active region by forming an isolation layer formed of a stacked film in which first, second and third insulating films are stacked on a substrate; Selectively etching the substrate to form a first recess pattern having a vertical sidewall on the substrate of the active region, and forming a second recess pattern having a portion of the sidewall inclined on the device isolation layer; Forming a plurality of gates simultaneously crossing the device isolation layer and the active region and having sidewalls contact the inclined sidewalls of the second recess pattern; Forming a gate spacer on both sidewalls of the gate to fill a space between the gate sidewall and an inclined sidewall of the second recess pattern; And Forming a landing plug between the gate patterns Semiconductor device manufacturing method comprising a. The method of claim 25, The second recess pattern includes a first pattern having an inclined sidewall and a second pattern having a vertical sidewall under the first pattern. The method of claim 25, Forming the first and second recess patterns, Etching the substrate of the active region using the hard mask pattern as an etch barrier to form a first recess pattern having a vertical sidewall; Forming a first pattern having an inclined sidewall by etching the third insulating layer using the hard mask pattern as an etch barrier; Extending a line width of the first pattern; Etching the second and first insulating layers using the hard mask pattern as an etch barrier to form a second pattern having a vertical sidewall under the first pattern to form a second recess pattern formed of the first and second patterns. step; And Further etching the bottom surface of the first recess pattern by using the hard mask pattern as an etch barrier to increase the depth of the first recess pattern. Semiconductor device manufacturing method comprising a. The method according to any one of claims 25 to 27, And said inclined sidewall has a negative slope. The method of claim 27, Forming the first pattern, A semiconductor device manufacturing method performed under etching conditions in which the etching speed in the vertical direction is faster than the etching speed in the horizontal direction. The method of claim 27, Extending the line width of the first pattern, A method of manufacturing a semiconductor device using the isotropic etching characteristic. The method of claim 27, And forming the first recess pattern, forming the second pattern, and increasing the depth of the first recess pattern using anisotropic dry etching. The method of claim 27, The bottom line width of the first pattern and the line width of the second pattern are the same as or larger than the line width of the first recess pattern. The method of claim 27, In increasing the depth of the first recess pattern, The depth of the first recess pattern is formed deeper than the depth of the first pattern. The method of claim 25, After forming the gate, And performing excessive etching to prevent a tail from occurring in the gate sidewall that is in contact with the inclined sidewall of the recess pattern. The method of claim 25, The landing plug includes a hole-type first plug in contact with both edges of the active region and a line-type second plug in contact with a central portion of the active region and extending from the active region to the device isolation layer. The method of claim 25, Forming the device isolation film, Forming a trench in the substrate for device isolation; Forming a first insulating layer partially filling the trench; Forming a second insulating film along the trench surface including the first insulating film; And Forming a third insulating layer filling the second trench on the second insulating layer Semiconductor device manufacturing method comprising a. The method of claim 36, The gate spacer and the second insulating layer are formed of a material having an etching selectivity with the first and third insulating layer. The method of claim 37, And the first and third insulating films include an oxide film, and the gate spacer and the second insulating film include a nitride film.
KR1020090057599A 2009-06-26 2009-06-26 Method of fabricating semiconductor device having recess gate KR20110000203A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8614481B2 (en) 2011-02-28 2013-12-24 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
KR20140100333A (en) * 2013-02-06 2014-08-14 삼성전자주식회사 Three Dimensional Semiconductor Device And Method Of Fabricating The Same
US8987111B2 (en) 2012-03-30 2015-03-24 Samsung Electronics Co., Ltd. Method of manufacturing a three dimensional array having buried word lines of different heights and widths

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8614481B2 (en) 2011-02-28 2013-12-24 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
US8987111B2 (en) 2012-03-30 2015-03-24 Samsung Electronics Co., Ltd. Method of manufacturing a three dimensional array having buried word lines of different heights and widths
KR20140100333A (en) * 2013-02-06 2014-08-14 삼성전자주식회사 Three Dimensional Semiconductor Device And Method Of Fabricating The Same

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