KR100908827B1 - Conductive Pattern Formation Method of Semiconductor Device - Google Patents

Abstract

The present invention prevents the loss of the barrier film on the sidewalls of the contact hole in which the lower pattern is formed in the etching process for forming the conductive pattern having a smaller width than the lower pattern, and prevents notch and necking of the conductive pattern. To provide a method for forming a conductive pattern of the present invention, for this purpose, forming a first insulating film on the conductive layer; Forming a contact pad penetrating the insulating layer and contacting the conductive layer; Forming a second insulating layer on the contact pad to define a bit line pattern region; Forming a photoresist pattern on the second insulating layer to form a bit line exposing an upper portion overlapping with the contact pad; Forming an open part to open the contact pad by etching the second insulating layer using the photoresist pattern as an etch mask; And filling the open part and forming a conductive pattern planarized with the second insulating layer.

Bit line, barrier film, metallization, necking, notch, voids.

Description

METHODS FOR FORMING OF CONDUCTION PATTERN OF SEMICONDUCTOR DEVICE             

1A to 1E are cross-sectional views illustrating a bit line forming process of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a bit line forming process of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30 substrate 31 impurity bonding layer

32: gate insulating film 33: gate conductive film

34: hard mask insulating film 35a: etch stop film

35b: spacer 36: first insulating film

37 plug 38 second insulating film

39: barrier film 40: contact pad

41 insulating film 42 bit line conductive film

43: bitline hardmask

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a conductive pattern of a semiconductor device that can solve the problems caused by the formation of an upper pattern having a narrower width than the lower pattern.

In general, a semiconductor device includes a plurality of semiconductor devices therein. As semiconductor devices become highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of semiconductor devices, for example, transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, the minimum line width of the recent semiconductor DRAM device is formed to 0.115㎛ or less. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

For example, the alignment margin between the bit line contact hole and the bit line is further insufficient so that the bit line contact hole does not completely overlap the bit line when the bit line is etched, thereby exposing a part of the bit line contact hole.

On the other hand, for example, in 4G DRAM, the size of the bit line B / L is about 10% to 30% smaller than the bit line contact hole in the mask layout. As a result, when misalignment occurs during the contact mask operation, the lower metal layer used as the barrier film is lost in the bit line etching step due to the limitation of the resolution, and the surface of the polysilicon layer under the barrier film is damaged. Insufficient resistance causes the semiconductor device to operate normally.

In the case of such a misalignment margin shortage, as the degree of integration of semiconductor devices increases, the misalignment margin shortage becomes more serious as the bit line does not sufficiently cover the bit line contact holes at the manufacturing stage of the cell layout as described above.

When forming the upper pattern narrower than the width of the lower pattern causes the following problems.

One). A photolithography process using an exposure source such as ArF (argon fluoride) has been introduced to form a fine pattern. However, the photoresist for ArF has poor etching resistance and is difficult to form a pattern of 70 mm or less. . In order to overcome this problem, a process method of reducing the critical dimension (hereinafter referred to as CD) through the plasma etching process has been studied, but due to the occurrence of the top notch and necking in the etching step, There arises a problem that the fidelity of the conduction pattern is reduced.

2). In the transient etching step after the conductive pattern is etched, for example, a loss of the barrier film on the sidewall of the contact hole in which the lower plug is formed occurs, which results in poor insulation.

3). Since the CD reduction of the micro pattern obtained through the etching process is limited, voids, etc. occur during the deposition of the insulating layer, thereby degrading the gap-fill characteristics.

Hereinafter, a brief description of a conventional bit line (B / L) forming process.                         

1A to 1E are cross-sectional views illustrating a bit line forming process of a semiconductor device according to the prior art.

FIG. 1A shows a cross section in which an open portion 19 for forming a bit line contact pad is formed.

Specifically, a field oxide film (not shown) is formed on the substrate 10 on which various elements for forming a semiconductor device are formed through a LOCOS or STI process to distinguish an active region and a device isolation region.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern are formed to deposit a gate insulating film 12 of an oxide film array, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like. Of the metal silicide, polysilicon, or the like alone or in combination, the gate conductive film 13 is deposited, and then the nitride film-based hard mask insulating film 14 is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then a hard mask insulating film 14, a gate conductive film 13, and a gate insulating film 12 are selectively formed using the gate electrode pattern as an etching mask. By etching, a gate electrode pattern forming a stack structure of the gate insulating film 12 / gate conductive film 13 / hard mask insulating film 14 is formed.

As the hard mask insulating film 14, it is preferable to use a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film.

Subsequently, a thin nitride film-based etch stop layer 15a is deposited along the entire profile of the gate electrode pattern. Here, the reason why the nitride-based material is used as the etch stop layer 15a can be obtained by selecting an etch selectivity with an oxide layer, which is an interlayer dielectric, during the SAC etching process for the subsequent plug formation, and also preventing the etching loss of the gate electrode pattern. It is to.

Here, a specific process of forming the impurity bonding layer 11 such as a source / drain through an ion implantation process using an ion implantation mask (not shown) between the gate electrode patterns is omitted.

Subsequently, an oxide-based first insulating film 16 such as a BPSG film is formed to sufficiently cover the gate electrode pattern and the upper portion of the substrate 10.

Here, the first insulating layer 16 may include, for example, a phospho-silicate glass (PSG) film or a boro-silicate glass (BSG) film, in addition to the above-described BPSG film. The process is involved.

Next, the cell contact is opened to form a contact plug for electrically connecting the substrate 10 between the gate electrode patterns, specifically, the impurity bonding layer 11 on the surface of the substrate 10 and the device to be formed thereon by a subsequent process. After forming the mask, the first insulating layer 16 is selectively etched using the cell contact open mask as an etch mask to form a contact hole (not shown) for opening the impurity bonding layer 11 between the gate electrode patterns.

By the SAC etching process, the etch stop layer 15a has an inclined profile in the region that is etched and opened, and remains on the sidewall of the gate electrode pattern in the form of a spacer 15b.                         

Subsequently, a conductive material such as polysilicon or tungsten (W) is deposited to contact the open and exposed impurity bonding layer 11 and fill the contact hole, and then a planarization process such as CMP is performed.

In FIG. 1A, the upper portion of the hard mask insulating layer 14 and the plug 17 are planarized. In this case, the planarization height does not need to be aligned with the hard mask insulating layer 14. It may be planarized with a part of 16).

In the case of etching the first insulating layer 16, CxFy (eg, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F _8, or C ₅ F ₁₀ ) may be used. x, y is 1 to 10) as a stock corner gas, and a gas such as CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ is added thereto, and as a carrier gas, He, Ne, Ar, or Xe is used. Use inert gas.

Here, the cell contact open mask may use a hole type, a bar type, a tee type, or the like.

Subsequently, the second insulating film 18 is deposited on the entire surface on which the plug 17 is formed, and then a photoresist pattern (not shown), which is a mask for forming a bit line contact pad, is formed, and then a photoresist pattern (not shown). The second insulating layer 18 is selectively etched with an etch mask to form an open portion 19 exposing the plug 17.

Here, the second insulating film 18 uses a BPSG film, an HTO film, an MTO film, an HDP oxide film, a TEOS film, or an APL film.

Subsequently, a barrier material film is deposited along the profile in which the open part 19 is formed, and then a metal film for forming a contact pad is deposited so as to sufficiently fill the open part 19 thereon.

Here, the metal film for forming the contact pad is preferably made of a material containing aluminum or tungsten.

Made of a berry fish farming material layer typically Ti / TiN structure or TiSi ₂ / Ti / TiN structure, primarily to prevent attack of the plug 17 and the impurity junction layer 11 of the metal film formed such as tungsten, TiSi ₂ is The ohmic contact between the plug 17 and the contact pad forming metal film is reduced.

Subsequently, as shown in FIG. 1B, the barrier layer 20 and the contact pad 21 are buried in the open part through a planarization process such as front etching or CMP. In FIG. 2B, the contact pad is buried. The planarized process cross section is shown.

Subsequently, as shown in FIG. 1C, a bit line forming metal film 22a and a bit line hard mask insulating film 23a are sequentially deposited on the entire surface where the contact pad 21 is formed, and then a photo for forming a bit line pattern is formed. The resist pattern 24 is formed.

Here, the width W1 of the lower pattern region including the contact pad 21 and the barrier layer 20 may be greater than the width W2 of the bit line formation region.

Subsequently, the bit line hard mask insulating film 23a and the bit line forming metal film 22a are sequentially etched using the photoresist pattern 24 as an etch mask to stack the metal film 22b and the hard mask 23b. The bit line pattern B / L of the structure is formed.                         

Subsequently, the photoresist pattern 24 is removed and a cleaning process is performed to remove by-products resulting from etching.

Here, the bit line forming metal film may be formed of a material including tungsten, copper, or aluminum, and FIG. 1D illustrates a process cross section in which the bit line pattern B / L is formed.

Meanwhile, in the etching process for forming the above-described bit line pattern B / L, the CD of the bit line pattern B / L is reduced as indicated by reference numeral 25, and in this process, the bit line pattern B / L is reduced. L) Pattern defects such as notches and neckings occur at the top.

In addition, as described above, the width of the bit line pattern (B / L) formation region is narrower than the width of the contact pad 21 and the barrier layer 20, so that the etching of FIG. 1D for forming the bit line (B / L) pattern is performed. When the over-etching is performed in the process, an under-cut occurs along the sidewalls of the bit line contact holes as indicated by reference numeral 26 to cause loss of the barrier film 20.

Subsequently, as illustrated in FIG. 1E, a third insulating layer 27 is deposited on the entire surface of the resultant bit line pattern B / L.

On the other hand, the cavity 27 is caused when the insulating film 27 is deposited by the cavity formed by the barrier film lost along the contact hole sidewall by the undercut as shown in FIG. 1D, and the void 27 is Lifting of the insulating film pattern occurs to cause a fatal defect of the semiconductor device.

The present invention has been proposed to solve the above problems of the prior art, and prevents the loss of the barrier film on the sidewalls of the contact hole in which the lower pattern is formed in the etching process for forming the conductive pattern having a narrower width than the lower pattern. An object of the present invention is to provide a method of forming a conductive pattern of a semiconductor device capable of preventing notch and necking of the conductive pattern.

The present invention to achieve the above object, forming a first insulating film on the conductive layer; Forming a contact pad penetrating the insulating layer and contacting the conductive layer; Forming a second insulating layer on the contact pad to define a bit line pattern region; Forming a photoresist pattern on the second insulating layer to form a bit line exposing an upper portion overlapping with the contact pad; Forming an open part to open the contact pad by etching the second insulating layer using the photoresist pattern as an etch mask; And filling the open part and forming a conductive pattern planarized with the second insulating layer.

The present invention is not a method of forming a conductive structure having a smaller width than that of a lower structure, for example, a plug structure, and then performing a conventional conductive pattern deposition and etching process for forming a pattern when forming a bit line. After depositing and patterning the insulating film to form an open portion exposing the lower pattern of the region where the conductive pattern is to be formed, the conductive pattern forming material is deposited on the defined open portion and chemical mechanical polishing (hereinafter referred to as CMP). Alternatively, by performing a kind of damascene process that forms an electrically conductive pattern by performing an etchback process, a cavity generated along the lower contact hole sidewall and resulting voids during deposition of the insulating layer is prevented.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2D are cross-sectional views illustrating a bit line forming process of a semiconductor device according to an embodiment of the present invention.

2A shows a process cross section in which a bitline contact pad 40 is formed.

Referring to the cross-sectional process of FIG. 2A, a field oxide film (not shown) is formed on the substrate 30 on which various elements for forming a semiconductor device are formed through a LOCOS or STI process to form an active region and an isolation region. Separate.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern are formed to deposit a gate insulating film 32 of an oxide film array, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like. Of the metal silicide or polysilicon alone or in combination to deposit the gate conductive film 33, and then to deposit a nitride-based hard mask insulating film 34.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then a hard mask insulating film 34, a gate conductive film 33, and a gate insulating film 32 are selectively formed using the gate electrode pattern as an etching mask. By etching, a gate electrode pattern forming a stack (lamination) structure of the gate insulating film 32 / gate conductive film 33 / hard mask insulating film 34 is formed.

It is preferable to use a nitride film series such as a silicon nitride film or a silicon oxynitride film as the hard mask insulating film 34.

Subsequently, a nitride-based etching stop layer 35a is thinly deposited along the entire profile where the gate electrode pattern is formed. The reason for using the nitride film-based material as the material of the etch stop film 35a is to obtain an etch selectivity with an oxide film, which is an interlayer insulating film, in the SAC etching process for the subsequent plug formation, and also the loss of etching of the gate electrode pattern. It is to prevent.

Here, a specific process of forming the impurity bonding layer 31 such as a source / drain through an ion implantation process using an ion implantation mask (not shown) between the gate electrode patterns is omitted.

Meanwhile, in the present embodiment, the bit line pattern forming process is taken as an example. In addition, in the case of forming a metal wiring or a storage node, the impurity bonding layer 31 may be a conductive layer having various forms such as a gate electrode, a bit line, or a plug. have.

Subsequently, an oxide-based first insulating film 36 such as a BPSG film is formed to sufficiently cover the gate electrode pattern and the upper portion of the substrate 30.

Here, the first insulating film 36 may be, for example, a BPSG film, a PSG film, or a BSG film, and these typically include a process of flowing by heat treatment at a predetermined temperature after deposition.

In addition, an HDP oxide film, a TEOS film, or an APL film may be used as the material of the first insulating film 36.

Next, the cell contact is opened to form a contact plug for the electrical connection between the substrate 30 between the gate electrode patterns, specifically, the impurity bonding layer 31 on the surface of the substrate 30 and the device to be formed thereon by a subsequent process. After forming a mask (not shown), a contact hole (not shown) for opening the impurity bonding layer 31 between the gate electrode patterns by selectively etching the first insulating layer 36 using the cell contact open mask as an etch mask. ).

By the SAC etching process, the etch stop layer 35a has an inclined profile in an area that is etched and opened, and remains on the sidewall of the gate electrode pattern in the form of a spacer 35b.

Subsequently, a conductive material such as polysilicon or tungsten is deposited to contact the open and exposed impurity bonding layer 31 and fill the contact hole sufficiently, and then a planarization process such as CMP is performed.

In the present exemplary embodiment, the upper portion of the hard mask insulating layer 34 and the plug 37 are planarized. At this time, the level of the planarization does not need to be matched with the hard mask insulating layer 34. It may be planarized with a part of 36.

In the case of etching the first insulating layer 66, CxFy (eg, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F _8, or C ₅ F ₁₀ ) may be used. x, y is 1 to 10) as a stock corner gas, and a gas such as CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ is added thereto, and as a carrier gas, He, Ne, Ar, or Xe is used. Use inert gas.

Here, the cell contact open mask may have various forms such as hole type, bar type or tee type.

Subsequently, the second insulating layer 38 is deposited on the entire surface on which the plug 37 is formed, and then a photoresist pattern (not shown), which is a mask for forming a bit line contact hole, is formed, and then the photoresist pattern is etched. The second insulating layer 38 is selectively etched to form an open portion (not shown), that is, a bit line contact hole, to expose the plug 37.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern, followed by a cleaning process to remove etch byproducts.

Here, the second insulating film 38 uses a BPSG film, an HTO film, an MTO film, an HDP oxide film, a TEOS film, or an APL film.

Subsequently, a barrier material film is deposited along the profile in which the bit line contact holes are formed, and then a metal film for forming contact pads is deposited on top of the barrier layer to sufficiently fill the bit line contact holes.

Here, the metal film for forming the contact pad is preferably made of a material containing Ti, Al or W.

Made of a berry fish farming material layer typically Ti / TiN structure or TiSi ₂ / Ti / TiN structure, primarily to prevent attack of the plug 37 and the impurity junction layer 31 of the metal film formed such as tungsten, TiSi ₂ is An ohmic contact that lowers the contact resistance between the plug 37 and the metal film for forming the contact pad is achieved.

Subsequently, as shown in FIG. 2B, the barrier layer 39 and the contact pad 40 are buried in the bit line contact hole through a planarization process such as full surface etching or CMP.

Next, an insulating film 41 for defining a bit line pattern region is deposited on the entire surface where the contact pad 40 is formed. In this case, since the thickness of the insulating layer 41 represents the thickness of the bit line pattern, the thickness of the insulating layer 41 is deposited to a thickness corresponding to the size of the bit line pattern to be formed, and an oxide-based material is preferably used.

A bit line forming photoresist pattern 42 is formed on the insulating film 41.

Here, it can be seen that the width W3 of the bit line contact hole is larger than the width W4 of the photoresist pattern 42 for forming the bit line, and FIG. 2B shows that the photoresist pattern 42 for forming the bit line pattern is formed. The process cross section is shown.

Subsequently, the insulating layer 41 is etched by using the photoresist pattern 42 as an etch mask to expose the bit line contact pads 40 to form an open portion having a width transferred by the width of the photoresist pattern 42. The metal film for forming the bit line is deposited to fill the open portion.

Here, the metal film for forming the bit line is preferably made of a material containing aluminum or tungsten, and is mainly deposited using a CVD method or a PVD method.

Subsequently, the bit line conductive film 42 recessed in the open part is etched to form the bit line conductive film 42. In FIG. 2C, the bit line forming conductive film 42 is formed in the open part formed by etching the insulating film 41. Represents a process cross section filling in a recessed form.

At this time, it is preferable to fill the bit line conductive film 42 by 1/3 to 1/2 from the bottom of the open portion.

The insulating film 43 for the bit line hard mask is deposited to a sufficient extent to fill the open portion on the entire surface where the bit line conductive film 42 is formed, and then an etch back or CMP process is performed until the insulating film 41 is exposed.

Accordingly, the bit line pattern B / L having the structure in which the hard mask insulating film 43 and the conductive film 42 are stacked is formed between the insulating films 41.

Accordingly, the bit line pattern B / L may be formed without a separate etching process for forming the bit line pattern (that is, the contact pad 40 and the barrier layer 39 are not exposed when the bit line pattern is formed). The barrier layer 39 may be prevented from being lost along the sidewalls of the bit line contact holes.

In addition, it is possible to prevent the notch phenomenon and the necking phenomenon of the betaine pattern on the bit line pattern by etching for pattern formation.

In addition, the gap caused by the barrier film loss can solve the gap-fill problem caused during the subsequent deposition of the insulating film.                     

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can prevent the loss of the barrier film in the contact hole sidewall of the lower conductive line, it can be expected an excellent effect to improve the yield of the semiconductor device.

Claims (7)

Forming a first insulating film on the conductive layer; Forming a contact pad penetrating the insulating layer and contacting the conductive layer; Forming a second insulating layer on the contact pad to define a bit line pattern region; Forming a photoresist pattern on the second insulating layer to form a bit line exposing an upper portion overlapping with the contact pad; Forming an open part to open the contact pad by etching the second insulating layer using the photoresist pattern as an etch mask; Depositing a conductive film to bury the open portion; Performing an etch back process to allow the conductive film to be recessed in the open portion; Depositing an insulating film for a hard mask to bury the open portion on the recessed conductive film; And Removing the hard mask insulating layer to expose the second insulating layer to form a conductive pattern in which the conductive layer and the hard mask insulating layer are stacked in the open part; Conductive pattern forming method of a semiconductor device comprising a. The method of claim 1, The width of the photoresist pattern is narrower than the width of the contact pad, the method of forming a conductive pattern of a semiconductor device. The method of claim 1, The second insulating layer is an oxide film-based method of forming a conductive pattern of a semiconductor device. delete The method of claim 1, And in the step of recessing the conductive film, the conductive film is formed to a depth of 1/3 to 1/2 from a bottom surface of the open part. The method of claim 1, And the conductive layer is any one of an impurity bonding layer, a contact pad, a gate electrode pattern, a bit line pattern, and a metal wiring. The method of claim 1, And wherein the conductive pattern is a bit line pattern or a metal wiring.

Images