KR980005619A - Method of forming a contact hole in a semiconductor device - Google Patents

Method of forming a contact hole in a semiconductor device Download PDF

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Publication number
KR980005619A
KR980005619A KR1019960025782A KR19960025782A KR980005619A KR 980005619 A KR980005619 A KR 980005619A KR 1019960025782 A KR1019960025782 A KR 1019960025782A KR 19960025782 A KR19960025782 A KR 19960025782A KR 980005619 A KR980005619 A KR 980005619A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor device
barrier layer
semiconductor substrate
etching
Prior art date
Application number
KR1019960025782A
Other languages
Korean (ko)
Inventor
김근태
김진웅
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025782A priority Critical patent/KR980005619A/en
Publication of KR980005619A publication Critical patent/KR980005619A/en

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Abstract

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 반도체 기판 상부에 게이트 전극을 형성하고, 상기 반도체기판의 전체 표면 상부에 완충막을 형성한 다음, 상기 완충막 상부에 식각 장벽층을 형성하고, 상기 반도체 기판의 전체 표면상부를 평탄화시키는 하부절연층을 형성한 다음, 상기 하부 절연층을 식각하되, 콘택마스크를 이용하여 상기 식각장벽층이 노출되도록 식각하고, 상기 노출된 식각장벽층과 상기 완충막을 이방성 식각하여 상기 반도체 기판을 노출시키는 콘택홀을 자기정렬적으로 형성함으로써 상기 식각장벽층으로 인한 반도체소자의 특성변화를 방지하여 반도체 소자의 특성 및 신뢰성을 향상 시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 잇점이 있다.A method of forming a contact hole in a semiconductor device includes forming a gate electrode on a semiconductor substrate, forming a buffer layer on the entire surface of the semiconductor substrate, forming an etch barrier layer on the buffer layer, Forming a lower insulating layer on the upper surface of the semiconductor substrate to planarize the upper surface of the semiconductor substrate; etching the lower insulating layer to etch the etch barrier layer using a contact mask; By forming the contact holes for aligning the semiconductor substrate by anisotropically etching the film, the characteristics of the semiconductor device can be prevented from being changed due to the etching barrier layer, thereby improving the characteristics and reliability of the semiconductor device, .

Description

반도체 소자의 콘택홀 형성방법Method of forming a contact hole in a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1a도 내지 제1c도는 본 발명의 실시예에 의한 반도체 소자의 콘택홀 형성방법을 도시한 단면도.FIGS. 1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention; FIGS.

Claims (4)

반도체 기판 상부에 게이트전극을 형성하는 공정과, 상기 반도체기판의 전체 표면 상부에 완충막을 형성하는 공정과, 상기 완충막 상부에 식각장벽층을 형성하는 공정과, 상기 반도체기판의 전체 표면 상부를 평탄화 시키는 하부 절연층을 형성하는 공정과, 상기 하부 절연층을 식각하되, 콘택 마스크를 이용하고 상기 식각장벽층이 노출되도록 식각하는 공정과, 상기 노출된 식각장벽층과 상기 완충막을 이방성 식각하여 상기 반도체 기판을 노출시키는 콘택홀을 형성하는 공정을 포함하는 반도체 소자의 콘택홀 형성방법.A method of manufacturing a semiconductor device, comprising: forming a gate electrode on a semiconductor substrate; forming a buffer film on the entire surface of the semiconductor substrate; forming an etching barrier layer on the buffer film; Etching the lower insulating layer so as to expose the etching barrier layer using a contact mask, and etching the exposed etching barrier layer and the buffer film to form a lower insulating layer, And forming a contact hole for exposing the substrate. 제1항에 있어서, 상기 완충막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method according to claim 1, wherein the buffer film is formed of an oxide film. 제1항에 있어서, 상기 식각장벽층은 상기 완충막과 식각선택비 및 응력의 차이가 없으며 상기 하부 절연층과 일정한 식각선택비 차이를 갖는 물질을 사용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The semiconductor device according to claim 1, wherein the etching barrier layer is formed of a material having no difference in etch selectivity and stress between the buffer layer and the lower insulating layer, Way. 제1항 또는 제3항에 있어서, 상기 식각장벽층은 산화질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1 or 3, wherein the etching barrier layer is formed of a nitride oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025782A 1996-06-29 1996-06-29 Method of forming a contact hole in a semiconductor device KR980005619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025782A KR980005619A (en) 1996-06-29 1996-06-29 Method of forming a contact hole in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025782A KR980005619A (en) 1996-06-29 1996-06-29 Method of forming a contact hole in a semiconductor device

Publications (1)

Publication Number Publication Date
KR980005619A true KR980005619A (en) 1998-03-30

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Family Applications (1)

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KR1019960025782A KR980005619A (en) 1996-06-29 1996-06-29 Method of forming a contact hole in a semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431822B1 (en) * 1999-12-28 2004-05-20 주식회사 하이닉스반도체 Method for forming contact in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431822B1 (en) * 1999-12-28 2004-05-20 주식회사 하이닉스반도체 Method for forming contact in semiconductor device

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