KR980005630A - Method for manufacturing platinum electrode of semiconductor device - Google Patents

Method for manufacturing platinum electrode of semiconductor device Download PDF

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Publication number
KR980005630A
KR980005630A KR1019960025938A KR19960025938A KR980005630A KR 980005630 A KR980005630 A KR 980005630A KR 1019960025938 A KR1019960025938 A KR 1019960025938A KR 19960025938 A KR19960025938 A KR 19960025938A KR 980005630 A KR980005630 A KR 980005630A
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South Korea
Prior art keywords
layer
etching
mask pattern
platinum
platinum electrode
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KR1019960025938A
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Korean (ko)
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KR100190055B1 (en
Inventor
남병윤
유원종
함진환
김현우
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김광호
삼성전자 주식회사
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Priority to KR1019960025938A priority Critical patent/KR100190055B1/en
Publication of KR980005630A publication Critical patent/KR980005630A/en
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Publication of KR100190055B1 publication Critical patent/KR100190055B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 장치의 백금전극 제조방법에 관하여 기재하고 있다. 트랜지스터 등과 같은 하부구조물이 형성된 반도체기판 상에 베리어층을 얇게 형성하고, 상기 베리어층 상에 백금층 및 접착층을 적층한 다음, 상기 접착층 상에 마스크 패턴을 형성한 다음, 상기 마스크 패턴을 식각마스크로 사용하고 제1 식각가스를 사용하여 상기 베리어층을 식각하고 상기 백금층을 제2 식각가스를 사용하여 식각한다. 하부절연막의 손상을 방지하면서, 마스크 패턴 측벽에 폴리머 발생을 감소시킬 수 있으며, 보다 양호한 경사를 갖는 백금전극을 형성할 수 있다.A method of manufacturing a platinum electrode of a semiconductor device is described. A thin layer of a barrier layer is formed on a semiconductor substrate on which a substructure such as a transistor is formed, a platinum layer and an adhesive layer are laminated on the barrier layer, a mask pattern is formed on the adhesive layer, The barrier layer is etched using a first etch gas and the platinum layer is etched using a second etch gas. It is possible to reduce the generation of polymer on the side wall of the mask pattern while preventing the lower insulating film from being damaged, and to form a platinum electrode having a better inclination.

Description

반도체 장치의 백금전극 제조방법Method for manufacturing platinum electrode of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도 및 제4도는 본 발명의 일 실시예에 따른 백금전극 제조방법을 설명하기 위하여 도시한 단면도들이다.FIGS. 3 and 4 are cross-sectional views illustrating a method of fabricating a platinum electrode according to an embodiment of the present invention.

Claims (8)

트랜지스터 등과 같은 하부구조물이 형성된 반도체 기판 상에 베리어층(barier layer)을 형성하는 제1단계; 상기 베어리층 상에 백금층 및 접착층을 적층하는 제2단계; 상기 접착층(adhesion layer) 상에 백금전극 형성을 위한 마스크 패턴을 형성하는 제3단계; 상기 마스크 패턴을 식각마스크로 사용하고 제1 식각가스를 사용하여 상기 베리어층을 식각하는 제 4단계; 및 상기 백금층을 염소(CI2)와 산소(O2)를 일정비율로 함유하는 제2 식각가스를 사용하여 식각하는 제5단계를 구비하는 것을 특징으로 하는 백금전극 제조방법.A first step of forming a barrier layer on a semiconductor substrate on which a substructure such as a transistor is formed; A second step of laminating a platinum layer and an adhesive layer on the bare layer; A third step of forming a mask pattern for forming a platinum electrode on the adhesion layer; A fourth step of etching the barrier layer using the mask pattern as an etching mask and using a first etching gas; And a fifth step of etching the platinum layer using a second etching gas containing chlorine (CI2) and oxygen (O2) at a predetermined ratio. 제1항에 있어서, 상기 베리어층은 질화타이타늄(TiN)으로, 접착층은 타이타늄(TiN) 또는 질화타이타늄으로 형성하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 1, wherein the barrier layer is formed of titanium nitride (TiN), and the adhesive layer is formed of titanium (TiN) or titanium nitride. 제2항에 있어서, 상기 제1 식각가스는 염소(CI2)계 화합물 가스를 사용하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 2, wherein the first etching gas is a chlorine (CI 2) compound gas. 제1항에 있어서, 상기 백금전극 식각시 오버 에치를 실시하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 1, wherein an overetching is performed when the platinum electrode is etched. 제1항에 있어서 상기 제2 식각가스는 O2 비율이 40% 이상인 CI2/O2 가스를 사용하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 1, wherein the second etching gas uses CI2 / O2 gas having an O2 ratio of 40% or more. 제1항에 있어서, 상기 마스크 패턴은 산화물로 형성하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 1, wherein the mask pattern is formed of an oxide. 제1항에 있어서, 상기 제5단계 후, 상기 베리어층을 제3 식각가스를 사용하여 식각하는 제6단계; 상기 마스크 패턴 및 상기 마스크 패턴 아래에 잔존하는 접착층을 제거하는 제7단계; 상기 백금전극을 둘러싸는 유전체막을 형성하는 제8단계; 및 유전체막이 형성된 결과물 상에 플레이트 전극을 형성하는 제9단계를 더 구비하는 것을 특징으로 하는 백금전극 제조방법.The method of claim 1, further comprising: after the fifth step, etching the barrier layer using a third etching gas; A seventh step of removing the mask pattern and the adhesive layer remaining under the mask pattern; An eighth step of forming a dielectric film surrounding the platinum electrode; And a ninth step of forming a plate electrode on the resultant product having the dielectric film formed thereon. 제7항에 있어서, 상기 제3 식각가스는 염소(CI2)계 화합물 가스를 사용하는 것을 특징으로 하는 백금전극 제조방법.8. The method of claim 7, wherein the third etching gas is a chlorine (Cl2) compound gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025938A 1996-06-29 1996-06-29 White electrode manufacturing method of semiconductor device KR100190055B1 (en)

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KR1019960025938A KR100190055B1 (en) 1996-06-29 1996-06-29 White electrode manufacturing method of semiconductor device

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KR980005630A true KR980005630A (en) 1998-03-30
KR100190055B1 KR100190055B1 (en) 1999-06-01

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100407983B1 (en) * 1997-12-29 2004-03-20 주식회사 하이닉스반도체 Pt ETCHING PROCESS
KR100499429B1 (en) * 1998-08-31 2005-07-07 인피니언 테크놀로지스 아게 Microelectronic structure, production method and utilization of the same
KR100546273B1 (en) * 1998-04-21 2006-04-21 삼성전자주식회사 Method for pt layer etching using merie equipment having dual rf power
KR100691927B1 (en) * 1998-12-30 2007-12-07 주식회사 하이닉스반도체 Capacitor Manufacturing Method of Semiconductor Device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100407983B1 (en) * 1997-12-29 2004-03-20 주식회사 하이닉스반도체 Pt ETCHING PROCESS
KR100546273B1 (en) * 1998-04-21 2006-04-21 삼성전자주식회사 Method for pt layer etching using merie equipment having dual rf power
KR100499429B1 (en) * 1998-08-31 2005-07-07 인피니언 테크놀로지스 아게 Microelectronic structure, production method and utilization of the same
KR100691927B1 (en) * 1998-12-30 2007-12-07 주식회사 하이닉스반도체 Capacitor Manufacturing Method of Semiconductor Device

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Publication number Publication date
KR100190055B1 (en) 1999-06-01

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