KR970077353A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970077353A
KR970077353A KR1019970022319A KR19970022319A KR970077353A KR 970077353 A KR970077353 A KR 970077353A KR 1019970022319 A KR1019970022319 A KR 1019970022319A KR 19970022319 A KR19970022319 A KR 19970022319A KR 970077353 A KR970077353 A KR 970077353A
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KR
South Korea
Prior art keywords
gas
semiconductor device
manufacturing
insulating film
volume ratio
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KR1019970022319A
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Korean (ko)
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KR100252492B1 (en
Inventor
히데아끼 가와모또
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가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
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Publication of KR970077353A publication Critical patent/KR970077353A/en
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Publication of KR100252492B1 publication Critical patent/KR100252492B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

알루미늄합금막(3-1Aa) 및 질화티탄막(8a)을 포함하는 적층막이 에칭될 때 에칭 가스로서 염소 가스(Cl2) 및 삼염화붕소(BCl3)를 포함하는 혼합가스가 채용되는 것을 특징으로 하는 반도체 디바이스 제조 방법이 제공되고 있다. Cl2및 BCl3가스에 대한 BCl3가스의 체적 비가 15% 이상으로 설정된다. 상기 언급된 발명은 에칭시 질화티탄막의 표면에 요철이 발생하는 것을 억제하게 되고, 이로써 질화티탄막의 표면의 요철에 기인하여 발생하는 에칭 잔류물의 발생을 방지하며, 결국 배선 층 들간의 단락회로를 방지하게 된다.When the laminated film including the aluminum alloy film 3-1Aa and the titanium nitride film 8a is etched, a mixed gas containing chlorine gas (Cl 2 ) and boron trichloride (BCl 3 ) is employed as the etching gas. A semiconductor device manufacturing method is provided. Volume of the BCl 3 gas for the Cl 2 gas and BCl 3 ratio is set to 15% or more. The above-mentioned invention suppresses the occurrence of unevenness on the surface of the titanium nitride film during etching, thereby preventing the occurrence of etching residues caused by the unevenness of the surface of the titanium nitride film, and thus preventing a short circuit between the wiring layers. Done.

Description

반도체 디바이스의 제조 방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4a도 내지 제4c도는 본 발명의 제1실시예에 따른 방법의 각 단계를 도시하는 반도체 디바이스의 단면도.4A to 4C are cross-sectional views of semiconductor devices showing respective steps of the method according to the first embodiment of the present invention.

Claims (8)

반도체 디바이스의 제조 방법에 있어서, (a) 반도체 기판(1) 상에 제1절연막(2)을 형성하는 단계; (b) 상기 제1절연막(2) 상에, 최소한 질화티탄(TiN)막(8, 3-2A) 및 알루미늄합금막(3-1A, 3-1B)을 포함하는 적층막(8, 3-1A;3-1B, 3-2A)을 형성하는 단계; (c) 상기 적층막(8, 3-1A;3-1B, 3-2A) 상에 제2절연막(9)을 형성하는 단계; (d) 상기 제2절연막(9)을 소망의 패턴으로 패턴화하는 단계; 및 (e) 상기 패턴화된 제2절연막(9a)이 플라즈마 에칭에 의한 마스크로서 사용되면서 상기 적층막(8, 3-1A;3-1B, 3-2A)을 패턴화하는 단계를 포함하되, 염소(Cl2) 가스 및 환원(reducing) 가스를 포함하는 혼합 가스가 에칭 가스로서 사용되며, 상기 염소 및 상기 환원 가스들에 대한 상기 환원 가스의 체적비는 15% 이상인 것을 특징으로 하는 반도체 디바이스의 제조 방법.A method of manufacturing a semiconductor device, comprising: (a) forming a first insulating film (2) on a semiconductor substrate (1); (b) On the first insulating film 2, a laminated film 8, 3- comprising at least titanium nitride (TiN) films 8, 3-2A and aluminum alloy films 3-1A, 3-1B. 1A; 3-1B, 3-2A); (c) forming a second insulating film (9) on the laminated film (8, 3-1A; 3-1B, 3-2A); (d) patterning the second insulating film (9) in a desired pattern; And (e) patterning the laminated films 8, 3-1A; 3-1B, 3-2A while the patterned second insulating film 9a is used as a mask by plasma etching. A mixed gas containing chlorine (Cl 2 ) gas and reducing gas is used as an etching gas, and the volume ratio of the chlorine and the reducing gas to the reducing gases is 15% or more. Way. 제1항에 있어서, 상기 환원 가스는 삼염화붕소(BCl3) 가스인 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the reducing gas is boron trichloride (BCl 3) gas. 제1항 또는 제2항에 있어서, 상기 환원 가스의 체적비는 70% 이하인 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the volume ratio of the reducing gas is 70% or less. 제1항 또는 제2항에 있어서, 상기 제2절연막(9)은 이산화규소막인 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the second insulating film (9) is a silicon dioxide film. 제1항 또는 제2항에 있어서, 상기 혼합 가스는 질소(N2) 가스를 더 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the mixed gas further comprises nitrogen (N 2 ) gas. 제5항에 있어서, 상기 환원 가스의 체적비는 70% 이하인 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method for manufacturing a semiconductor device according to claim 5, wherein the volume ratio of the reducing gas is 70% or less. 제5항에 있어서, 상기 염소, 환원 및 질소 가스들 모두에 대한 상기 질소 가스의 체적비는 5% 이상인 것을 특징으로 하는 반도체 디바이스의 제조 방법.6. The method of claim 5, wherein the volume ratio of the nitrogen gas to all of the chlorine, reducing and nitrogen gases is at least 5%. 제7항에 있어서, 상기 질소 가스의 체적비는 50% 이하인 것을 특징으로 하는 반도체 디바이스의 제조 방법.The method for manufacturing a semiconductor device according to claim 7, wherein the volume ratio of the nitrogen gas is 50% or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019970022319A 1996-05-30 1997-05-30 Method of fabricating semiconductor device KR100252492B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP08137225A JP3112832B2 (en) 1996-05-30 1996-05-30 Method for manufacturing semiconductor device
JP96-137225 1996-05-30

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KR970077353A true KR970077353A (en) 1997-12-12
KR100252492B1 KR100252492B1 (en) 2000-05-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100453956B1 (en) * 2001-12-20 2004-10-20 동부전자 주식회사 Method for manufacturing metal line of semiconductor device
KR20210110657A (en) * 2020-02-27 2021-09-08 주식회사 히타치하이테크 Plasma treatment method

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW383427B (en) * 1998-04-03 2000-03-01 United Microelectronics Corp Method for etching tantalum oxide
GB2337361B (en) * 1998-05-06 2000-03-29 United Microelectronics Corp Method of etching tantalum oxide layer
US6177353B1 (en) * 1998-09-15 2001-01-23 Infineon Technologies North America Corp. Metallization etching techniques for reducing post-etch corrosion of metal lines
JP3257533B2 (en) 1999-01-25 2002-02-18 日本電気株式会社 Wiring formation method using inorganic anti-reflection film
JP3733021B2 (en) * 2000-12-15 2006-01-11 シャープ株式会社 Plasma process method
JP4546667B2 (en) * 2001-05-17 2010-09-15 東京エレクトロン株式会社 Dry etching method
DE102004022402B4 (en) * 2004-05-06 2007-03-15 Infineon Technologies Ag Process for the anisotropic etching of aluminum-containing substrates
JP5237306B2 (en) * 2010-01-07 2013-07-17 日本電信電話株式会社 Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
JPH06104222A (en) * 1992-09-18 1994-04-15 Fujitsu Ltd Manufacture of semiconductor device
JPH06151382A (en) * 1992-11-11 1994-05-31 Toshiba Corp Dry etching method
US5350488A (en) * 1992-12-10 1994-09-27 Applied Materials, Inc. Process for etching high copper content aluminum films

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100453956B1 (en) * 2001-12-20 2004-10-20 동부전자 주식회사 Method for manufacturing metal line of semiconductor device
KR20210110657A (en) * 2020-02-27 2021-09-08 주식회사 히타치하이테크 Plasma treatment method

Also Published As

Publication number Publication date
GB9711309D0 (en) 1997-07-30
GB2313708B (en) 1998-07-29
JP3112832B2 (en) 2000-11-27
JPH09321026A (en) 1997-12-12
GB2313708A (en) 1997-12-03
KR100252492B1 (en) 2000-05-01

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