KR950034416A - How to Form Via Holes - Google Patents

How to Form Via Holes Download PDF

Info

Publication number
KR950034416A
KR950034416A KR1019940010292A KR19940010292A KR950034416A KR 950034416 A KR950034416 A KR 950034416A KR 1019940010292 A KR1019940010292 A KR 1019940010292A KR 19940010292 A KR19940010292 A KR 19940010292A KR 950034416 A KR950034416 A KR 950034416A
Authority
KR
South Korea
Prior art keywords
via hole
protective film
gas
forming
slope
Prior art date
Application number
KR1019940010292A
Other languages
Korean (ko)
Inventor
승성표
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940010292A priority Critical patent/KR950034416A/en
Publication of KR950034416A publication Critical patent/KR950034416A/en

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 비아홀의 바닥에 잔류물의 증착이 없으며 슬로프가 완만한 비아홀 형성방법에 관한 것이다.The present invention relates to a method of forming a via hole without a deposit of residue at the bottom of the via hole and having a gentle slope.

본 발명은 반도체장치의 다층배선구조에서 메탈콘택부의 비아홀 형성방법에 있어서, 가) 제1절연막위에 메탈층을 형성하고 제2절연막을 증착하는 단계와, 나) 감광제로서 마스크패턴을 형성하여 플라즈마분위기에서 절연막까지만 비등방성식각을 하고 나서 감광제를 제거하여 비아홀을 형성하는 단계와, 다) 도포성이 뛰어난 물질을 코팅하여 보호막을 형성하고 비아홀 내에 보호막의 일부가 잔류하도록 식각함과 동시에 비아홀 측벽 모서리의 슬로프를 조절하는 단계와, 라) 비아홀 내에 잔류하는 보호막을 제거하는 단계의 포함한다.In the method of forming a via hole of a metal contact portion in a multilayer wiring structure of a semiconductor device, a) forming a metal layer on a first insulating film and depositing a second insulating film; and b) forming a mask pattern as a photosensitive agent to form a plasma atmosphere. Anisotropically etch only to the insulating film, and then remove the photoresist to form a via hole; c) coating a material having excellent coating property to form a protective film, and etching part of the protective film to remain in the via hole, Adjusting the slope; and d) removing the protective film remaining in the via hole.

Description

비아홀 형성방법How to Form Via Holes

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 방법에 의한 비아홀의 단면도이다.3 is a cross-sectional view of the via hole by the method of the present invention.

Claims (8)

반도체장치의 다층배선구조에서 메탈콘택부의 비아홀 형성방법에 있어서, 가) 제1절연막위에 메탈층을 형성하고 제2절연막을 증착하는 단계와, 나) 감광제로서 마스크패턴을 형성하여 플라즈마분위기에서 절연막까지만 비등방성식각을 하고 나서 감광제를 제거하여 비아홀을 형성하는 단계와, 다) 도포성이 뛰어난 물질로 코팅하여 보호막을 형성하고 비아홀 내에 보호막의 일부가 잔류하도록 식각함과 동시에 비아홀 측벽 모서리의 슬로프를 조절하는 단계와, 라) 비아홀 내에 잔류하는 보호막을 제거하는 단계를 포함하는 비아홀 형성방법.In the method of forming a via hole of a metal contact portion in a multi-layer wiring structure of a semiconductor device, a) forming a metal layer on the first insulating film and depositing a second insulating film; and b) forming a mask pattern as a photosensitive agent to form only a plasma atmosphere to an insulating film. Anisotropic etching and removing the photoresist to form via holes; c) coating with a coating material to form a protective film, and etching the portion of the protective film to remain in the via hole and simultaneously controlling the slope of the sidewall of the via hole. And d) removing the protective film remaining in the via hole. 제1항에 있어서, 상기 다)단계의 보호막은 SOG이고, 슬로프조절방법은 불활성개스에 프레온 개스를 첨가해서 스퍼터에치를 실시하여 하는 것이 특징인 비아홀 형성방법.The method of claim 1, wherein the protective film of step c) is SOG, and the slope adjusting method is performed by sputter etching by adding freon gas to an inert gas. 제2항에 있어서, 불활성 개스는 Ar, He, Xe, N2중의 어느 하나를 사용하여 10 내지 500mtorr의 공정압력으로 하는 것이 특징인 비아홀 형성방법.The method of claim 2, wherein the inert gas is a process pressure of 10 to 500 mtorr using any one of Ar, He, Xe, and N 2 . 제1항에 있어서, 상기 보호막은 폴리머이고, 상기 슬로프조절방법은 산소와 프레온 개스로 선택비를 1로 식각하여 슬로프를 조절하는 것이 특징인 비아홀 형성방법.The method of claim 1, wherein the passivation layer is a polymer, and the slope control method includes adjusting a slope by etching a selectivity of 1 with oxygen and a freon gas. 제4항에 있어서, 상기 폴리머는 포토레지스트인 것이 특징인 비아홀 형성방법.The method of claim 4, wherein the polymer is a photoresist. 제1항에 있어서, 상기 라)단계의 보호막의 제거는 불화개스에 산소개스에 첨가하여 제거하는 것이 특징인 비아홀 형성방법.The method of claim 1, wherein the removing of the protective film in step d) is performed by adding oxygen gas to fluoride gas. 제6항에 있어서, 불화개스는 CF4, CHF3, C2F8, C3F|8, C4F8등의 할로카본개스중 하나 이상을 함께 사용하는 것이 특징인 비아홀 형성방법.The method of claim 6 wherein the fluoride gas is CF 4 , CHF 3 , C 2 F 8 , C 3 F | 8 , C 4 F 8 Via hole formation method characterized in using together one or more of the halocarbon gas. 제7항에 있어서, 상기 CHF3/CF4의 값은 1:1 내지 2.5:1 인 것이 특징인 비아홀 형성방법.The method of claim 7, wherein the value of CHF 3 / CF 4 is 1: 1 to 2.5: 1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010292A 1994-05-11 1994-05-11 How to Form Via Holes KR950034416A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940010292A KR950034416A (en) 1994-05-11 1994-05-11 How to Form Via Holes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940010292A KR950034416A (en) 1994-05-11 1994-05-11 How to Form Via Holes

Publications (1)

Publication Number Publication Date
KR950034416A true KR950034416A (en) 1995-12-28

Family

ID=66682423

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940010292A KR950034416A (en) 1994-05-11 1994-05-11 How to Form Via Holes

Country Status (1)

Country Link
KR (1) KR950034416A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480580B1 (en) * 1998-02-09 2005-05-16 삼성전자주식회사 Method for forming via hole of semiconductor device using n2 gas

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480580B1 (en) * 1998-02-09 2005-05-16 삼성전자주식회사 Method for forming via hole of semiconductor device using n2 gas

Similar Documents

Publication Publication Date Title
WO2000031775A3 (en) A method of manufacturing an electronic device comprising two layers of organic-containing material
KR20010014608A (en) Fabricating method of semiconductor device
KR970077353A (en) Manufacturing Method of Semiconductor Device
KR950034416A (en) How to Form Via Holes
GB2320613A (en) Interconnect fabrication
KR100221585B1 (en) Forming method for via hole of semiconductor device
KR0172293B1 (en) Method of forming contact hole of semiconductor device
KR950003224B1 (en) Fabricationg method of semiconductor device having multi-layer structure
KR100284311B1 (en) Method of manufacturing semiconductor device for improving via contact resistance
KR950011172B1 (en) Method of patterning triple layer photoresist
KR950025875A (en) Method for manufacturing metal contact vias in semiconductor devices
KR100279047B1 (en) A fabricating method of contact hole of semiconductor device
KR960043119A (en) Via hole formation method of semiconductor device
JPH03116830A (en) Etching back method
KR940015698A (en) Fine photoresist pattern formation method
KR100252757B1 (en) Method of forming metal pattern
KR970018216A (en) Planarization Method of Semiconductor Device
KR950014970A (en) Method of planarizing interlayer insulating film of semiconductor device
KR970052372A (en) Metal wiring formation method of semiconductor device
KR960032681A (en) Method of forming multilayer wiring in semiconductor device
KR970052230A (en) Method for manufacturing via contact hole in semiconductor device
KR970003854A (en) How to Form Multilayer Metal Wiring
KR960042958A (en) Contact hole formation method of semiconductor device
KR970052270A (en) Method for manufacturing micro contact hole of semiconductor device
KR960019515A (en) Contact etching method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application