KR960035810A - Contact formation method of semiconductor device - Google Patents

Contact formation method of semiconductor device Download PDF

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Publication number
KR960035810A
KR960035810A KR1019950004721A KR19950004721A KR960035810A KR 960035810 A KR960035810 A KR 960035810A KR 1019950004721 A KR1019950004721 A KR 1019950004721A KR 19950004721 A KR19950004721 A KR 19950004721A KR 960035810 A KR960035810 A KR 960035810A
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South Korea
Prior art keywords
forming
thin film
contact
pad thin
material layer
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KR1019950004721A
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Korean (ko)
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KR100329070B1 (en
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박철수
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김주용
현대전자산업 주식회사
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Priority to KR1019950004721A priority Critical patent/KR100329070B1/en
Publication of KR960035810A publication Critical patent/KR960035810A/en
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Publication of KR100329070B1 publication Critical patent/KR100329070B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 반도체기판 상부에 형성된 제1물질층 상부에 절연막을 형성하고 상기 제1물질층에 제2물질층을 콘택시키는 공정에 있어서, 최소크기로 설계된 콘택부분의 일측을 오버랩하도록 패드박막을 형성하고 상기 콘택부분을 중심으로 상기 패드박막이 형성된 부분과 반대방향으로부터 상기 패드박막이 형성된 부분으로 콘택마스크를 쉬프트시킨 다음, 상기 콘택마스크와 패드박막을 이용한 식각공정으로 상기 제1물질층을 노출시키는 미세한 콘택홀을 형성하고 상기 제1물질층에 제2물질층을 콘택을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, the method comprising: forming an insulating film on a first material layer formed on a semiconductor substrate and contacting the second material layer on the first material layer, wherein the contact is designed to have a minimum size. A pad thin film is formed to overlap one side of the portion, and the contact mask is shifted from a direction opposite to the portion where the pad thin film is formed around the contact portion to a portion where the pad thin film is formed, and then etched using the contact mask and the pad thin film. By forming a fine contact hole exposing the first material layer in a process and forming a contact with the second material layer in the first material layer, it is possible to improve the characteristics and reliability of the semiconductor device and to achieve high integration of the semiconductor device.

Description

반도체 소자의 콘택 형성방법Contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2c도는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 개략도.2C is a schematic diagram showing a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

Claims (10)

반도체기판 상부에 형성된 제1물질층 상부에 제2물질층을 콘택시키는 반도체소자의 콘택 형성방법에 있어서, 반도체기판 상부에 제1물질층을 형성하는 공정과, 상기 제1물질층 상부에 평탄화된 절연막을 형성하는 공정과, 상기 절연막 상부에 패드박막을 형성하되, 최소크기로 설계된 상기 제1물질층의 콘택 부분을 일측에서 오버랩시켜 형성하는 공정과, 상기 패드박막이 형성된 부분으로 상기 콘택마스크를 쉬프트시켜 감광막패턴을 형성하는 공정과, 상기 감광막패턴과 상기 패드박막을 마스크로하여 상기 절연막을 식각함으로써 상기 제1물질층을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 제2물질층을 상기 제1물질층에 콘택시키는 공정을 포함하는 반도체소자의 콘택 형성방법.A method for forming a contact of a semiconductor device in which a second material layer is contacted on an upper portion of a first material layer formed on a semiconductor substrate, the method comprising: forming a first material layer on an upper portion of the semiconductor substrate; Forming an insulating film, forming a pad thin film on the insulating film, and overlapping a contact portion of the first material layer designed to have a minimum size on one side, and forming the pad thin film on the contact mask. Shifting to form a photoresist pattern, forming a contact hole exposing the first material layer by etching the insulating film using the photoresist pattern and the pad thin film as a mask, and a second material through the contact hole And contacting the layer to the first material layer. 제1항에 있어서, 상기 절연막은 BPSG와 같이 유동성이 우수한 절연물질로 형성된 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 1, wherein the insulating layer is formed of an insulating material having excellent fluidity, such as BPSG. 제1항에 있어서, 상기 패드박막은 상기 절연막과 식각선택비 차이를 갖는 전도물질로 형성된 것을 특징으로하는 반도체소자의 콘택형성방법.The method of claim 1, wherein the pad thin film is formed of a conductive material having an etch selectivity difference from the insulating layer. 제1항에 있어서, 상기 패드박막의 오버랩 정도는 상기 콘택부분 전체폭의 반 미만인 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 1, wherein an overlap degree of the pad thin film is less than half of the entire width of the contact portion. 제1항에 있어서, 상기 콘택마스는 상기 콘택부분 전체폭의 반 미만으로 쉬프트되는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 1, wherein the contact mask is shifted to less than half the entire width of the contact portion. 반도체기판 상부에 워드라인, 불순물 접합영역 및 제1절연막 스페이서를 형성하는 공정과, 전체표면상부에 일정두께 제2절연막을 형성하는 공정과, 전체표면상부를 평탄화시키는 제3절연막을 형성하는 공정과, 상기 제3절연막을 상부에 워드라인을 오버랲하도록 패드박막을 형성하는 공정과, 전체표면상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴과 패드박막을 마스크로하여 상기 불순물 접합영역을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 불순물 접합영역에 도전층을 접속시키는 공정을 포함하는 반도체소자의 콘택 형성방법.Forming a word line, an impurity junction region, and a first insulating film spacer on the semiconductor substrate, forming a second insulating film with a predetermined thickness over the entire surface, and forming a third insulating film for flattening the entire surface; Forming a pad thin film overlying a word line on the third insulating film; forming a photoresist pattern on the entire surface; exposing the impurity junction region by using the photoresist pattern and the pad thin film as a mask; And forming a contact hole to connect the conductive layer to the impurity junction region through the contact hole. 제6항에 있어서, 상기 패드박막은 상기 절연막과 식각선택비의 차이를 갖는 전도물질로 형성된 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 6, wherein the pad thin film is formed of a conductive material having a difference in etching selectivity from the insulating film. 제6항에 있어서, 상기 제3절연막은 BPSG와 같이 유동성을 갖는 절연물질로 형성되는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The contact forming method of claim 6, wherein the third insulating layer is formed of an insulating material having fluidity such as BPSG. 제6항에 있어서, 상기 감광막패턴은 상기 패드박막이 형성된 부분으로 쉬프트된 콘택마스크를 이용한 식각공정으로 형성되는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 6, wherein the photoresist pattern is formed by an etching process using a contact mask shifted to a portion where the pad thin film is formed. 제6항에 있어서, 상기 패드박막과 상기 패드박막의 반대편에 형성된 감광막패턴은 간격을 갖고 형성된 것을 특징으로 하는 반도체소자의 콘택 형성방법.The method of claim 6, wherein the photoresist pattern formed on the opposite side of the pad thin film and the pad thin film is formed at intervals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950004721A 1995-03-08 1995-03-08 Method for forming contact in semiconductor device KR100329070B1 (en)

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KR960035810A true KR960035810A (en) 1996-10-28
KR100329070B1 KR100329070B1 (en) 2002-11-22

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