KR100197116B1 - Method for forming metal wiring in semiconductor device - Google Patents

Method for forming metal wiring in semiconductor device Download PDF

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Publication number
KR100197116B1
KR100197116B1 KR1019950034293A KR19950034293A KR100197116B1 KR 100197116 B1 KR100197116 B1 KR 100197116B1 KR 1019950034293 A KR1019950034293 A KR 1019950034293A KR 19950034293 A KR19950034293 A KR 19950034293A KR 100197116 B1 KR100197116 B1 KR 100197116B1
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South Korea
Prior art keywords
forming
insulating film
layer
metal wiring
interlayer insulating
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KR1019950034293A
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Korean (ko)
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KR970024006A (en
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이원규
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

[청구범위에 기재된 발명이 속한 기술분야][Technical field to which the invention described in the claims belong]

반도체 소자 제조 방법Semiconductor device manufacturing method

[발명이 해결하려고 하는 기술적 과제][Technical Challenges to Invent]

엣치백 공정시 과다 식각 또는 부분적인 과다 식각으로 절연막에 의해 보호된 급속층이 건식식각 공정에서 노출되어 플라즈마에 의한 손상과 오염을 일으킨다는 문제점을 해결하고자 함.In the etching back process, the rapid layer protected by the insulating layer due to over etching or partial over etching is exposed in the dry etching process to cause the damage and contamination by plasma.

[발명의 해결방법의 요지][Summary of the solution of the invention]

금속배선의 평탄화 공정 중에 금속층이 플라즈마에 노출되지 않게 함으로써, 신뢰성 있는 다층금속배선을 형성하고자 함.The metal layer is not exposed to the plasma during the planarization of the metal wiring, thereby forming a reliable multilayer metal wiring.

[발명의 중요한 용도][Important Uses of the Invention]

반도체 소자의 다중금속배선 형성방법에 이용됨.Used in the method of forming multi-metal interconnections of semiconductor devices.

Description

반도체 소자의 다층금속배선 형성 방법Method of forming multi-layer metal wiring of semiconductor device

제1a도 내지 제1c도는 종래의 다층금속배선 형성 방법에 따른 공정도.1a to 1c is a process chart according to the conventional multi-layer metal wiring method.

제2a도 내지 제2d도는 본 발명의 다층금속배선 형성 방법에 따른 공정도.2a to 2d is a process chart according to the method of forming a multi-layer metal wiring of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,11 : 반도체 기판 2,12 : 제1 층간절연막1,11 semiconductor substrate 2,12 first interlayer insulating film

3.13 : 금속층 4,16 : 포토레지스트 패턴3.13 metal layer 4,16 photoresist pattern

14 : 산화막 15 : 질화막14 oxide film 15 nitride film

5,17 : 제2 층간절연막 6,18 : 제3 중간절연막5,17: Second interlayer insulating film 6,18: Third intermediate insulating film

7,19 : 제4 층간절연막7,19: fourth interlayer insulating film

본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로 특히 다층금속배선 구조를 채택하는 반도체 소자의 제조 공정 중 금속배선간의 중간 절연막을 평탄화하는 방법을 개선한 다층금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a multi-layer metal wiring, which is an improvement of a method of planarizing an intermediate insulating film between metal wirings during a manufacturing process of a semiconductor device employing a multi-layer metal wiring structure.

먼저 종래의 다층금속배선 형성 방법을 첨부도면 제1a도 내지 제1c도를 참조하여 살펴보면, 제1a도에 도시된 바와 같이 반도체 기판(1)에 형성된 하부측 패턴 상에 제1 층간절연막(2)이 형성된 구조 상에 금속층(3)을 형성하고 금속라인을 정의하기 위한 포토레지스트 패턴(4)을 형성한다. 그리고 상기 포토레지스트 패턴(4)을 식각 배리어로 이용하여 상기 금속층(3)을 식각한다. 다음으로 제1b도에 도시된 바와 같이 잔류 포토레지스트를 제거하고 제2 층간절연막(5)을 형성한 후 평탄화를 용이하게 하기 위한 제3 층간절연막(6)으로 SOG(Spin On Glass)막을 형성한다. 그리고 상기 금속층이 노출될 때까지 엣치백(etch back) 공정을 실시하여 평탄화 시킨 후 제4층간절연막(7)을 형성한다. 다음으로 제1c도에 도시된 바와 같이 제1a도 내지 제1b도에 도시된 바와 같은 공정을 반복하여 다층배선구조를 이루면 된다. 전술한 바와 같은 종래의 방법에 따르면 엣치백 공정시 과다 식각(overetch)또는 식각 균일도의 차이에 따른 부분적인 과다 식각으로 절연막에 의해 보호된 금속층이 건식식각 공정에서 노출되어 플라즈마에 의한 손상과 오염을 일으키고 플라즈마(plasma)에 의한 차지업(charge-up) 현상에 의하여 소자의 열화현상을 가져온다는 문제점을 가지고 있었다.First, a conventional method of forming a multi-layered metal wiring will be described with reference to FIGS. 1A through 1C. As shown in FIG. 1A, a first interlayer insulating film 2 is formed on a lower side pattern formed on a semiconductor substrate 1. The metal layer 3 is formed on the formed structure and the photoresist pattern 4 for defining the metal line is formed. The metal layer 3 is etched using the photoresist pattern 4 as an etch barrier. Next, as shown in FIG. 1B, the residual photoresist is removed, and a second interlayer insulating film 5 is formed. A spin on glass (SOG) film is formed of the third interlayer insulating film 6 to facilitate planarization. . The planarization process is performed by performing an etch back process until the metal layer is exposed, and then forming a fourth interlayer insulating film 7. Next, as shown in FIG. 1C, the process as shown in FIGS. 1A to 1B may be repeated to form a multilayer wiring structure. According to the conventional method as described above, the metal layer protected by the insulating layer is exposed in the dry etching process by partial overetching due to overetching or difference in etching uniformity during the etching back process, thereby preventing damage and contamination by plasma. And deterioration of the device due to a charge-up phenomenon due to plasma.

따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명은 금속배선의 평탄화 공정 중에 금속층이 플라즈마에 노출되지 않게 함으로써, 신뢰성 있는 다층금속배선을 형성하는 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a reliable multilayer metal wiring by preventing the metal layer from being exposed to plasma during the planarization process of the metal wiring.

본 발명의 반도체 소자의 다층금속배선 형성 방법은, 반도체 기판에 형성된 하부층 패턴 상에 제1 층간 절연막이 형성된 구조 상에 금속층을 형성하고 소정의 두께로 산화막과 질화막을 차례로 형성하는 단계와, 금속라인을 정의하기 위한 포토레지스트 패턴을 형성하는 단계와 , 상기 포토레지스트 패턴을 식각 베이렁로 이용하여 상기 질화막과 상기 산화막 및 상기 금속층을 건식식각한 후 잔류 포토레지스트를 제거하는 단계와, 소정의 두께로 제2 층간절연막을 형성하고 표면 평탄화를 용이하게 하기 위한 제3 층간절연막을 형성하는 단계와, 상기 질화막이 노출될 때까지 평탄화 공정을 수행한 후 제4 층간절연막을 형성하는 단계 및 상기한 전공정을 반복하여 실시하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method of forming a multi-layer metal wiring of the semiconductor device of the present invention comprises the steps of forming a metal layer on a structure in which a first interlayer insulating film is formed on a lower layer pattern formed on a semiconductor substrate, and sequentially forming an oxide film and a nitride film to a predetermined thickness, and a metal line Forming a photoresist pattern to define the photoresist; dry etching the nitride film, the oxide film, and the metal layer by using the photoresist pattern as an etching bayer; and removing residual photoresist to a predetermined thickness. Forming a second interlayer insulating film for forming a second interlayer insulating film and facilitating planarization, performing a planarization process until the nitride film is exposed, and then forming a fourth interlayer insulating film and the foregoing preprocess Characterized in that it comprises a step of performing repeatedly.

이제 본 발명의 다중금속배선 형성방법의 한 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다. 먼저 제2a도 에 도시된 바와 같이 반도체 기판(11)에 형성된 하부층 패턴상에 제1 층간 절연막(12)이 형성된 구조 상에 금속층(13)을 형성하고 약 500Å 내지 약 1000Å 두께의 산화막층(14)과 약 200Å 내지 약 500Å 두께의 질화막(15)을 차례로 형성한다. 그리고 금속라인을 정의하기 위한 포토레지스트 패턴(16)을 형성한다. 다음으로 제2b도에 도시된 바와 같이 상기 포토레지스트 패턴(16)을 식각 베리어로 이용하여 상기 질화막(15)과 상기 산화막(14) 및 상기 금속층(14)을 건식식각한 후 잔류 포토레지스트를 제거한다. 그리고 제2 층간절연막(17)을 형성하고 표면 평탄화를 용이하게 하기 위한 제3 층간 절연막(18)으로 SOG(Spin On Glass)을 도포하거나 플리머(polymer)층 또는 고온 저항성의 절연막층을 형성한다. 다음으로 제2c도에 도시된 바와 같이 상기 질화막이 노출될 때까지 또는 완전히 제거될 때까지 엣치백(etch back)을 실시하여 표면을 평탄화 시킨 후 제4 층간절연막(19)을 형성한다. 이 때 상기 에칫백 공정 대신에 화학적 기계연마 공정을 수행할 수 있다. 다음으로 제2d도에 도시된 바와 같이 제2a도 내지 제2c도에 도시된 바와 같은 공정을 반복하여 다중금속배선 구조를 이룬다.Now with reference to the accompanying drawings, an embodiment of a method for forming a multi-metal wiring of the present invention will be described in detail. First, as shown in FIG. 2A, the metal layer 13 is formed on the structure in which the first interlayer insulating layer 12 is formed on the lower layer pattern formed on the semiconductor substrate 11, and the oxide layer 14 having a thickness of about 500 kV to about 1000 kV is formed. ) And the nitride film 15 having a thickness of about 200 kPa to about 500 kPa is formed in this order. Then, the photoresist pattern 16 for defining the metal line is formed. Next, as shown in FIG. 2B, the photoresist pattern 16 is used as an etching barrier to dry-etch the nitride layer 15, the oxide layer 14, and the metal layer 14, and then remove residual photoresist. do. In addition, a spin on glass (SOG) is applied or a polymer layer or a high temperature resistant insulating layer is formed on the third interlayer insulating layer 18 to form a second interlayer insulating layer 17 and to facilitate surface planarization. . Next, as illustrated in FIG. 2C, the fourth interlayer insulating film 19 is formed after the planarization is performed by etching back until the nitride film is exposed or completely removed. In this case, a chemical mechanical polishing process may be performed instead of the etching back process. Next, as shown in FIG. 2d, the process as shown in FIGS. 2a to 2c is repeated to form a multi-metal wiring structure.

반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 다층금속배선 공정에서 금속라인이 손상되거나 오염되는 것을 방지할 수 있고 플라즈마에 의한 차지업(charge-up)현상을 방지하여 신뢰성 있는 다층금속배선 구조를 형성할 수 있다.In the manufacture of semiconductor devices, according to the present invention as described above, it is possible to prevent the metal line from being damaged or contaminated in the multi-layer metal wiring process, and to prevent charge-up phenomenon by plasma, thereby providing a reliable multilayer metal wiring structure. Can be formed.

Claims (4)

반도체 소자의 다층금속배선 형성 방법에 있어서, 반도체 기판에 형성된 하부층 패턴 상에 제1 층간절연막이 형성된 구조 상에 금속층을 형성하고 소정의 두께로 산화막과 질화막을 차례로 형성하는 단계와, 금속라인을 정의하기 위한 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 베리어로 이용하여 상기 질화막과 상기 산화막 및 상기 금속층을 건식식각한 후 잔류 포토레지스트를 제거하는 단계와, 소정의 두께로 제2 층간절연막을 형성하고 표면 평탄화를 용이하게 하기 위한 제3층간절연막을 형성하는 단계와, 상기 질화막이 노출될 때까지 평탄화 공정을 수행한 후 제4 층간절연막을 형성하는 단계, 및 상기한 전공정을 반복하여 실시하는 단계를 포함하여 이루어진 다층금속배선 형성 방법.A method of forming a multi-layer metal wiring of a semiconductor device, comprising: forming a metal layer on a structure in which a first interlayer insulating film is formed on a lower layer pattern formed on a semiconductor substrate, and sequentially forming an oxide film and a nitride film at a predetermined thickness, and defining a metal line; Forming a photoresist pattern for etching; dry etching the nitride film, the oxide film, and the metal layer by using the photoresist pattern as an etching barrier; and removing residual photoresist, and forming a second interlayer with a predetermined thickness. Forming an insulating film and forming a third interlayer insulating film for facilitating surface planarization, performing a planarization process until the nitride film is exposed, and then forming a fourth interlayer insulating film, and repeating the preceding steps Method for forming a multi-layer metal wiring comprising the step of performing. 제1항에 있어서, 상기 산화막의 두께는 약 500Å 내지 약 1000Å 이고 상기 질화막의 두께는 약 200Å 내지 약 500Å 인 것을 특징으로 하는 다층금속배선 형성 방법.The method of claim 1, wherein the oxide film has a thickness of about 500 kPa to about 1000 kPa and the nitride film has a thickness of about 200 kPa to about 500 kPa. 제1항에 있어서, 상기 제3 층간 절연막은 스핀은글래스와 폴리머와 고온 저항성의 절연막 중 어느 한 물질을 사용하는 것을 특징으로 하는 다층금속배선 형성 방법.The method of claim 1, wherein the third interlayer insulating film is formed of spin silver glass, a polymer, or a high temperature resistant insulating film. 제1항에 있어서, 상기 평탄화 공정은 엣치백 공정 또는 화학적 기계연마 공정 중 어느 한 공정을 실시하는 것을 특징으로 하는 다층금속배선 형성방법.The method of claim 1, wherein the planarization process comprises any one of an etch back process and a chemical mechanical polishing process.
KR1019950034293A 1995-10-06 1995-10-06 Method for forming metal wiring in semiconductor device KR100197116B1 (en)

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KR1019950034293A KR100197116B1 (en) 1995-10-06 1995-10-06 Method for forming metal wiring in semiconductor device

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KR100197116B1 true KR100197116B1 (en) 1999-06-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055768A (en) * 1997-12-27 1999-07-15 김영환 Manufacturing method of semiconductor device
KR100335350B1 (en) * 1999-10-21 2002-05-06 곽정소 a patterning method for multi-metal layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055768A (en) * 1997-12-27 1999-07-15 김영환 Manufacturing method of semiconductor device
KR100335350B1 (en) * 1999-10-21 2002-05-06 곽정소 a patterning method for multi-metal layer

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