CN103187361A - Manufacturing method of copper interconnection layers - Google Patents
Manufacturing method of copper interconnection layers Download PDFInfo
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- CN103187361A CN103187361A CN2011104574463A CN201110457446A CN103187361A CN 103187361 A CN103187361 A CN 103187361A CN 2011104574463 A CN2011104574463 A CN 2011104574463A CN 201110457446 A CN201110457446 A CN 201110457446A CN 103187361 A CN103187361 A CN 103187361A
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- copper interconnection
- interconnection layer
- copper
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- stressor layers
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Abstract
The invention provides a manufacturing method of copper interconnection layers. The manufacturing method of the copper interconnection layers comprises a base. A copper interconnection through groove is formed in the base; the copper interconnection layers are formed in the copper interconnection through groove and on the base; stress layers are formed on the copper interconnection layers; and a thermal annealing technology is conducted so as to repair the copper interconnection layers. The stress layers and the copper interconnection layer on the base are removed, the stress layers are covered on the copper interconnection layers, the thermal annealing technology is conducted so as to ensure that the stress layers produce stress which is acted on the copper interconnection layers, abnormal defects such as protrusions and holes generated in the covering process of the copper interconnection layers are repaired, and therefore electrical connection characteristics of the copper interconnection layers are improved.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, relate in particular to a kind of manufacture method of copper interconnection layer.
Background technology
Copper-connection is the main flow interconnection technique in the present very lagre scale integrated circuit (VLSIC), and electro-coppering is one of critical process in the copper-connection.Copper wiring technique is put forward by IBM as far back as in September, 1997, the mosaic technology of being known as (also claiming Damascus) refers to adopt in the making of semiconductor integrated circuit interconnection layer the copper metal material to replace the novel semi-conductor manufacturing process technology of conventional aluminum interconnect materials.Because the conductance of copper is much higher than aluminium, adopt copper interconnecting line can reduce the thickness of interconnection layer, make that the distributed capacitance between interconnection layer reduces, thereby being improved, frequency becomes possibility.In addition, the integrity problem by the electron transfer initiation under the situation that device density further increases, also can occur, and copper also there is very strong superiority than aluminium in this respect.Therefore copper interconnection layer has obtained application more and more widely in semiconductor device.
Fig. 1 is the structural representation in the manufacture process of copper interconnection layer in the semiconductor device in the prior art, as shown in Figure 1, it forms processing step and comprises: at first at a substrate 10 deposition interlayer dielectric layers 12, then, utilize photoetching and etching technics, in interlayer dielectric layer 12, form the copper-connection groove, then in the copper-connection groove, form barrier layer 14 and copper interconnection layer 16 successively, wherein barrier layer 14 is used on the one hand stopping that copper interconnection layer 16 infiltrates substrate 10 and causes the device short circuit, another conveniently can make copper interconnection layer 16 adhere to better, copper interconnection layer 16 adopts electric plating method to form usually, in the process that forms copper interconnection layer 16, because current density change in the technology, the electroplate liquid change in concentration, and factor affecting such as copper-connection groove depth-to-width ratio is bigger, projection (hillock) as shown in Figure 1 can appear in the copper interconnection layer 16, hole defectives such as (Hole), influence the characteristic that is electrically connected of copper interconnection layer 16, even serious problems such as cause that device opens circuit.
Summary of the invention
The purpose of this invention is to provide a kind of manufacture method that reduces the semiconductor device of copper interconnection layer defective.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of copper interconnection layer, may further comprise the steps: substrate is provided, is formed with the copper-connection groove in the described substrate; In described copper-connection groove and described substrate form copper interconnection layer; Form stressor layers at described copper interconnection layer; Carry out thermal anneal process, so that described copper interconnection layer is repaired; Remove described stressor layers and described suprabasil copper interconnection layer.
Further, described stressor layers is a kind of or its combination in titanium nitride, tantalum nitride, tantalum or the titanium.
Further, described stressor layers adopts chemical vapour deposition (CVD) or physical vaporous deposition to form.
Further, the thickness of described stressor layers is 10nm～150nm.
Further, in carrying out thermal anneal process, the thermal annealing temperature is 200 ℃～600 ℃.
Further, adopt wet etching or dry etching to remove stressor layers, adopt chemical mechanical milling method to remove suprabasil copper interconnection layer.
Further, the etching material of described wet etching comprises hydrogen fluoride, sulfuric acid and hydrogen peroxide.
Further, the etching material of described dry etching comprises methane, helium and chlorine.
Further, described stressor layers and described suprabasil copper interconnection layer all adopt chemical mechanical milling method to remove.
Further, between the step of covering copper interconnection layer and stressor layers, also be included in the step that forms the barrier layer on the described copper interconnection layer, the material on described barrier layer is a kind of or its combination in titanium, tantalum, titanium nitride or the tantalum nitride.
In sum, the manufacture method of copper interconnection layer of the present invention is by covering stressor layers after the covering copper interconnection layer, pass through thermal anneal process, make stressor layers produce compression, act on the copper interconnection layer, unusual defective such as the projection that copper interconnection layer is produced in overwrite procedure, hole is repaired, thereby improves the characteristic that is electrically connected of copper interconnection layer.
Description of drawings
Fig. 1 is the structural representation in the manufacture process of copper interconnection layer in the semiconductor device in the prior art.
Fig. 2 is the schematic flow sheet of the manufacture method of copper interconnection layer in one embodiment of the invention.
Fig. 3～Fig. 8 is the structural representation of the manufacture method of copper interconnection layer in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 2 is the schematic flow sheet of the manufacture method of copper interconnection layer in one embodiment of the invention.The manufacture method of described copper interconnection layer comprises:
Step S01: substrate is provided, is formed with the copper-connection groove in the described substrate;
Step S02: in described copper-connection groove and described substrate form copper interconnection layer;
Step S03: form stressor layers at described copper interconnection layer;
Step S04: carry out thermal anneal process, act on the described copper interconnection layer so that stressor layers produces stress, described copper interconnection layer is repaired;
Step S05: remove described stressor layers and described suprabasil copper interconnection layer.
Fig. 3～Fig. 8 is the structural representation in the manufacture process of copper interconnection layer in the semiconductor device in one embodiment of the invention.Below in conjunction with Fig. 2～Fig. 7, describe the manufacture process of copper interconnection layer in the device of the present invention in detail.
As shown in Figure 3 and Figure 4, in step S01, provide substrate 100, be formed with copper-connection groove 200 in the described substrate 100; Described substrate 100 can be for Semiconductor substrate with active circuit (indicating among the figure) or for can also being preceding one deck copper interconnection layer.
The process that forms current copper interconnection layer in described substrate 100 comprises: at first at substrate 100 deposition interlayer dielectric layers 102, then utilize photoetching and etching technics, in interlayer dielectric layer 102, form copper-connection groove 200, the structure of described copper-connection groove 200 can for example be shown in Figure 3 or be shown in Figure 4, wherein copper-connection groove 200 can be used for the dual damascene metal interconnection structure among Fig. 4, comprise groove and the narrower groove of lower section that the cross section, top is wideer, the metal throuth hole connector of groove in follow-up filling formation copper interconnection layer that lower section is narrower.Briefly clear for describing, following forming process is example with copper-connection groove shown in Figure 3 200.Be understandable that, in the copper-connection groove 200 of other shapes, form copper interconnection layer all within thought range of the present invention.
As shown in Figure 5, in step S02, in described copper-connection groove 200 and described substrate 100 form copper interconnection layers 106, before covering copper interconnection layer 106, can also in described groove, form barrier layer 104, the material on barrier layer 104 can be a kind of or its combination in titanium, tantalum, titanium nitride or the tantalum nitride, and described barrier layer 104 is used on the one hand stopping that follow-up formation copper interconnection layer infiltrates substrate 100 and causes the device short circuit, and another conveniently can make copper interconnection layer adhere to formation better; Then, utilize electric plating method covering copper interconnection layer 106, be covered in substrate 100 and fill copper-connection groove 200 shown in Figure 3.
Committed step of the present invention is that step S03 is to step S05.As shown in Figure 6, in step S03, cover stressor layers 108 at described copper interconnection layer 106, described stressor layers 108 preferable thickness are 10nm～150nm, the material of described stressor layers 108 can be a kind of or its combination in titanium nitride, tantalum nitride, tantalum or the titanium, above-mentioned material and thickness can make stressor layers 108 produce enough stress and act on the copper interconnection layer 106, to repair the defective of copper interconnection layer 106.Wherein said stressor layers 108 can adopt chemical vapour deposition (CVD) or physical vaporous deposition to form, and adopts the stressor layers 108 of titanium, tantalum material can adopt the method for sputter to be formed on the described copper interconnection layer 108; Adopt the stressor layers 108 of titanium nitride or tantalum nitride the nitrogen reaction of titanium source or tantalum source and feeding can be formed titanium nitride or tantalum nitride, and be deposited on the described copper interconnection layer 106, namely form stressor layers 108.
In step S04, carry out thermal anneal process, so that producing stress, stressor layers 108 acts on the described copper interconnection layer 106; Wherein the preferable scope of thermal annealing temperature is 200 ℃～600 ℃, under this temperature range, makes stressor layers 108 can produce the stress effect, and has avoided the device architecture in the too high damage substrate 100 of temperature.In the process that forms copper interconnection layer 106; usually can form defectives such as shown in Figure 5 projection, hole; and in thermal annealing process of the present invention; stressor layers 108 produces compression; act on the copper interconnection layer 106, copper interconnection layer 106 is repaired, thereby reduced defectives such as projection, hole; under preferable situation, form structure as shown in Figure 7.
In step S05, remove in described stressor layers 108 and the described substrate copper interconnection layer 106 beyond 100 the copper-connection groove 200, form structure as shown in Figure 8.In one embodiment, removing described stressor layers 108 can adopt wet etching or dry etching to remove, 106 of copper interconnection layers beyond the copper-connection groove as shown in Figure 3 can adopt chemical mechanical milling method to remove, when using wet etching, the etching material can comprise hydrogen fluoride, sulfuric acid and hydrogen peroxide, uses the etching material of dry etching can comprise methane, helium and chlorine.In another embodiment, the copper interconnection layer 106 beyond described stressor layers and the described copper-connection groove 200 all adopts chemical mechanical milling method to remove, and solves the swap time of different etching and cmp different process step, has improved the technology make efficiency.In addition, be arranged in the process of removing copper interconnection layer at cmp in copper-connection groove 200 barrier layer 104 in addition and remove in the lump, the interlayer dielectric layer 102 beyond the exposed copper interconnection channel 200, the final structure that forms as shown in Figure 8.
On the basis of semiconductor device structure shown in Figure 8, can also continue to adopt the manufacture method of copper interconnection layer of the present invention to form new layer of copper interconnection layer, and finish the manufacture craft of follow-up semiconductor device, the technical method that follow-up semiconductor device fabrication process is well known to those skilled in the art is so repeat no more.
In sum, the manufacture method of copper interconnection layer of the present invention is by covering stressor layers after the covering copper interconnection layer, pass through thermal anneal process, make stressor layers produce compression, act on the copper interconnection layer, unusual defective such as the projection that copper interconnection layer is produced in overwrite procedure, hole is repaired, thereby improves the characteristic that is electrically connected of copper interconnection layer.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. the manufacture method of a copper interconnection layer comprises
Substrate is provided, is formed with the copper-connection groove in the described substrate;
In described copper-connection groove and described substrate form copper interconnection layer;
Form stressor layers at described copper interconnection layer;
Carry out thermal anneal process, so that described copper interconnection layer is repaired;
Remove described stressor layers and described suprabasil copper interconnection layer.
2. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, described stressor layers is a kind of or its combination in titanium nitride, tantalum nitride, tantalum or the titanium.
3. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, described stressor layers adopts chemical vapour deposition (CVD) or physical vaporous deposition to form.
4. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, the thickness of described stressor layers is 10nm～150nm.
5. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, in carrying out thermal anneal process, the thermal annealing temperature is 200 ℃～600 ℃.
6. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, adopts wet etching or dry etching to remove stressor layers, adopts chemical mechanical milling method to remove suprabasil copper interconnection layer.
7. the manufacture method of copper interconnection layer as claimed in claim 6 is characterized in that, the etching material of described wet etching comprises hydrogen fluoride, sulfuric acid and hydrogen peroxide.
8. the manufacture method of copper interconnection layer as claimed in claim 6 is characterized in that, the etching material of described dry etching comprises methane, helium and chlorine.
9. the manufacture method of copper interconnection layer as claimed in claim 1 is characterized in that, described stressor layers and described suprabasil copper interconnection layer all adopt chemical mechanical milling method to remove.
10. as the manufacture method of any described copper interconnection layer in the claim 1 to 9, it is characterized in that, between the step of covering copper interconnection layer and stressor layers, also be included in the step that forms the barrier layer on the described copper interconnection layer, the material on described barrier layer is a kind of or its combination in titanium, tantalum, titanium nitride or the tantalum nitride.
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| CN2011104574463A CN103187361A (en) | 2011-12-31 | 2011-12-31 | Manufacturing method of copper interconnection layers |
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| CN2011104574463A CN103187361A (en) | 2011-12-31 | 2011-12-31 | Manufacturing method of copper interconnection layers |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298662A (en) * | 2015-05-21 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof and electronic installation |
| US9721835B2 (en) | 2015-12-11 | 2017-08-01 | International Business Machines Corporation | Modulating microstructure in interconnects |
| CN107154380A (en) * | 2017-05-11 | 2017-09-12 | 上海华力微电子有限公司 | A kind of preparation method of metal interconnection structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1205547A (en) * | 1997-07-16 | 1999-01-20 | 三菱电机株式会社 | Manufacturing method of semiconductor device having high pressure reflow process and semiconductor device manufactured thereby |
| US5926736A (en) * | 1996-10-30 | 1999-07-20 | Stmicroelectronics, Inc. | Low temperature aluminum reflow for multilevel metallization |
-
2011
- 2011-12-31 CN CN2011104574463A patent/CN103187361A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926736A (en) * | 1996-10-30 | 1999-07-20 | Stmicroelectronics, Inc. | Low temperature aluminum reflow for multilevel metallization |
| CN1205547A (en) * | 1997-07-16 | 1999-01-20 | 三菱电机株式会社 | Manufacturing method of semiconductor device having high pressure reflow process and semiconductor device manufactured thereby |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298662A (en) * | 2015-05-21 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof and electronic installation |
| CN106298662B (en) * | 2015-05-21 | 2019-09-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
| US9721835B2 (en) | 2015-12-11 | 2017-08-01 | International Business Machines Corporation | Modulating microstructure in interconnects |
| CN107154380A (en) * | 2017-05-11 | 2017-09-12 | 上海华力微电子有限公司 | A kind of preparation method of metal interconnection structure |
| CN107154380B (en) * | 2017-05-11 | 2020-04-24 | 上海华力微电子有限公司 | Preparation method of metal interconnection structure |
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Application publication date: 20130703 |