CN103117245A - Formation method of air-gap interconnection structure - Google Patents
Formation method of air-gap interconnection structure Download PDFInfo
- Publication number
- CN103117245A CN103117245A CN 201110365145 CN201110365145A CN103117245A CN 103117245 A CN103117245 A CN 103117245A CN 201110365145 CN201110365145 CN 201110365145 CN 201110365145 A CN201110365145 A CN 201110365145A CN 103117245 A CN103117245 A CN 103117245A
- Authority
- CN
- China
- Prior art keywords
- layer
- air
- formation method
- groove
- interconnect architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a formation method of an air-gap interconnection structure. The formation method includes that a first dielectric layer is deposited on the base layer of a semiconductor integrated circuit, and a second dielectric layer is deposited on the first dielectric layer. Slots are formed on the second dielectric layer, and adjacent two slots are isolated by the second dielectric layer. A barrier layer and a main conducting layer are deposited on the surface of the second dielectric layer surface and inside slots in sequence. The surface of the main conducting layer is in planarization, and the main conducting layer with certain thickness is retained. All main conducting layers other than conducting layers in the slots are removed by the unstressed polishing technology. All barrier layers other than those exposed outside the slots are removed by the unstressed removing barrier layers technology. The second dielectric layer is removed and a groove is formed between the adjacent two slots; a third dielectric layer is deposited on the wall of the groove and on exposed the main conducting layer and the barrier layer which are arranged on. A fourth dielectric layer is deposited on the third dielectric layer and in the slots, and air-gap is formed in the slots. The formation method of the air-gap interconnection structure enables the air-gap interconnection structure to be formed in the semiconductor integrated circuit with an ultra fine feature size structure by utilizing the unstressed polishing technology and unstressed removing barrier layer technology.
Description
Technical field
The present invention is about the manufacture method of semiconductor integrated circuit, especially about a kind of formation method in order to the air-gap interconnect architecture that reduces the capacitance in semiconductor integrated circuit.
Background technology
Along with the development of semi-conductor industry, great scale integrated circuit (VLSI) and very lagre scale integrated circuit (VLSIC) (ULSI) are widely used.Compare integrated circuit in the past, great scale integrated circuit and very lagre scale integrated circuit (VLSIC) have more complicated sandwich construction, less characteristic size.As everyone knows, in resistance-capacitance circuit, circuitous resistance and circuit capacitance have determined the capacitance-resistance sluggish (RCdelay) of circuit, and the energy consumption (E=CV of circuit
2F).So the resistance value of integrated circuit and capacitance have directly determined the performance of integrated circuit, especially ultra tiny characteristic size integrated circuit.Property development greatly existing and very lagre scale integrated circuit (VLSIC) is subject to capacitance-resistance sluggishness and the energy consumption in circuit.In order to reduce capacitance-resistance sluggishness and the energy consumption in circuit, copper (Cu) is due to its higher conductivity, progressively replace aluminium (Al) and consisted of metal structure in integrated circuit, advanced low-k materials (loW-k material, k＜2.5), for example aromatics hydrocarbon thermosettingpolymer (SILK), also be used to replace traditional dielectric material such as SiO
2(k＞4.0).
But because the mechanical strength of low-k dielectric material is very weak, Young's modulus difference with respect to copper is huge, and the mechanical strength of copper interconnect architecture is directly proportional (as shown in Figure 1) to its live width, when using chemical-mechanical planarization (CMP) technique to be planarized to the barrier layer to unnecessary steel structure, its downforce can be destroyed the dielectric layer structure of low-k dielectric material, cause the copper cash short circuit or open circuit, make ic failure, the mechanical performance defective of low-k dielectric material has hindered its being widely used in integrated circuit.
The defective that exists in order to overcome the low-k dielectric material, air-gap (air-gap) interconnection technique is introduced in the integrated circuit interconnect architecture.The air-gap technology, accurately the space in air-gap is the vacuum that there is no air, because common air must comprise moisture, may cause corrosion and the degeneration of copper conductor on every side.The air-gap technology can not change existing dielectric layer material just, do not change under the prerequisite of existing technology and equipment, utilizing permittivity of vacuum is 1 characteristic, reduce significantly the dielectric constant of dielectric layer, indirectly reached the function of low-k dielectric material, the dielectric layer structure that contains air-gap can be considered to contain the dielectric material structure of loose structure.But present air-gap technology such as U.S. Patent number are US 7,501,347, US 7,629,268 and US 7,361,991 etc. disclosed, can only be applied to characteristic size is in the above integrated circuit of 90nm, when the characteristic size of integrated circuit reduces, the technical bottleneck of mechanical stress to copper interconnect architecture injury when traditional Damascus technics (damascene process) also is faced with the planarization of copper interconnect architecture, the stress damage bottleneck of how breaking through in flatening process becomes the key that forms the air-gap technology.
In order to solve mechanical stress in chemical-mechanical planarization technique to the dielectric layer structural damage; in the formation technique of existing air-gap; usually can be used for protecting sacrificial layer material by the hard Protective film of deposit one deck on sacrifice layer; utilize hard Protective film to have very high mechanical strength and resist the mechanical stress that chemical-mechanical planarization technique is brought, hard Protective film is removed subsequently.This kind technique has increased the formation step of air-gap, makes the formation technique of air-gap become complicated.
Simultaneously, for fear of chemical-mechanical planarization technique, copper cash is caused potential injury, a part of dielectric material can be retained the both wings that get off to protect copper cash.Therefore cause air-gap to form in narrow copper cash pitch area, perhaps can only form the air-gap of small volume in narrow copper cash pitch area.Based on this reason, existing air-gap interconnect architecture forms technique and can't be used in the integrated circuit of very small feature size, yet the characteristic size of integrated circuit is less, dielectric constant is more significantly on the electric property impact of circuit, undermost the first metal interconnection structure in interconnect architecture for example, therefore, this technical barrier needs urgent the solution.
Summary of the invention
The objective of the invention is to provide a kind of for the defective that the above-mentioned background technology exists and to form the method for air-gap interconnect architecture in the semiconductor integrated circuit with ultra tiny characteristic size structure.
For achieving the above object, the present invention proposes a kind of formation method of air-gap interconnect architecture, comprises the steps:
Deposit first medium layer on the basalis of semiconductor integrated circuit;
Deposit second medium layer on the first medium layer;
Form groove on the second medium layer, adjacent two grooves are kept apart by the second medium layer;
Barrier layer and main conductive layer successively in the surface of second medium layer and groove;
Main conductive layer is carried out flattening surface, and keep certain thickness main conductive layer;
Adopt non-stress polishing technique removal all main conductive layers except the main conductive layer in groove;
Adopt unstressed removal barrier layer technique to remove to be exposed to all outer barrier layers of groove;
Remove the second medium layer, form a groove between adjacent two grooves;
Deposit the 3rd dielectric layer on groove walls and exposed main conductive layer and barrier layer;
Deposit the 4th dielectric layer in the 3rd dielectric layer and groove, air-gap is formed in groove.
Preferably, described first medium layer can be made of one of SiCN, SiC, SiN and SiOC or their mixture.
Preferably, described second medium layer can be made of ultralow K dielectric material or low-K dielectric material or dielectric material.
Preferably, described dielectric material can be organic material.
Preferably, described organic material can be SiLK.
Preferably, described barrier layer can be made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture.
Preferably, described barrier layer is to adopt sputtering technology to be deposited on the surface and trench wall of second medium layer.
Preferably, described main conductive layer is to be made of copper.
Preferably, adopt the thin Seed Layer of CVD (Chemical Vapor Deposition) method deposit one deck on described barrier layer, then adopt Cu electroplating technique to be deposited on the copper layer on described thin Seed Layer and groove in.
Preferably, adopt the chemico-mechanical polishing flatening process of low downforce to carry out flattening surface to main conductive layer, and keep the main conductive layer of 100nm to 200nm thickness.
Preferably, adopt XeF2 vapor phase etchant technique to remove all barrier layers that are exposed to outside groove.
Preferably, adopt plasma etching process to remove the second medium layer to form described groove, described first medium layer is as etching stopping layer.
Preferably, the characteristic size of described groove is between 10nm to 250nm.
Preferably, described the 3rd dielectric layer can be made of one of SiCN, SiC, SiN, SiOC or their mixture.
Preferably, adopt non-conformal chemical vapor deposition method deposit the 4th dielectric layer.
Preferably, described the 4th dielectric layer can be made of one of SiOF, SiOC or their mixture.
In sum, the formation method of a kind of air-gap interconnect architecture of the present invention is by adopting non-stress polishing to remove unnecessary main conductive layer and unstressed removal unnecessary barrier layer, due to all machinery-free stress generations, thereby can not cause any damage to remaining main conductive layer, barrier layer and dielectric layer in semiconductor integrated circuit especially semiconductor integrated circuit, therefore, described air-gap interconnect architecture can be formed in the semiconductor integrated circuit with ultra tiny characteristic size structure, and for example characteristic size is less than in 65nm and following semiconductor integrated circuit.By forming relatively large described air-gap, further reduce the dielectric constant of semiconductor integrated circuit medium layer, and then reduce the capacitance in semiconductor integrated circuit, to improve the performance of semiconductor integrated circuit.For existing technique, technique of the present invention is simple, does not need to develop new material, and by deposit the 4th dielectric layer, makes the overall structure of semiconductor integrated circuit have good mechanical strength, can bear the pressure of follow-up encapsulation.
Description of drawings
Figure 1 shows that the schematic diagram that concerns of copper line width and its mechanical strength.
Figure 2 shows that the present invention is by the operation cross section schematic diagram after deposit first medium layer, second medium layer, antireflection film and photoetching block mask on the basalis of semiconductor integrated circuit successively.
Figure 3 shows that the present invention carries out graph exposure by operation to the photoetching block mask, and be formed with the cross section schematic diagram after the antireflection film of figure.
Figure 4 shows that the present invention is by the cross section schematic diagram of operation after forming groove on the second medium layer.
Figure 5 shows that the cross section schematic diagram after the present invention is by operation barrier layer successively and main conductive layer.
Figure 6 shows that the present invention by operation the cross section schematic diagram after to the preliminary planarization of main conductive layer surface.
Figure 7 shows that the present invention by operation the cross section schematic diagram after to the planarization of main conductive layer surface non-stress polishing.
Figure 8 shows that the present invention will be exposed to cross section schematic diagram after the outer barrier layer etch of groove by operation.
Figure 9 shows that the present invention removes the second medium layer by operation, and the cross section schematic diagram after deposit the 3rd dielectric layer.
Figure 10 shows that the present invention by operation deposit the 4th dielectric layer, and form the cross section schematic diagram after air-gap.
Embodiment
By describing technology contents of the present invention, structural feature in detail, being reached purpose and effect, below in conjunction with embodiment and coordinate graphic detailed description the in detail.
Please consult successively Fig. 2 to Figure 10, the formation method of a kind of air-gap interconnect architecture of the present invention comprises the steps:
Step 1: deposit first medium layer 302 on the basalis 301 of semiconductor integrated circuit.Described first medium layer 302 can be made of one of SiCN, SiC, SiN and SiOC or their mixture.
Step 2: deposit second medium layer 303 is as sacrifice layer on described first medium layer 302.Described second medium layer 303 can be made of ultralow K dielectric material or low-K dielectric material or dielectric material, and described dielectric material can be organic material, for example the SiLK material.
Step 3: deposit antireflection film 304 on described second medium layer 303.
Step 4: deposit photoetching block mask 305 on described antireflection film 304.
Step 5: described photoetching block mask 305 is carried out graph exposure, be formed with the photoetching block mask of figure, then adopt dry method etch technology with described antireflection film 304 selective removals, make figure be formed at (as shown in Figure 3) on antireflection film 304.
Step 6: will have the photoetching block mask 305 of figure as etching mask, adopt the described second medium layer 303 of dry method etch technology selective removal, form groove 100 on second medium layer 303, adjacent two grooves 100 are kept apart by described second medium layer 303, then described photoetching block mask 305 and described antireflection film 304 are all removed (as shown in Figure 4).
step 7: sputtering deposit barrier layer 306 on the surface of described second medium layer 303 and groove 100 inwalls, described barrier layer 306 can be by tantalum, tantalum nitride, titanium, one of titanium nitride or their mixture consist of, then on described barrier layer 306 and 307 (as shown in Figure 5) of the interior deposit master of groove 100 conductive layer, described main conductive layer 307 can be made of copper, when selecting metallic copper as main conductive layer 307, need first to adopt the thin Seed Layer of CVD (Chemical Vapor Deposition) method deposit one deck on described barrier layer 306, adopting Cu electroplating technique that the copper layer is deposited on described thin Seed Layer reaches in groove 100 again.
Step 8: adopt the chemico-mechanical polishing flatening process of low downforce to carry out polishing to described main conductive layer 307, make main conductive layer 307 part planarizations, and keep certain thickness main conductive layer 307 (as shown in Figure 6), in the present embodiment, preferred main conductive layer 307 is the copper layer, accordingly, the thickness of the copper layer of reservation is that 100nm-200nm is best.
Step 9: all the copper layers (as shown in Figure 7) the copper layer of employing non-stress polishing technique removal in groove 100, described non-stress polishing technique is based on the electrochemical polish principle, the steel structure of the surface of semiconductor integrated circuit that need are polished is as anode, the polishing fluid shower nozzle is as negative electrode, apply a voltage between anode and negative electrode, the polishing fluid shower nozzle is injected into the copper surface with polishing fluid, and copper dissolution is in polishing fluid and be removed.Non-stress polishing technique can the unnecessary steel structure of selective removal, and can not produce erosion and deformation to dielectric layer and barrier layer, thoroughly avoided the damage of mechanical stress to copper, low k dielectric layer and ultralow k dielectric layer, fundamentally solved the technique difficult problem that low-K dielectric material or ultralow K dielectric material and copper are integrated, simultaneously, in the non-stress polishing system, because polishing fluid can be recycled, not only reduced cost but also reduced environmental pollution.
Step 10: adopt unstressed removal barrier layer technique to remove to be exposed to all outer barrier layers 306 of groove 100, and only keep barrier layer 306 (as shown in Figure 8) in groove 100, in the present embodiment, described barrier layer 306 is made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture, therefore, the present embodiment has adopted XeF
2Vapor phase etchant technique is removed all barrier layers 306 that are exposed to outside groove 100, XeF
2Can be spontaneous and the etching chemistry reaction optionally occurs under uniform temperature and pressure condition with the barrier layer 306 that is consisted of by one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture.In the present embodiment, the temperature of etch process can be at 0 ℃ to 300 ℃, and 25 ℃ to 200 ℃ is optimal reaction temperature, XeF
2Gas pressure can be at 0.1Torr to 100Torr, and 0.5Torr to 20Torr is optimum response pressure.XeF
2Has good selectivity for copper with by the second medium layer 303 that dielectric material consists of, especially for take Si-C-O-H as basic material and dielectric constant as 1.2 to 4.2, wherein have better selectivity take dielectric constant as 1.3 to 2.4 as the best second medium layer 303 that consists of again.In whole vapor phase etchant process, machinery-free stress is applied on barrier layer 306 and second medium layer 303, thus for copper film and second medium layer 303 without any injury.And, XeF
2With obtain vapor-phase reactant after the reaction of barrier layer 306, for example Xe and the volatile matter that produces under certain reaction temperature and pressure are fluoridized tantalum, therefore, are attached to the surface of semiconductor integrated circuit without any residuals.
Step 11: adopt plasma etching process to remove second medium layer 303, form a groove 1007 between described adjacent two grooves 100, described first medium layer 302 is as etching stopping layer, and the characteristic size of described groove 1007 can be between between 10nm to 250nm.The plasma reduction gas of selecting in plasma etching process can be NH
3Perhaps H
2Perhaps N
2In etching process, barrier layer 306 and main conductive layer 307 can not be subject to any damage.Then, surface deposition the 3rd dielectric layer 308 at whole semiconductor integrated circuit, described the 3rd dielectric layer 308 covers the surface of whole semiconductor integrated circuit as the sealing medium layer, described the 3rd dielectric layer 308 can consist of (as shown in Figure 9) by one of SiCN, SiC, SiN, SiOC or their mixture.
Step 12: adopt non-conformal CVD (Chemical Vapor Deposition) method deposit the 4th dielectric layer 309 on described the 3rd dielectric layer 308, at the interior formation air-gap 200 of described groove 1007.The size and shape of described air-gap 200 can be optimized according to the size of the characteristic size of semiconductor integrated circuit, with the dielectric constant of the dielectric layer that reduces semiconductor integrated circuit.Described the 4th dielectric layer 309 can be made of one of SiOF, SiOC or their mixture.
From the above, the present invention adopts the non-stress polishing technology to remove unnecessary copper layer and unstressed removal unnecessary barrier layer 306, in implementing this two processing steps process, all machinery-free stress produces, therefore can not cause any damage to remaining copper film, barrier layer and dielectric layer in semiconductor integrated circuit especially semiconductor integrated circuit, therefore, described air-gap 200 can be formed in the semiconductor integrated circuit with ultra tiny characteristic size structure, and for example characteristic size is less than in 65nm and following semiconductor integrated circuit.By forming relatively large described air-gap 200, further reduce the dielectric constant of semiconductor integrated circuit medium layer, and then reduce the capacitance in semiconductor integrated circuit, to improve the performance of semiconductor integrated circuit.For existing technique, technique of the present invention is simple, does not need to develop new material, and by deposit the 4th dielectric layer 309, makes the overall structure of semiconductor integrated circuit have good mechanical strength, can bear the pressure of follow-up encapsulation.
In sum, the formation method of a kind of air-gap interconnect architecture of the present invention is by the explanation of above-mentioned execution mode and correlative type, the exposure that oneself is concrete, full and accurate correlation technique, those skilled in the art can be implemented according to this.And the above embodiment just is used for illustrating the present invention, rather than is used for limiting of the present invention, and interest field of the present invention should be defined by claim of the present invention.Still all should belong to interest field of the present invention as for the change of described component number or the replacement of equivalence element etc. herein.
Claims (16)
1. the formation method of an air-gap interconnect architecture, is characterized in that: comprise the steps:
Deposit first medium layer on the basalis of semiconductor integrated circuit;
Deposit second medium layer on the first medium layer;
Form groove on the second medium layer, adjacent two grooves are kept apart by the second medium layer;
Barrier layer and main conductive layer successively in the surface of second medium layer and groove;
Main conductive layer is carried out flattening surface, and keep certain thickness main conductive layer;
Adopt non-stress polishing technique removal all main conductive layers except the main conductive layer in groove;
Adopt unstressed removal barrier layer technique to remove to be exposed to all outer barrier layers of groove;
Remove the second medium layer, form a groove between adjacent two grooves;
Deposit the 3rd dielectric layer on groove walls and exposed main conductive layer and barrier layer;
Deposit the 4th dielectric layer in the 3rd dielectric layer and groove, air-gap is formed in groove.
2. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described first medium layer can be made of one of SiCN, SiC, SiN and SiOC or their mixture.
3. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: described second medium layer can be made of ultralow K dielectric material or low-K dielectric material or dielectric material.
4. the formation method of air-gap interconnect architecture as claimed in claim 3, it is characterized in that: described dielectric material can be organic material.
5. the formation method of air-gap interconnect architecture as claimed in claim 4, it is characterized in that: described organic material can be SiLK.
6. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described barrier layer can be made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture.
7. the formation method of air-gap interconnect architecture as claimed in claim 6 is characterized in that: described barrier layer is to adopt sputtering technology to be deposited on the surface and trench wall of second medium layer.
8. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described main conductive layer is to be made of copper.
9. the formation method of air-gap interconnect architecture as claimed in claim 8 is characterized in that: adopt the thin Seed Layer of CVD (Chemical Vapor Deposition) method deposit one deck on described barrier layer, then adopt Cu electroplating technique to be deposited on the copper layer on described thin Seed Layer and groove in.
10. the formation method of air-gap interconnect architecture as claimed in claim 1, is characterized in that: adopt the chemico-mechanical polishing flatening process of low downforce to carry out flattening surface to main conductive layer, and keep the main conductive layer of 100nm to 200nm thickness.
11. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt XeF2 vapor phase etchant technique to remove all barrier layers that are exposed to outside groove.
12. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt plasma etching process to remove the second medium layer to form described groove, described first medium layer is as etching stopping layer.
13. the formation method of air-gap interconnect architecture as described in claim 1 or 12 is characterized in that: the characteristic size of described groove is between 10nm to 250nm.
14. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: described the 3rd dielectric layer can be made of one of SiCN, SiC, SiN, SiOC or their mixture.
15. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt non-conformal chemical vapor deposition method deposit the 4th dielectric layer.
16. the formation method of air-gap interconnect architecture as described in claim 1 or 15 is characterized in that: described the 4th dielectric layer can be made of one of SiOF, SiOC or their mixture.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110365145 CN103117245A (en) | 2011-11-17 | 2011-11-17 | Formation method of air-gap interconnection structure |
| TW101102572A TWI608541B (en) | 2011-11-17 | 2012-01-20 | Method for forming air gap interconnect structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110365145 CN103117245A (en) | 2011-11-17 | 2011-11-17 | Formation method of air-gap interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103117245A true CN103117245A (en) | 2013-05-22 |
Family
ID=48415584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110365145 Pending CN103117245A (en) | 2011-11-17 | 2011-11-17 | Formation method of air-gap interconnection structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103117245A (en) |
| TW (1) | TWI608541B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633021A (en) * | 2013-12-02 | 2014-03-12 | 上海华力微电子有限公司 | Method for manufacturing air gap copper interconnecting structure |
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
| CN104916578A (en) * | 2014-03-12 | 2015-09-16 | 台湾积体电路制造股份有限公司 | Air-gap scheme for BEOL process |
| CN105321871A (en) * | 2014-07-29 | 2016-02-10 | 盛美半导体设备（上海）有限公司 | Integration technology of copper and low K dielectric material |
| CN105990131A (en) * | 2015-02-15 | 2016-10-05 | 盛美半导体设备（上海）有限公司 | Integrated processing method for semiconductor structure |
| CN106340504A (en) * | 2015-07-07 | 2017-01-18 | 旺宏电子股份有限公司 | Semiconductor element |
| CN106463455A (en) * | 2014-07-08 | 2017-02-22 | 盛美半导体设备（上海）有限公司 | Method for forming metal interconnection |
| CN108321118A (en) * | 2018-04-04 | 2018-07-24 | 睿力集成电路有限公司 | The preparation method and semiconductor devices in conductive inter-level dielectric cavity |
| WO2022048212A1 (en) * | 2020-09-02 | 2022-03-10 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method therefor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI571999B (en) * | 2015-07-03 | 2017-02-21 | 旺宏電子股份有限公司 | Semiconductor device |
| JP6434877B2 (en) | 2015-08-26 | 2018-12-05 | 東芝メモリ株式会社 | Semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7544606B2 (en) * | 2005-06-01 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to implement stress free polishing |
| US7560380B2 (en) * | 2006-10-27 | 2009-07-14 | Intel Corporation | Chemical dissolution of barrier and adhesion layers |
| JP5329786B2 (en) * | 2007-08-31 | 2013-10-30 | 株式会社東芝 | Polishing liquid and method for manufacturing semiconductor device |
| JP5412517B2 (en) * | 2008-08-20 | 2014-02-12 | エーシーエム リサーチ （シャンハイ） インコーポレーテッド | Barrier layer removal method and apparatus |
| CN101882595B (en) * | 2009-05-08 | 2014-07-09 | 盛美半导体设备（上海）有限公司 | Method and device for removing barrier layer |
| US7956463B2 (en) * | 2009-09-16 | 2011-06-07 | International Business Machines Corporation | Large grain size conductive structure for narrow interconnect openings |
| DE102010001400B4 (en) * | 2010-01-29 | 2019-12-05 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | SOI semiconductor device with reduced topography over a substrate window area |
-
2011
- 2011-11-17 CN CN 201110365145 patent/CN103117245A/en active Pending
-
2012
- 2012-01-20 TW TW101102572A patent/TWI608541B/en active
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
| CN103633021B (en) * | 2013-12-02 | 2015-12-30 | 上海华力微电子有限公司 | A kind of method preparing air gap copper interconnection structure |
| CN103633021A (en) * | 2013-12-02 | 2014-03-12 | 上海华力微电子有限公司 | Method for manufacturing air gap copper interconnecting structure |
| CN104916578B (en) * | 2014-03-12 | 2018-08-28 | 台湾积体电路制造股份有限公司 | Air gap scheme for BEOL techniques |
| CN104916578A (en) * | 2014-03-12 | 2015-09-16 | 台湾积体电路制造股份有限公司 | Air-gap scheme for BEOL process |
| US10062603B2 (en) | 2014-03-12 | 2018-08-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air-gap scheme for BEOL process |
| CN106463455B (en) * | 2014-07-08 | 2019-02-15 | 盛美半导体设备（上海）有限公司 | A method of forming metal interconnection structure |
| CN106463455A (en) * | 2014-07-08 | 2017-02-22 | 盛美半导体设备（上海）有限公司 | Method for forming metal interconnection |
| KR20170030522A (en) * | 2014-07-08 | 2017-03-17 | 에이씨엠 리서치 (상하이) 인코포레이티드 | Method for forming metal interconnection |
| KR102247940B1 (en) | 2014-07-08 | 2021-05-07 | 에이씨엠 리서치 (상하이) 인코포레이티드 | Method for forming metal interconnection |
| CN105321871A (en) * | 2014-07-29 | 2016-02-10 | 盛美半导体设备（上海）有限公司 | Integration technology of copper and low K dielectric material |
| CN105990131A (en) * | 2015-02-15 | 2016-10-05 | 盛美半导体设备（上海）有限公司 | Integrated processing method for semiconductor structure |
| CN106340504A (en) * | 2015-07-07 | 2017-01-18 | 旺宏电子股份有限公司 | Semiconductor element |
| CN106340504B (en) * | 2015-07-07 | 2019-03-15 | 旺宏电子股份有限公司 | Semiconductor element |
| CN108321118A (en) * | 2018-04-04 | 2018-07-24 | 睿力集成电路有限公司 | The preparation method and semiconductor devices in conductive inter-level dielectric cavity |
| CN108321118B (en) * | 2018-04-04 | 2023-10-13 | 长鑫存储技术有限公司 | Method for preparing dielectric cavity between conductive layers and semiconductor device |
| WO2022048212A1 (en) * | 2020-09-02 | 2022-03-10 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201322334A (en) | 2013-06-01 |
| TWI608541B (en) | 2017-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103117245A (en) | Formation method of air-gap interconnection structure | |
| CN101299419B (en) | Semiconductor device and manufacture method thereof | |
| US10937694B2 (en) | Chamferless via structures | |
| CN100514597C (en) | Manufacturing method for IC with air interval | |
| US6503827B1 (en) | Method of reducing planarization defects | |
| US20210036053A1 (en) | Semiconductor memory device | |
| US7119008B2 (en) | Integrating metal layers with ultra low-K dielectrics | |
| KR101842903B1 (en) | Method for forming air gap interconnect structure | |
| US20190229015A1 (en) | Semiconductor interconnect structure and manufacturing method thereof | |
| CN102054748A (en) | Formation method of copper interconnection and processing method of dielectric layer | |
| TW567530B (en) | Manufacturing method semiconductor integrated circuit including simultaneous formation of via hole reaching metal wiring and concave groove in interlayer film and semiconductor integrated circuit manufactured with the manufacturing method | |
| US10297532B2 (en) | Stacked interconnect structure and method of making the same | |
| CN102054754A (en) | Manufacturing method for metal interconnection line | |
| CN102403263B (en) | Trench etching method in double Damascus structure | |
| CN104851835A (en) | Metal interconnection structure and forming method thereof | |
| CN102339790A (en) | Manufacture method of semiconductor device | |
| CN102693935A (en) | Manufacturing method of interconnection structure | |
| US7341940B2 (en) | Method for forming metal wirings of semiconductor device | |
| CN105826279A (en) | Semiconductor structure and formation method thereof | |
| CN102361019A (en) | Method for manufacturing semiconductor device | |
| CN102339793A (en) | Manufacture method of semiconductor device | |
| US20120012979A1 (en) | Semiconductor capacitor | |
| CN102969270A (en) | Semiconductor device and production method thereof | |
| KR100955838B1 (en) | Semiconductor device and method for forming metal line in the same | |
| TW201725655A (en) | Method for forming metal interconnection structure preventing barrier layer deposited on sidewall of trench from being over-etched |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130522 |