TW201322334A - Method for forming air gap interconnection structure - Google Patents

Abstract

The present invention discloses a method for forming an air gap interconnection structure. The method comprises: depositing a first medium layer on the substrate layer of a semiconductor integrated circuit; depositing a second medium layer on the first medium layer; forming trenches on the second medium layer in which two adjacent trenches are separated by the second medium layer; depositing a block layer and a main conductive layer at the surface of the second medium layer and in the trenches sequentially; performing planarization to the surface of the main conductive layer and keeping the main conductive layer with a certain amount of thickness; using a stress-free polish process to remove all of the main conductive layer except the portion in the trenches; using a stress-free block layer removal process to remove all of the block layer exposed outside the trenches; removing the second medium layer and forming a concave trench between two adjacent trenches; depositing a third medium layer on the concave trench walls, the exposed main conductive layer and the block layer; and depositing a fourth medium layer on the third medium layer and in the concave trenches so as to form air gaps in the concave trenches. This invention uses the stress-free polish process and the stress-free block layer removal process to allow said air gap interconnection structure to be formed in the semiconductor integrated circuit with an ultra fine feature-size structure.

Description

Method for forming air gap interconnection structure

The present invention relates to a method of fabricating a semiconductor integrated circuit, and more particularly to a method of forming an air gap interconnect structure for reducing a capacitance value in a semiconductor integrated circuit.

According to the development of the semiconductor industry, very large integrated circuits (VLSI) and ultra large integrated circuits (ULSI) have been widely used. Compared with the conventional integrated circuit, the maximal integrated circuit and the ultra-large integrated circuit have a more complicated multi-layer structure and a smaller feature size. It is well known that in a RC circuit, the circuit resistance and circuit capacitance determine the RC delay of the circuit and the energy consumption of the circuit (E = CV2 f ). Therefore, the resistance value and capacitance value of the integrated circuit directly determine the performance of the integrated circuit, especially the ultra-fine feature size integrated circuit. The performance development of existing very large and very large integrated circuits is limited by the resistance delay and energy consumption in the circuit. In order to reduce the RC hysteresis and energy consumption in the circuit, copper (Cu) has gradually replaced aluminum (Al) to form the metal structure in the integrated circuit due to its higher conductivity, low dielectric constant material (low- k material, k < 2.5), such as aromatic, hydrocarbon thermosetting polymer (SILK), is also used to replace traditional dielectric materials such as SiO2 (k>4.0).

However, due to the weak mechanical strength of the low-k dielectric material, the Young's modulus is quite different from that of copper, and the mechanical strength of the copper interconnect structure is proportional to its line width (as shown in the first figure) when using chemical mechanical flatness. When the (CMP) process planarizes the excess copper structure to the barrier layer, the downforce will destroy the dielectric layer structure of the low-k dielectric material, causing the copper wire to be short-circuited or broken, causing the integrated circuit to fail, low-k medium. Defects in the mechanical properties of materials hinder their widespread use in integrated circuits.

In order to overcome the shortcomings of low-k dielectric materials, air-gap interconnect technology has been introduced into integrated circuit interconnect structures. Air gap technology, precisely the space inside the air gap is a vacuum without air, because ordinary air must contain moisture, which may cause corrosion and degradation of the surrounding copper wire. The air gap technology can precisely reduce the dielectric constant of the dielectric layer by indirectly changing the dielectric constant of the dielectric layer without changing the existing dielectric layer material without changing the existing process technology and equipment, and indirectly achieves low- The function of the k dielectric material, the dielectric layer structure containing the air gap can be considered as a dielectric material structure containing a porous structure. However, the current air gap technology, as disclosed in U.S. Patent Nos. 7,501,347, US 7,629,268, and US 7,361,991, can only be applied to an integrated circuit having a feature size of 90 nm or more. When the feature size of the integrated circuit is reduced, the conventional The damascene process also faces the technical bottleneck of mechanical stress on the copper interconnect structure when the copper interconnect structure is flattened. How to break through the stress damage bottleneck in the planarization process becomes the key to form the air gap technology.

In order to solve the damage of the dielectric layer structure caused by the mechanical stress in the chemical mechanical planarization process, in the formation process of the existing air gap, a hard shielding film is usually deposited on the sacrificial layer to protect the sacrificial layer material, and the hard shielding film is utilized. It has a high mechanical strength to withstand the mechanical stresses caused by the chemical mechanical planarization process, and then the hard mask film is removed. This process increases the step of forming the air gap, complicating the formation process of the air gap.

At the same time, in order to avoid potential damage to the copper wire caused by the chemical mechanical planarization process, a portion of the dielectric material is retained to protect the two wings of the copper wire. As a result, the air gap cannot be formed in the narrow copper line spacing region, or a small volume air gap can be formed only in the narrow copper line spacing region. For this reason, the existing air gap interconnect structure forming process cannot be applied to an integrated circuit of extremely small feature size. However, the smaller the feature size of the integrated circuit, the more significant the influence of the dielectric constant on the electrical performance of the circuit, such as the interconnect structure. The first metal interconnect structure in the lowermost layer, therefore, this technical problem needs to be urgently solved.

SUMMARY OF THE INVENTION The object of the present invention is to provide a method of forming an air gap interconnect structure in a semiconductor integrated circuit having an ultrafine feature size structure in view of the above-described deficiencies of the prior art.

To achieve the above object, a method for forming an air gap interconnection structure according to the present invention includes the steps of: depositing a first dielectric layer on a base layer of a semiconductor integrated circuit; and depositing a second dielectric layer on the first dielectric layer Forming a trench on the second dielectric layer, the adjacent two trenches being separated by the second dielectric layer; sequentially depositing a barrier layer and a main conductive layer on the surface of the second dielectric layer and the trench; performing the main conductive layer The surface is flattened, and a main conductive layer of a certain thickness is retained; all main conductive layers except the main conductive layer in the trench are removed by a stress-free polishing process; and all barriers exposed outside the trench are removed by a stress-free removal barrier process a layer; a second dielectric layer is removed, a recess is formed between adjacent trenches; a third dielectric layer is deposited on the trench walls and the exposed main conductive layer and the barrier layer; and the third dielectric layer and the recess are formed A fourth dielectric layer is deposited therein, and an air gap is formed in the recess.

Preferably, the first dielectric layer may be composed of one of SiCN, SiC, SiN and SiOC or a mixture thereof.

Preferably, the second dielectric layer may be composed of an ultra-low K dielectric material or a low-k dielectric material or a dielectric material.

Preferably, the dielectric material may be an organic material.

Preferably, the organic material may be SiLK.

Preferably, the barrier layer may be composed of one of tantalum, tantalum nitride, titanium, titanium nitride or a mixture thereof.

Preferably, the barrier layer is deposited on the surface of the second dielectric layer and the inner wall of the trench by a sputtering process.

Preferably, wherein the main conductive layer is composed of copper.

Preferably, a thin seed layer is deposited on the barrier layer by chemical vapor deposition, and a copper layer is deposited on the thin seed layer and in the trench by an electrochemical copper plating process.

Preferably, the chemical mechanical polishing planarization process using a low downforce planarizes the surface of the main conductive layer and retains the main conductive layer having a thickness of 100 nm to 200 nm.

Preferably, wherein the XeF2 vapor phase etching process is used to remove all barrier layers exposed outside the trench.

Preferably, wherein the second dielectric layer is removed by a plasma etching process to form the recess, and the first dielectric layer serves as an etch stop layer.

Preferably, wherein the groove has a feature size between 10 nm and 250 nm.

Preferably, the third dielectric layer may be composed of one of SiCN, SiC, SiN, SiOC or a mixture thereof.

Preferably, the fourth dielectric layer is deposited by a non-conformal chemical vapor deposition process.

Preferably, the fourth dielectric layer may be composed of one of SiOF, SiOC or a mixture thereof.

As described above, the method for forming the air gap interconnection structure of the present invention removes the excess main conductive layer by using stress-free polishing and removes the excess barrier layer without stress, since no mechanical stress is generated, and thus the semiconductor integrated circuit is not particularly The main conductive layer, the barrier layer and the dielectric layer remaining in the semiconductor integrated circuit cause any damage, and therefore, the air gap interconnection structure can be formed in a semiconductor integrated circuit having an ultrafine feature size structure, for example, a feature size of less than 65 nm and In the following semiconductor integrated circuits. By forming a relatively large air gap, the dielectric constant of the dielectric layer in the semiconductor integrated circuit is further reduced, thereby reducing the capacitance value in the semiconductor integrated circuit to improve the performance of the semiconductor integrated circuit. Compared with the prior art, the process of the invention is simple, no need to develop new materials, and by depositing the fourth dielectric layer, the overall structure of the semiconductor integrated circuit has good mechanical strength and can withstand the pressure of subsequent packaging.

In order to explain the technical content, structural features, objectives and effects of the present invention in detail, the following detailed description is given by way of example.

Referring to FIG. 2 to FIG. 10 in sequence, the method for forming an air gap interconnection structure of the present invention includes the following steps:

Step 1: Depositing a first dielectric layer 302 on the base layer 301 of the semiconductor integrated circuit. The first dielectric layer 302 may be composed of one of SiCN, SiC, SiN, and SiOC or a mixture thereof.

Step 2: depositing a second dielectric layer 303 as a sacrificial layer on the first dielectric layer 302. The second dielectric layer 303 may be composed of an ultra-low K dielectric material or a low-K dielectric material or a dielectric material, which may be an organic material such as a SiLK material.

Step 3: depositing an anti-reflection film 304 on the second dielectric layer 303.

Step 4: depositing a lithography blocking mask 305 on the anti-reflection film 304.

Step 5: performing pattern exposure on the lithography barrier mask 305 to form a patterned lithography blocking mask, and then selectively removing the anti-reflection film 304 by a dry etching process to form a pattern on the anti-reflection film. On 304 (as shown in the third figure).

Step 6: using the patterned lithography barrier mask 305 as an etch mask, selectively removing the second dielectric layer 303 by a dry etching process, forming a trench 100 on the second dielectric layer 303, adjacent to the two trenches The trench 100 is isolated by the second dielectric layer 303, and then the lithography blocking mask 305 and the anti-reflective film 304 are all removed (as shown in the fourth figure).

Step 7: sputter depositing a barrier layer 306 on the surface of the second dielectric layer 303 and the inner wall of the trench 100, and the barrier layer 306 may be one of tantalum, tantalum nitride, titanium, titanium nitride or The mixture is formed, and then a main conductive layer 307 is deposited on the barrier layer 306 and in the trench 100 (as shown in FIG. 5). The main conductive layer 307 may be composed of copper when metal copper is selected as the main conductive In the case of layer 307, a thin seed layer is first deposited on the barrier layer 306 by chemical vapor deposition, and a copper layer is deposited on the thin seed layer and the trench 100 by an electrochemical copper plating process. Inside.

Step 8: polishing the main conductive layer 307 by a low-pressure chemical mechanical polishing planarization process to partially planarize the main conductive layer 307 and retain a certain thickness of the main conductive layer 307 (as shown in FIG. 6). In the present embodiment, the preferred main conductive layer 307 is a copper layer, and correspondingly, the thickness of the remaining copper layer is preferably from 100 nm to 200 nm.

Step 9: removing all copper layers except the copper layer in the trench 100 by using a stress-free polishing process (as shown in the seventh figure), which is based on the principle of electrochemical polishing, and the semiconductor to be polished The copper structure on the surface of the integrated circuit serves as an anode, and the polishing liquid nozzle serves as a cathode. A voltage is applied between the anode and the cathode. The polishing liquid nozzle sprays the polishing liquid onto the copper surface, and the copper is dissolved in the polishing liquid and removed. The stress-free polishing process selectively removes excess copper structure and does not cause erosion and deformation of the dielectric layer and the barrier layer, completely avoiding damage of copper, low-k dielectric layer and ultra-low-k dielectric layer by mechanical stress. The process problem of integrating low-k dielectric material or ultra-low-k dielectric material with copper is solved, and in the unstressed polishing system, since the polishing liquid can be recycled, the cost is reduced and the environmental pollution is reduced.

Step 10: removing all barrier layers 306 exposed outside the trenches 100 using a stress free removal barrier process, leaving only the barrier layer 306 in the trenches 100 (as shown in the eighth figure), in this embodiment, The barrier layer 306 is composed of one of tantalum, tantalum nitride, titanium, titanium nitride or a mixture thereof. Therefore, the present embodiment employs a XeF2 vapor phase etching process to remove all barrier layers 306 exposed outside the trench 100, XeF2. The barrier layer 306, which is composed of one of tantalum, tantalum nitride, titanium, titanium nitride, or a mixture thereof, spontaneously and selectively undergoes an etch chemistry under certain temperature and pressure conditions. In this embodiment, the temperature of the etching process may be from 0 ° C to 300 ° C, 25 ° C to 200 ° C is the optimum reaction temperature, and the XeF 2 gas pressure may be from 0.1 Torr to 100 Torr, and the optimum reaction pressure is from 0.5 Torr to 20 Torr. . XeF2 has good selectivity for copper and the second dielectric layer 303 composed of a dielectric material, especially for Si-COH as a base material and a dielectric constant of 1.2 to 4.2, wherein the dielectric constant is 1.3 to 2.4. The second dielectric layer 303, which is preferably constructed, has better selectivity. No mechanical stress is applied to the barrier layer 306 and the second dielectric layer 303 throughout the vapor phase etching process, so there is no damage to the copper film and the second dielectric layer 303. Further, XeF2 reacts with the barrier layer 306 to obtain a gas phase reactant such as Xe and a volatile barium fluoride which is generated at a certain reaction temperature and pressure, and therefore, no residual substance adheres to the surface of the semiconductor integrated circuit.

Step 11: removing the second dielectric layer 303 by a plasma etching process, forming a recess 1007 between the adjacent trenches 100, the first dielectric layer 302 serving as an etch stop layer, and the features of the recess 1007 The size can be between 10 nm and 250 nm. The plasma reducing gas selected in the plasma etching process may be NH3 or H2 or N2. The barrier layer 306 and the main conductive layer 307 are not subjected to any damage during the etching process. Next, a third dielectric layer 308 is deposited over the surface of the entire semiconductor integrated circuit, the third dielectric layer 308 covering the surface of the entire semiconductor integrated circuit as a sealing dielectric layer, which may be made of SiCN, One of SiC, SiN, SiOC or a mixture thereof (as shown in Figure IX).

Step 12: depositing a fourth dielectric layer 309 on the third dielectric layer 308 by non-conformal chemical vapor deposition, and forming an air gap 200 in the recess 1007 (as shown in FIG. 10). The size and shape of the air gap 200 can be optimized according to the size of the feature size of the semiconductor integrated circuit to reduce the dielectric constant of the dielectric layer of the semiconductor integrated circuit. The fourth dielectric layer 309 may be composed of one of SiOF, SiOC, or a mixture thereof.

It can be seen from the above that the present invention uses the stress-free polishing technique to remove the excess copper layer and the stress-free removal of the excess barrier layer 306. During the implementation of the two process steps, no mechanical stress is generated, so that the semiconductor integrated circuit, especially the semiconductor, is not The remaining copper film, barrier layer and dielectric layer in the integrated circuit cause any damage, and therefore, the air gap 200 can be formed in a semiconductor integrated circuit having an ultra-fine feature size structure, such as a semiconductor having a feature size of less than 65 nm and below. In the integrated circuit. By forming the relatively large air gap 200, the dielectric constant of the dielectric layer in the semiconductor integrated circuit is further reduced, thereby reducing the capacitance value in the semiconductor integrated circuit to improve the performance of the semiconductor integrated circuit. Compared with the prior art, the process of the invention is simple, no need to develop new materials, and by depositing the fourth dielectric layer 309, the overall structure of the semiconductor integrated circuit has good mechanical strength and can withstand the pressure of subsequent packaging.

The method for forming the air-gap interconnect structure of the present invention has been specifically and specifically disclosed by the above-described embodiments and related drawings, so that those skilled in the art can implement it. The above-mentioned embodiments are only intended to illustrate the invention, and are not intended to limit the invention, and the scope of the invention should be defined by the scope of the invention. Changes in the number of elements or substitution of equivalent elements herein are still within the scope of the invention.

301. . . Base layer

302. . . First dielectric layer

303. . . Second dielectric layer

304. . . Anti-reflection film

305. . . Lithography blocking mask

306. . . Barrier layer

307. . . Main conductive layer

308. . . Third dielectric layer

309. . . Fourth dielectric layer

100. . . Trench

1007. . . Groove

200. . . Air gap

The first figure shows the relationship between the width of the copper wire and its mechanical strength.

The second figure shows a cross-sectional view of the first dielectric layer, the second dielectric layer, the anti-reflection film and the lithographic barrier mask deposited on the underlying layer of the semiconductor integrated circuit in sequence according to the present invention.

The third figure shows a cross-sectional view of the etch stop mask in accordance with the process of the present invention and a patterned anti-reflection film.

The fourth figure shows a schematic cross-sectional view of the present invention after forming a trench on the second dielectric layer in the process.

The fifth figure shows a cross-sectional view of the present invention in which the barrier layer and the main conductive layer are sequentially deposited in the process.

Fig. 6 is a schematic cross-sectional view showing the surface of the main conductive layer in a preliminary planarization process according to the present invention.

FIG. 7 is a schematic cross-sectional view showing the surface of the main conductive layer without stress polishing and planarizing according to the process of the present invention.

Figure 8 is a schematic cross-sectional view showing the etching of the barrier layer exposed outside the trench in accordance with the present invention.

Figure 9 is a cross-sectional view showing the second dielectric layer removed by a process in the present invention and after depositing a third dielectric layer.

Figure 10 is a schematic cross-sectional view showing the fourth dielectric layer deposited in the process of the present invention and forming an air gap.

301. . . Base layer

302. . . First dielectric layer

306. . . Barrier layer

307. . . Main conductive layer

308. . . Third dielectric layer

309. . . Fourth dielectric layer

200. . . Air gap

Claims (16)

A method of forming an air gap interconnect structure includes the steps of: depositing a first dielectric layer on a base layer of a semiconductor integrated circuit; depositing a second dielectric layer on the first dielectric layer; forming a trench on the second dielectric layer a groove, the adjacent two trenches are separated by the second dielectric layer; a barrier layer and a main conductive layer are sequentially deposited on the surface and the trench of the second dielectric layer; the main conductive layer is planarized and retained to a certain thickness a main conductive layer; removing all main conductive layers except the main conductive layer in the trench by a stress-free polishing process; removing all barrier layers exposed outside the trench by a stress-free removal barrier process; removing the second dielectric layer, Forming a groove between two adjacent grooves; depositing a third dielectric layer on the groove wall and the exposed main conductive layer and the barrier layer; depositing a fourth dielectric layer in the third dielectric layer and the groove, air A gap is formed in the groove. The method of forming an air gap interconnection structure according to claim 1, wherein the first dielectric layer may be composed of one of SiCN, SiC, SiN, and SiOC or a mixture thereof. The method of forming an air gap interconnection structure according to claim 1, wherein the second dielectric layer may be composed of an ultra-low K dielectric material or a low-k dielectric material or a dielectric material. The method of forming an air gap interconnection structure according to claim 3, wherein the dielectric material may be an organic material. The method of forming an air gap interconnect structure according to claim 4, wherein the organic material may be SiLK. The method of forming an air gap interconnection structure according to claim 1, wherein the barrier layer may be composed of one of tantalum, tantalum nitride, titanium, titanium nitride or a mixture thereof. The method of forming an air gap interconnect structure according to claim 6, wherein the barrier layer is deposited on a surface of the second dielectric layer and an inner wall of the trench by a sputtering process. The method of forming an air gap interconnection structure according to claim 1, wherein the main conductive layer is made of copper. The method for forming an air gap interconnection structure according to claim 8, wherein a thin seed layer is deposited on the barrier layer by chemical vapor deposition, and the copper layer is deposited by an electrochemical copper plating process. Accumulated on the thin seed layer and in the trench. The method for forming an air gap interconnection structure according to claim 1, wherein the surface of the main conductive layer is planarized by a chemical mechanical polishing planarization process using a low downforce, and a main conductive layer having a thickness of 100 nm to 200 nm is retained. . The method of forming an air gap interconnect structure according to claim 1, wherein the XeF2 vapor phase etching process is used to remove all barrier layers exposed outside the trench. The method of forming an air gap interconnect structure according to claim 1, wherein the second dielectric layer is removed by a plasma etching process to form the recess, and the first dielectric layer serves as an etch stop layer. The method for forming an air gap interconnection structure according to claim 1 or claim 12, wherein the groove has a feature size of between 10 nm and 250 nm. The method of forming an air gap interconnect structure according to claim 1, wherein the third dielectric layer may be composed of one of SiCN, SiC, SiN, SiOC or a mixture thereof. The method of forming an air gap interconnect structure according to claim 1, wherein the fourth dielectric layer is deposited by a non-conformal chemical vapor deposition process. The method of forming an air gap interconnection structure according to claim 1 or claim 15, wherein the fourth dielectric layer may be composed of one of SiOF, SiOC or a mixture thereof.