TWI697983B - Method for forming metal interconnection structure - Google Patents

Abstract

The present invention provides a method for forming a metal interconnection structure to prevent the barrier layer on the sidewall of the recessed area from being over-etched. The method includes the following steps: forming a recessed area on the hard mask layer and the dielectric layer; depositing a barrier layer on the hard mask layer, the sidewall of the recessed area, and the bottom of the recessed area; depositing metal on the barrier layer and making The recessed area is filled with metal; the electro-polishing process is used to remove the metal on the non-recessed area, and the metal in the recessed area is over-polished to form a recess. During the electro-polishing process, an oxide film is formed on the barrier layer; the hard mask is removed The oxide film on the barrier layer on the layer, leaving a certain thickness of the oxide film on the barrier layer on the sidewall of the recessed area; the barrier layer and the hard mask layer are removed by etching, which has a high selectivity ratio to the oxide film, The remaining oxide film prevents the barrier layer on the sidewall of the recessed area from being overetched.

Description

Method for forming metal interconnection structure

The present invention relates to the field of semiconductor device manufacturing, in particular to a method for forming a metal interconnection structure to avoid over-etching of the barrier layer deposited on the sidewall of the trench.

With the rapid development of semiconductor device manufacturing processes, the integration of semiconductor devices is getting higher and higher, and metal interconnect structures of two or more layers are widely used. The existing metal interconnect structure is made of aluminum. However, as the feature size of semiconductor devices becomes smaller and smaller, the influence of RC delay on the performance of semiconductor devices becomes more and more obvious. In order to reduce the RC delay effect, copper is often used instead of aluminum to make interconnect structures because of its lower resistance than aluminum. In addition, low-k materials are used instead of traditional dielectric materials as the dielectric layer in the interconnect structure to reduce parasitic capacitance.

As shown in FIGS. 1(a) to 1(c), a method for forming a copper interconnect structure generally includes the following steps: providing a substrate 101, such as a wafer; depositing a dielectric layer 102 on the substrate 101; A hard mask layer 103 is deposited on 102; a plurality of trenches 106 are formed on the dielectric layer 102 and the hard mask layer 103, and the trenches 106 are shown in Figure 1 (a) to Figure 1 (c); in the hard mask layer Depositing a barrier layer 104 on 103 and on the sidewalls and bottom of the trench 106; A copper seed layer is deposited on the barrier layer 104 and the sidewalls and bottom of the trench 106, and the copper seed layer is deposited on the barrier layer 104; copper 105 is deposited on the copper seed layer and in the trench 106, and the trench 106 is filled with copper 105 ; Remove the copper 105 deposited on the non-recessed area, and the copper 105 remaining in the recessed area (such as the trench 106) forms a copper interconnect structure; remove the barrier layer 104 and the dielectric layer 102 on the non-recessed area The hard mask layer 103.

The traditional method for removing the copper 105, the barrier layer 104 and the hard mask layer 103 is CMP (Chemical Mechanical Polishing). In the chemical mechanical polishing process, the substrate 101 is placed on the polishing pad, and the substrate 101 is pressed against the polishing pad with pressure. When pressure is used to polish and planarize the copper 105, the barrier layer 104, and the hard mask layer 103, the polishing pad and the substrate 101 move relative to each other. Providing a polishing fluid, often referred to as abrasive, to the polishing pad makes polishing easier. Although chemical mechanical polishing can achieve good barrier removal results, due to the strong mechanical forces involved, chemical mechanical polishing will have some adverse effects on semiconductor devices. Strong mechanical forces can cause permanent damage to low-k media, and polishing fluids can reduce the performance of low-k media. The good removal result of the barrier layer 104 means that the barrier layer 104 on the non-recessed area is completely removed, and the barrier layer on the sidewall of the recessed area is not damaged by etching, as shown in FIG. 1(c).

Due to the shortcomings of the CMP method, a dry etching method is used to remove the barrier layer 104 and the hard mask layer 103. After removing the copper 105 by CMP, XeF2 vapor phase etching is used to remove the barrier layer 104 and the hard mask layer 103 in a high temperature and low pressure environment. The material of the barrier layer 104 is tantalum, tantalum nitride, titanium or titanium nitride, and the material of the hard mask layer 103 is titanium nitride. The use of XeF2 vapor etching does not damage the copper 105 and the dielectric layer 102, but the XeF2 vapor etching can easily cause insufficient or over-etching of the barrier layer 104. As shown in FIG. 2, the barrier layer 104 is under-etched. It can be seen from FIG. 2 that the barrier layer 104 on the non-recessed area is not completely removed, and a part of the barrier layer 104 remains on the non-recessed area. Fig. 3 shows a situation where the barrier layer 104 is over-etched. It can be seen from Fig. 3 that although the barrier layer 104 on the non-recessed area is completely removed, a part of the barrier layer 104 deposited on the sidewall of the trench 106 is also Remove. The upper surface of the barrier layer 104 in the trench 106 is lower than the upper surface of the copper 105 in the trench 106. Either under-etching or over-etching of the barrier layer 104 will degrade the quality of the semiconductor device.

Correspondingly, the present invention proposes a method for forming a metal interconnection structure to prevent the barrier layer deposited on the sidewall of the recessed region from being over-etched.

According to an exemplary embodiment of the present invention, a method for forming a metal interconnection structure includes the following steps: forming a recessed area on a hard mask layer and a dielectric layer; on the hard mask layer, the sidewall of the recessed area, and the recess Deposit a barrier layer on the bottom of the entry area; deposit metal on the barrier layer and fill the recessed area with metal; use an electro-polishing process to remove the metal deposited on the non-recessed area, and the metal in the recessed area is over-polished to form Recess, during the electropolishing process, an oxide film is formed on the barrier layer, the thickness of the oxide film on the barrier layer on the sidewall of the recessed area is greater than the thickness of the oxide film on the barrier layer on the hard mask layer; remove the hard mask layer The oxide film on the barrier layer on the upper side, and leave a certain thickness of the oxide film on the barrier layer on the sidewall of the recessed area; The barrier layer and the hard mask layer are removed by etching, and the etching has a high selectivity to the oxide film, and the remaining oxide film prevents the barrier layer on the sidewall of the recessed region from being over-etched.

In summary, when the electro-polishing process is used to remove the metal and make the metal over-polished, an oxide film is formed on the barrier layer due to the anodic oxidation effect to passivate the exposed barrier layer. The dielectric layer is located under the barrier layer and the hard mask layer. Therefore, the charges are evenly distributed in the conductive layer (ie, the barrier layer and the hard mask layer) and are concentrated on the surface of the dielectric layer. Based on the theory of non-conductive material surface potential equalization, the charge distributed on the surface of the non-conductive material is inversely proportional to the radius of curvature. Therefore, the charge accumulated on the shoulder of the barrier layer is more than that on the flat area, so that the oxide film on the shoulder of the barrier layer is more The oxide film in other areas is thick, which is why the oxide film on the barrier layer on the sidewall of the recessed area is thicker than the oxide film on the barrier layer on the hard mask layer. After the oxide film on the barrier layer on the hard mask layer is removed, the oxide film left on the barrier layer on the sidewall of the recessed area forms a continuous film on the barrier layer to prevent the barrier layer on the sidewall of the recessed area from being When the barrier layer and the hard mask layer are removed, they are over-etched, which helps to improve the quality of the semiconductor device.

101‧‧‧Substrate

102‧‧‧Media layer

103‧‧‧Hard Mask Layer

104‧‧‧Barrier

105‧‧‧Copper

106‧‧‧Groove

201‧‧‧Substrate

202‧‧‧Media layer

203‧‧‧Hard Mask Layer

204‧‧‧Barrier

205‧‧‧Metal

206‧‧‧Oxide film

207‧‧‧Recessed area

Those skilled in the art can clearly understand the content of the present invention by reading the description of the specific embodiments and referring to the accompanying drawings. The accompanying drawings include: Figure 1 (a) to Figure 1 (c) are existing metal interconnections formed Sectional view of the structural process; Figure 2 is a cross-sectional view of the under-etched barrier layer; Figure 3 is a cross-sectional view of the over-etched barrier layer; Figure 4 (a) to Figure 4 (d) are cross-sectional views of the formation of the metal interconnect structure of the present invention; Figure 5 It is a flow chart of the method of forming a metal interconnect structure of the present invention; FIG. 6 is the measurement result of the oxygen content after the electropolishing process; FIG. 7 is a STEM cross-sectional view of the POST-TFE sample, showing a good barrier layer Removal results; and Figure 8 is a FIB/SEM cross-sectional view of the POST-TFE sample, showing the over-etching of the barrier layer.

Referring to FIGS. 4(a) to 4(d) and FIG. 5, a method for forming a metal interconnection structure according to an exemplary embodiment of the present invention is disclosed. The method includes the following steps, which will be performed in the following A detailed description.

Step 301, forming a recessed area on the hard mask layer and the dielectric layer. As shown in FIG. 4(a), a substrate 201, such as a wafer, is provided. A dielectric layer 202 is deposited on the substrate 201. The material of the dielectric layer 202 may be SiO ₂ , SiOC, SiOF, SiLK, BD, BDII, BDIII, etc. Preferably, the dielectric layer 202 selects a low-k dielectric to reduce the capacitance between interconnect structures in the semiconductor device. According to different structural requirements, the dielectric layer 202 may be composed of two or more layers. If the dielectric layer 202 is composed of two layers, the dielectric constant of the upper layer is higher than the dielectric constant of the lower layer. A hard mask layer 203 is deposited on the dielectric layer 202. The material of the hard mask layer 203 may be tantalum nitride or titanium nitride. The existing technology is used to form recessed areas, such as grooves, holes, etc., on the hard mask layer 203 and the dielectric layer 202. The recessed area 207 is illustrated in the figure.

In step 302, a barrier layer 204 is deposited on the hard mask layer 203, the sidewalls of the recessed area 207, and the bottom of the recessed area 207. Still referring to FIG. 4(a), any suitable method can be used to deposit the barrier layer 204 on the sidewalls and bottom of the hard mask layer 203 and the recessed region 207, such as chemical vapor deposition (VCD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The barrier layer 204 may be made of conductive materials, such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt, and the like.

In step 303, a metal 205 is deposited on the barrier layer 204, and the recessed area 207 is filled with the metal 205. As shown in FIG. 4(a), any suitable method is used to deposit metal 205 on the barrier layer 204 and fill the recessed area 207 with the metal 205, such as PVD, CVD, ALD, electroplating, etc. In addition, in some applications, for example, the metal 205 is deposited by an electroplating process, and a metal seed layer is deposited on the barrier layer 204 before the metal 205 is deposited. In order to make the metal 205 easier to deposit on the barrier layer 204, the metal seed layer may include the same material as the metal 205. The metal 205 fills the recessed area and covers the non-recessed area, as shown in FIG. 4(a). The metal 205 is preferably copper.

In step 304, an electro-polishing process is used to remove the metal 205 deposited on the non-recessed area, and the metal 205 in the recessed area 207 is over-polished to form a recess. During the electropolishing process, oxygen is formed on the barrier layer 204 The thickness of the oxide film 206 on the barrier layer 204 on the sidewall of the recessed region is greater than the thickness of the oxide film 206 on the barrier layer 204 on the hard mask layer 203. As shown in FIG. 4(b), when the metal 205 is removed and overpolished by the electro-polishing process, an oxide film 206 is formed on the barrier layer 204 due to the anodization effect, so that the exposed barrier layer 204 is passivated. The dielectric layer 202 is located under the barrier layer 204 and the hard mask layer 203. Therefore, the charges are evenly distributed in the conductive layer (including the barrier layer 204 and the hard mask layer 203), and the charges will be accumulated on the surface of the dielectric layer 202. Based on the theory of surface potential equalization of non-conductive materials, the charge distribution on the surface of non-conductive materials is inversely proportional to the radius of curvature, so the charge accumulated on the shoulder of the barrier layer is more than that in the flat area, so that the thickness of the oxide film 206 at the shoulder of the barrier layer 204 The thickness of the oxide film is thicker than that of other regions. This means that the oxide film 206 on the barrier layer 204 on the sidewall of the recessed area (corresponding to the shoulder) is larger than the oxide film 206 on the barrier layer 204 on the hard mask layer 203 (corresponding to the flat area). The reason for the thick film 206. As shown in FIG. 6, experiments show that the thickness of the oxide film 206 on the barrier layer 204 on the sidewall of the recessed region is greater than the thickness of the oxide film 206 on the barrier layer 204 on the hard mask layer 203. When the metal 205 on the non-recessed area is removed by the electro-polishing process, and the metal 205 in the recessed area is over-polished, a part of the substrate 201 is cut as a sample, and then, an electron microscope and model of HELIOS 660 are used. An energy spectrometer model X-MaxN SDD is used to line scan the surface of the sample. The energy of the electron beam is 3kV, the scan length is about 2μm, and the number of scan points is 400. The scan length of the barrier layer 204 is 1 μm, and the scan length of the metal structures on both sides of the barrier layer 204 is 1 μm. It can be seen from the measurement results that the weight percentage of oxygen in the barrier layer 204 near the metal structure is higher than that in other regions. This proves that the thickness of the oxide film 206 on the barrier layer 204 on the sidewall of the recessed region is greater than the thickness of the oxide film 206 on the barrier layer 204 on the hard mask layer 203.

In step 304, in order to form an oxide film 206 on the shoulder of the barrier layer 204, the metal 205 filled in the recessed area is overpolished to form a recess, as shown in FIG. 4(b). The thickness of the oxide film 206 formed on the barrier layer 204 is proportional to the overpolished amount of the metal 205 filled in the recessed area, and the overpolished amount of the metal 205 is equal to or greater than the thickness of the barrier layer 204 and the hard mask layer 203. In a specific embodiment, the amount of metal 205 over-polished is 300-500 angstroms.

Step 305, remove the oxide film 206 on the barrier layer 204 on the hard mask layer 203, and leave a certain thickness of the oxide film 206 on the barrier layer 204 on the sidewall of the recessed area, as shown in FIG. 4(c). The oxide film 206 on the barrier layer 204 is removed by wet etching, such as BHF solution. The oxide film 206 on the barrier layer 204 can also be removed by dry etching, such as HF vapor or a mixture of HF vapor and ethanol, methanol or isopropanol. The oxide film 206 on the barrier layer 204 on the sidewall of the remaining recessed region 207 forms a continuous thin film on the barrier layer 204, and the thickness of the remaining oxide film 206 is greater than 5 angstroms. If the oxide film 206 on the barrier layer 204 on the sidewall of the recessed area 207 is etched and a continuous film cannot be formed on the barrier layer 204, the barrier layer 204 sandwiched between the metal 205 and the dielectric layer 202 will be overetched , As shown in Figure 8, Figure 8 is a FIB/SEM cross-sectional view of the POST-TFE sample, indicating that the barrier layer is over-etched.

In step 306, the barrier layer 204 and the hard mask layer 203 are removed by etching. The etching has a high selectivity to the oxide film 206, and the remaining oxide film 206 prevents the barrier layer 204 on the sidewall of the recessed region from being overetched, such as As shown in Figure 4(d). The high selection ratio means that the etching rate of the barrier layer 204 and the hard mask layer 203 is much higher than the etching rate of the oxide film 206. The barrier layer 204 and the hard mask layer 203 are removed by vapor etching, and the etching gas can be XeF ₂ , XeF ₄ , XeF ₆ , KrF ₂ , BrF _3, etc. Taking XeF ₂ as an example, the XeF ₂ gas spontaneously chemically reacts with the barrier layer of tantalum or tantalum nitride at a certain temperature and pressure. XeF ₂ isotropic selective etching of tantalum or tantalum nitride. XeF ₂ gas has a good selection ratio for both copper and dielectric materials. During the etching process, the pressure of the XeF ₂ gas is between 0.1-100 Torr, preferably 0.5-20 Torr. XeF ₂ has a high selectivity to the oxide film 206. Therefore, during the etching of the barrier layer 204 and the hard mask layer 203, the oxide film 206 can prevent the barrier layer 204 on the sidewall of the recessed region from being over-etched. As shown in Figure 7, Figure 7 is a STEM cross-sectional view of the POST-TFE sample, showing a good barrier layer removal result, that is, the barrier layer 204 on the non-recessed area is completely removed, and it is sandwiched between the metal 205 and the dielectric layer 202. The barrier layer 204 in between is not etched or damaged. When the barrier layer 204 and the hard mask layer 203 on the non-recessed area are completely removed, the adjacent metal interconnection structures are separated by the dielectric layer 202.

In summary, when the metal 205 is removed by an electro-polishing process and the metal 205 is over-etched, an oxide film 206 is formed on the barrier layer 204 to passivate the exposed barrier layer 204, and the oxidation on the barrier layer 204 on the sidewall of the recessed region The thickness of the film 206 is greater than the thickness of the oxide film 206 on the barrier layer 204 on the hard mask layer 203. After the oxide film 206 on the barrier layer 204 on the hard mask layer 203 is removed, the barrier layer 204 on the sidewall of the recessed area remains The oxide film 206 forms a continuous thin film on the surface of the barrier layer 204 to prevent the barrier layer 204 on the sidewall of the recessed area from being over-etched when the barrier layer 204 and the hard mask layer 203 are removed, thereby improving the quality of the semiconductor device.

The present invention has been described in detail through the above-mentioned embodiments and related drawings, and the related technology has been disclosed in detail, so that those skilled in the art can implement it accordingly. The above-mentioned embodiments are only used to illustrate the present invention, not to limit the present invention. The scope of rights of the present invention should be defined by the scope of the patent application of the present invention. As for the change in the number of elements described herein or the replacement of equivalent elements, all should still belong to the scope of the present invention.

201‧‧‧Substrate

202‧‧‧Media layer

204‧‧‧Barrier

205‧‧‧Metal

207‧‧‧Recessed area

Claims (17)

A method of forming a metal interconnection structure includes: forming a recessed area on a hard mask layer and a dielectric layer; depositing a barrier layer on the hard mask layer, the sidewalls of the recessed area, and the bottom of the recessed area; on the barrier layer Deposit metal on the top and fill the recessed area with metal; use an electro-polishing process to remove the metal on the non-recessed area, and over polish the metal in the recessed area to form a recess. During the electro-polishing process, an oxide film is formed on the barrier layer , The thickness of the oxide film on the barrier layer on the sidewall of the recessed area is greater than the thickness of the oxide film on the barrier layer on the hard mask layer; remove the oxide film on the barrier layer on the hard mask layer, and leave a certain thickness of recess The oxide film on the barrier layer on the sidewall of the region; the hard mask layer and the barrier layer on the hard mask layer and the barrier layer on the sidewall of the recess are removed by etching. The etching has a high selectivity ratio to the oxide film, leaving behind The oxide film prevents the barrier layer sandwiched between the metal and the dielectric layer in the recessed area from being overetched. The method according to claim 1, wherein the metal is copper. The method according to claim 1, wherein the barrier layer is tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and cobalt. The method according to claim 1, characterized in that the thickness of the oxide film formed on the barrier layer is proportional to the amount of metal overpolishing in the recessed area. The method according to claim 4, wherein the amount of metal overpolishing is equal to or greater than the thickness of the barrier layer and the hard mask layer. The method according to claim 4, characterized in that the amount of metal over-polishing is 300-500 angstroms. The method according to claim 1, characterized in that the oxide film on the barrier layer is removed by wet etching. The method according to claim 7, wherein the oxide film on the barrier layer is removed using a BHF solution. The method according to claim 1, characterized in that the oxide film on the barrier layer is removed by dry etching. The method according to claim 9, characterized in that the oxide film on the barrier layer is removed using HF steam or a mixture of HF steam and ethanol, methanol or isopropanol. The method according to claim 1, wherein the remaining oxide film forms a continuous thin film on the barrier layer. The method according to claim 11, wherein the thickness of the remaining oxide film is greater than 5 angstroms. The method according to claim 1, characterized in that the barrier layer and the hard mask layer are removed by vapor etching. The method according to claim 13, characterized in that the gas for gas phase etching is XeF ₂ , XeF ₄ , XeF ₆ , KrF ₂ , BrF ₃ . The method according to claim 1, wherein the material of the dielectric layer is a low-k dielectric material. The method according to claim 1, wherein the medium layer is two or more layers. The method according to claim 16, characterized in that the dielectric layer is two layers, and the dielectric constant of the upper layer is higher than the dielectric constant of the lower layer.

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