CN106463455A - Method for forming metal interconnection - Google Patents
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- CN106463455A CN106463455A CN201480079797.7A CN201480079797A CN106463455A CN 106463455 A CN106463455 A CN 106463455A CN 201480079797 A CN201480079797 A CN 201480079797A CN 106463455 A CN106463455 A CN 106463455A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
A method for forming metal interconnection, which can avoid a barrier layer (204) deposited on the sidewall of recessed area (207) being over etched, is disclosed. The method includes the following steps: forming a recessed area (207) on a hard mask layer (203) and a dielectric layer (202); depositing a barrier layer (204) on the hard mask layer(203), sidewall of the recessed area (207) and bottom of the recessed area (207); depositing metal (205) on the barrier layer (204) and filling the recessed area (207) with the metal (205); removing the metal (205) deposited on non-recessed area by electropolishing and the metal (205) filled in the recessed area (207) being over polished to form a dishing, an oxide film (206) being formed on the barrier layer (204) during the electropolishing process; removing the oxide film (206) on the barrier layer (204) deposited on the hard mask layer (203), and retaining a certain thickness of oxide film (206) on the barrier layer (204) deposited on the sidewall of the recessed area (207); removing the barrier layer (204) and the hard mask layer (203) by etching which has a high selectivity to the oxide film (206), the retained oxide film (206) preventing the barrier layer (204) deposited on the sidewall of the recessed area (207) from being over etched.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, more particularly, to a kind of method forming metal interconnection structure, to keep away
Exempt from the barrier layer over etching being deposited on trenched side-wall.
Background technology
With the fast development of process for fabrication of semiconductor device, the integrated level more and more higher of semiconductor device, two-layer or two
Metal interconnection structure more than layer is widely used.Existing metal interconnection structure is made of aluminum.However, with semiconductor device
Characteristic size less and less, the impact to performance of semiconductor device for the RC retardation ratio is more and more obvious.In order to reduce RC retardation ratio effect,
Copper is used to because its resistance ratio aluminum is little replace aluminum to make interconnection structure.Additionally, replacing traditional medium material using low-k materials
Material is as the dielectric layer in interconnection structure to reduce parasitic capacitance.
As shown in Fig. 1 (a) to Fig. 1 (c), a kind of method forming copper interconnection structure generally comprises following steps：Lining is provided
Bottom 101, such as wafer；Metallization medium layer 102 on the substrate 101；Hard mask layer 103 is deposited on dielectric layer 102；In dielectric layer
102 and hard mask layer 103 on form multiple grooves 106, groove 106 is as shown in Fig. 1 (a) to Fig. 1 (c)；On hard mask layer 103
And the side wall of groove 106 and bottom deposit barrier layer 104；On barrier layer 104 and the side wall of groove 106 and bottom deposit
Copper seed layer, copper seed layer is deposited on barrier layer 104；Copper 105 is deposited, copper 105 will on copper seed layer and in groove 106
Groove 106 fills up；Remove the copper 105 being deposited on non-recess region, retain copper 105 shape in recessed region (as groove 106)
Become copper interconnection structure；Remove the hard mask layer 103 on the barrier layer 104 and dielectric layer 102 on non-recess region.
It is CMP (chemically mechanical polishing) that tradition goes the method for copper removal 105, barrier layer 104 and hard mask layer 103.In chemistry
In mechanical polishing process, substrate 101 is placed on polishing pad, with pressure, substrate 101 is pressed on polishing pad.When with pressure
When polishing and planarization copper 105, barrier layer 104 and hard mask layer 103, polishing pad and substrate 101 carry out relative motion.To throwing
A kind of polishing fluid being often referred to as abrasive material is provided so that polishing is easier to make on light pad.Although chemically mechanical polishing can obtain
Well barrier layer go division result, however, due to being related to strong mechanicals efforts, chemically mechanical polishing can be to semiconductor device
Produce some harmful effects.Strong mechanicals efforts can cause permanent damage to low k dielectric, and polishing fluid can reduce low k dielectric
Performance.The division result of going on described good barrier layer 104 means that the barrier layer 104 on non-recess region is completely removed,
And the barrier layer on the wall of recessed region side is not etched destruction, as shown in Fig. 1 (c).
The shortcoming being existed due to CMP method, a kind of method of dry etching is used to remove barrier layer 104 and hard mask layer
103.After removing copper removal 105 using CMP, using XeF2 gas phase etching, remove barrier layer 104 and hard in the environment of high-temperature low-pressure
Mask layer 103.The material on barrier layer 104 is tantalum, tantalum nitride, titanium or titanium nitride, and the material of hard mask layer 103 is titanium nitride.Make
With XeF2 gas phase etching, copper 105 and dielectric layer 102 are not damaged, but XeF2 gas phase etching easily causes barrier layer 104
Etching is not enough or over etching.It is illustrated in figure 2 the situation that barrier layer 104 etches deficiency, as can be seen from Figure 2 on non-recess region
Barrier layer 104 do not remove completely, a part of barrier layer 104 remains on non-recess region.It is illustrated in figure 3 barrier layer
The situation of 104 over etchings, although the barrier layer 104 as can be seen from Figure 3 on non-recess region is completely removed, is deposited on
A part of barrier layer 104 on groove 106 side wall is also removed.The upper surface on the barrier layer 104 in groove 106 is less than groove
The upper surface of the layers of copper 105 in 106.Either barrier layer 104 etches deficiency or over etching all will reduce semiconductor device
Quality.
Content of the invention
Correspondingly, the present invention proposes a kind of method forming metal interconnection structure, it is to avoid be deposited on recessed region side wall
On barrier layer by over etching.
A kind of method of the formation metal interconnection structure being disclosed according to the present invention one one exemplary embodiment comprises the following steps：
Recessed region is formed on hard mask layer and dielectric layer；On hard mask layer, the side wall of recessed region and the bottom of recessed region
Portion deposition barrier layer；Deposited metal over the barrier layer, and make recessed region fill up metal；Removed using electrolytic brightening process and be deposited on
Metal on non-recess region, and the metal in recessed region is polished to form depression excessively, in electric polishing procedure, barrier layer
Upper formation oxide-film, the thickness of the oxide-film on barrier layer on the wall of recessed region side is more than on the barrier layer on hard mask layer
The thickness of oxide-film；Remove the oxide-film on the barrier layer being formed on hard mask layer, and stay certain thickness be formed at recessed
The oxide-film on barrier layer on the wall of recessed region side；Barrier layer and hard mask layer are removed by etching, this etching has to oxide-film
There is high selectivity, the oxide-film staying stops the barrier layer on the wall of recessed region side by over etching.
In sum, when metal is removed and when making metal cross polishing using electrolytic brightening process, due to anodic oxidation effect,
Form oxide-film on barrier layer and so that the barrier layer of exposure is passivated.Dielectric layer is located under barrier layer and hard mask layer, therefore, electricity
Lotus is evenly distributed on conductive layer (i.e. barrier layer and hard mask layer), and is gathered in dielectric layer surface.Based on non-conducting material surface
Potential balance is theoretical, is distributed in the electric charge on non-conducting material surface and radius of curvature is inversely proportional to, therefore, be gathered in barrier layer shoulder
Charge ratio flat place many, so that the oxide-film of barrier layer shoulder is than the thickness of oxidation film in other regions, here it is recessed
The reason oxide-film on barrier layer in region side walls is than thickness of oxidation film on the barrier layer on hard mask layer.Hard mask layer
On barrier layer on oxide-film be removed after, oxide-film shape over the barrier layer that the barrier layer on the wall of recessed region side stays
Become continuous thin film to prevent barrier layer on the wall of recessed region side when removing barrier layer and hard mask layer by over etching, favorably
In the quality improving semiconductor device.
Brief description
Those skilled in the art passes through to read the description of specific embodiment, and refer to the attached drawing, can be clearly understood from this
The content of invention, wherein accompanying drawing includes：
Fig. 1 (a) to Fig. 1 (c) is the existing sectional view forming metal interconnection structure process；
Fig. 2 is the not enough sectional view of barrier etch；
Fig. 3 is the sectional view of barrier layer over etching；
Fig. 4 (a) to Fig. 4 (d) is the sectional view of the formation metal interconnection structure of the present invention；
Fig. 5 is the flow chart of the method for formation metal interconnection structure of the present invention；
Fig. 6 is the measurement result of percentage by weight contained by oxygen element after electrolytic brightening process；
Fig. 7 is the STEM sectional view of POST-TFE sample, illustrates good barrier layer and goes division result；And
Fig. 8 is the FIB/SEM sectional view of POST-TFE sample, illustrates the over etching on barrier layer.
Specific embodiment
With reference to Fig. 4 (a) to the formation gold shown in Fig. 4 (d) and Fig. 5, disclosing according to the present invention one one exemplary embodiment
The method belonging to interconnection structure, the method comprises the steps, these steps will be described in detail below.
Step 301, forms recessed region on hard mask layer and dielectric layer.As shown in Fig. 4 (a), provide substrate 201, such as
Wafer.Metallization medium layer 202 on the substrate 201, the material of dielectric layer 202 can be SiO2、SiOC、SiOF、SiLK、BD、
BDII, BDIII etc..Preferably, dielectric layer 202 selects low k dielectric to reduce the electric capacity between interconnection structure in semiconductor device.Root
According to different topology requirements, dielectric layer 202 can be by two-layer or two-layer composition described above.If dielectric layer 202 is made up of two-layer, on
The dielectric constant of layer is higher than the dielectric constant of lower floor.Hard mask layer 203, the material of hard mask layer 203 are deposited on dielectric layer 202
Material can be tantalum nitride or titanium nitride.Using prior art, recessed region is formed on hard mask layer 203 and dielectric layer 202, such as
Groove, hole etc., have illustrated recessed region 207.
Step 302, on hard mask layer 203, the bottom deposit resistance of the side wall of recessed region 207 and recessed region 207
Barrier 204.Referring still to Fig. 4 (a) Suo Shi, can be using any suitable method in hard mask layer 203, recessed region 207
Barrier layer 204, such as chemical vapor deposition (VCD), physical vapour deposition (PVD) (PVD), ald are deposited on side wall and bottom
(ALD) etc..Barrier layer 204 can be constructed from a material that be electrically conducting, such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt etc..
Step 303, deposited metal 205 on barrier layer 204, and make recessed region 207 fill up metal 205.As Fig. 4 (a)
Shown, using any suitable method on barrier layer 204 deposited metal 205 make metal 205 fill up recessed region 207, example
As PVD, CVD, ALD, plating etc..Additionally, in some applications, for example, using electroplating technology deposited metal 205, in deposition gold
Before belonging to 205, first deposited metal Seed Layer on barrier layer 204.In order that metal 205 is easier is deposited on barrier layer 204
On, metal seed layer can comprise and metal 205 identical material.Metal 205 fills up recessed region and covers non-recess area
Domain, such as shown in Fig. 4 (a).The preferred copper of metal 205.
Step 304, removes, using electrolytic brightening process, the metal 205 being deposited on non-recess region, in recessed region 207
Metal 205 is crossed polishing and is formed depression.During electrolytic brightening process, barrier layer 204 forms oxide-film 206, recessed region side
The thickness of the oxide-film 206 on barrier layer 204 on wall is more than the oxide-film 206 on the barrier layer 204 on hard mask layer 203
Thickness.As shown in Fig. 4 (b), when being removed using electrolytic brightening process and cross polishing metal 205, due to anodic oxidation effect, in resistance
Form oxide-film 206 in barrier 204 and so that the barrier layer 204 of exposure is passivated.Dielectric layer 202 is located at barrier layer 204 and hard mask
Under layer 203, therefore, electric charge is evenly distributed in conductive layer (including barrier layer 204 and hard mask layer 203), and electric charge will be assembled
Surface in dielectric layer 202.Based on non-conducting material surface potential isostatic theory, the CHARGE DISTRIBUTION on non-conducting material surface and song
Rate radius is inversely proportional to, so being gathered in the many of the charge ratio flat place of barrier layer shoulder, so that the oxidation of barrier layer 204 shoulder
The thickness of film 206 is thicker than the thickness of the oxide-film in other regions, here it is the stop on recessed region side wall (corresponding shoulder)
Oxide-film 206 on layer 204 is more former than oxide-film 206 thickness on the barrier layer 204 on hard mask layer 203 (corresponding flat place)
Cause.As shown in fig. 6, experiment shows, the thickness of the oxide-film 206 on barrier layer 204 on the wall of recessed region side is greater than to be covered firmly
The thickness of the oxide-film 206 on barrier layer 204 in film layer 203.When using electrolytic brightening process by the metal on non-recess region
205 removals, and the metal 205 in recessed region is crossed after polishing, the part cutting substrate 201, as sample, then, uses
The ultramicroscope of model HELIOS 660 and model X-MaxNThe energy disperse spectroscopy of SDD comes the surface of line scanned samples.Electronics
The energy of bundle is 3kv, and sweep length is about 2 μm, and number of scan points is at 400 points.The sweep length on barrier layer 204 is 1 μm, stops
The sweep length of the metal structure of layer 204 both sides is 1 μm.From measurement result as can be seen that near metal structure barrier layer 204
In oxygen element percentage by weight be higher than other regions, thus demonstrating the oxygen on the barrier layer 204 on the wall of recessed region side
Change the thickness that film 206 thickness is greater than the oxide-film 206 on the barrier layer 204 on hard mask layer 203.
In step 304, in order to the shoulder on barrier layer 204 forms oxide-film 206, it is filled in the metal in recessed region
205 are crossed polishing forms depression, such as shown in Fig. 4 (b).On barrier layer 204 formed the thickness of oxide-film 206 be filled in recessed
The amount that metal 205 in region crosses polishing is directly proportional, and the amount that metal 205 crosses polishing is equal to or more than barrier layer 204 and hard mask
The thickness of layer 203.In a detailed embodiment, metal 205 crosses the amount polishing for 300-500 angstrom.
Step 305, removes the oxide-film 206 on the barrier layer 204 being formed on hard mask layer 203, and leaves certain thickness
Oxide-film 206 on the barrier layer 204 being formed on the wall of recessed region side of degree, such as shown in Fig. 4 (c).Oxygen on barrier layer 204
Change film 206 wet etching to remove, such as BHF solution.Oxide-film 206 on barrier layer 204 can also be removed with dry etching, such as
HF steam or the mixture of HF steam and ethanol, methanol or isopropanol.The resistance being formed on recessed region 207 side wall staying
Oxide-film 206 in barrier 204 forms continuous thin film on barrier layer 204, and the thickness of the oxide-film 206 staying is more than
5 angstroms.If the oxide-film 206 on barrier layer 204 on recessed region 207 side wall be etched and can not on barrier layer 204 shape
Become continuous thin film, the barrier layer 204 being clipped between metal 205 and dielectric layer 202 will be by over etching, as shown in figure 8, Fig. 8 is
The FIB/SEM sectional view of POST-TFE sample, illustrates barrier layer over etching.
Step 306, etching removes barrier layer 204 and hard mask layer 203, and this etching has high selectivity to oxide-film 206,
The oxide-film 206 staying stops the barrier layer 204 on the wall of recessed region side by over etching, such as shown in Fig. 4 (d).High selectivity
Mean that the speed of etching barrier layer 204 and hard mask layer 203 is far above the speed of etching oxidation film 206.Using gas phase etching
Remove barrier layer 204 and hard mask layer 203, etching gas can be XeF2, XeF4, XeF6, KrF2, BrF3 etc..With XeF2 it is
Example, spontaneously there is chemical reaction with barrier layer tantalum or tantalum nitride in XeF2 gas at certain temperature and pressure.XeF2 respectively to
The selective etch tantalum of the same sex or tantalum nitride.XeF2 gas all has good selection ratio to copper and dielectric substance.In etching
During, between 0.1-100 support, preferably 0.5-20 holds in the palm the pressure of XeF2 gas.XeF2 has high selection to oxide-film 206
Therefore during etching barrier layer 204 and hard mask layer 203, oxide-film 206 can stop the resistance on the wall of recessed region side to ratio
Barrier 204 is by over etching.As shown in fig. 7, Fig. 7 is the STEM sectional view of POST-TFE sample, illustrates good barrier layer and go
Division result, that is, the barrier layer 204 on non-recess region remove completely, and be clipped in the barrier layer between metal 205 and dielectric layer 202
204 are not etched and damage.After the barrier layer 204 on non-recess region and hard mask layer 203 remove completely, adjacent gold
Belong to interconnection structure to be separated by dielectric layer 202.
In sum, when metal 205 and over etching metal 205 are removed using electrolytic brightening process, shape on barrier layer 204
Become oxide-film 206 so that the barrier layer 204 of exposure is passivated, be formed at the oxide-film on the barrier layer 204 on the wall of recessed region side
206 thickness is more than the thickness of the oxide-film 206 on the barrier layer 204 being formed on hard mask layer 203.It is formed at hard mask layer
After the oxide-film 206 on barrier layer 204 on 203 is removed, oxidation that the barrier layer 204 on the wall of recessed region side stays
Film 206 forms continuous thin film to prevent the barrier layer 204 on the wall of recessed region side from removing stop on the surface on barrier layer 204
Over etching when layer 204 and hard mask layer 203, improves the quality of semiconductor device.
The present invention passes through above-mentioned embodiment and correlative type explanation, and what oneself was concrete, full and accurate discloses correlation technique, makes this
The technical staff in field can implement according to this.And embodiment described above is used only to illustrate the present invention, rather than it is used for limiting
The present invention's, the interest field of the present invention, should be defined by the claim of the present invention.As for component number specifically described herein
Replacement of change or equivalence element etc. still all should belong to the interest field of the present invention.
Claims (17)
1. a kind of method forming metal interconnection structure, including：
Recessed region is formed on hard mask layer and dielectric layer；
On hard mask layer, the bottom deposit barrier layer of the side wall of recessed region and recessed region；
Deposited metal over the barrier layer, and make recessed region fill up metal；
Metal on non-recess region is removed using electrolytic brightening process, the metal in recessed region is crossed polishing and formed depression, in electricity
In polishing process, barrier layer forms oxide-film, the thickness being formed at oxide-film on the barrier layer on the wall of recessed region side is big
The thickness of the oxide-film on the barrier layer being formed on hard mask layer；
Remove the oxide-film on the barrier layer being formed on hard mask layer, and stay and certain thickness be formed at recessed region side wall
On barrier layer on oxide-film；
Barrier layer and hard mask layer are removed by etching, this etching has high selectivity to oxide-film, the oxide-film resistance staying
Only the barrier layer on the wall of recessed region side is by over etching.
2. method according to claim 1 is it is characterised in that metal is copper.
3. method according to claim 1 is it is characterised in that barrier layer is tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt.
4. method according to claim 1 it is characterised in that on barrier layer formed the thickness of oxide-film and recessed region
The amount that interior metal crosses polishing is directly proportional.
5. method according to claim 4 is it is characterised in that the amount that metal crosses polishing is equal to or more than barrier layer and firmly covers
The thickness of film layer.
6. method according to claim 4 is it is characterised in that the amount that metal crosses polishing is 300-500 angstrom.
7. method according to claim 1 is it is characterised in that remove the oxide-film on barrier layer using wet etching.
8. method according to claim 7 is it is characterised in that the oxide-film on barrier layer uses BHF solution to remove.
9. method according to claim 1 is it is characterised in that remove the oxide-film on barrier layer using dry etching.
10. method according to claim 9 is it is characterised in that the oxide-film on barrier layer uses HF steam or HF steam
Remove with the mixture of ethanol, methanol or isopropanol.
11. methods according to claim 1 are it is characterised in that the oxide-film staying is formed continuously over the barrier layer
Thin film.
12. methods according to claim 11 are it is characterised in that the thickness of the oxide-film staying is more than 5 angstroms.
13. methods according to claim 1 are it is characterised in that remove barrier layer and hard mask layer using gas phase etching.
14. methods according to claim 13 it is characterised in that gas phase etching gas be XeF2, XeF4, XeF6,
KrF2、BrF3.
15. methods according to claim 1 are it is characterised in that the material of dielectric layer is low k dielectric materials.
16. methods according to claim 1 are it is characterised in that dielectric layer is more than two-layer or two-layer.
17. methods according to claim 16 are it is characterised in that dielectric layer is two-layer, under the dielectric constant on upper strata is higher than
The dielectric constant of layer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2014/081790 WO2016004573A1 (en) | 2014-07-08 | 2014-07-08 | Method for forming metal interconnection |
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| CN106463455A true CN106463455A (en) | 2017-02-22 |
| CN106463455B CN106463455B (en) | 2019-02-15 |
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| JP (1) | JP6301003B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108873172A (en) * | 2018-06-29 | 2018-11-23 | 中国科学院上海光学精密机械研究所 | A kind of powering on the preparation method of adjustable height quality thin film micro-optical device |
| CN110911350A (en) * | 2019-11-22 | 2020-03-24 | 上海集成电路研发中心有限公司 | Forming method of inclined hole |
| CN115881549A (en) * | 2023-01-19 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653683B (en) * | 2016-12-29 | 2019-09-13 | 上海集成电路研发中心有限公司 | A method of etching buried layer in post-channel interconnection |
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Also Published As
| Publication number | Publication date |
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| JP6301003B2 (en) | 2018-03-28 |
| KR20170030522A (en) | 2017-03-17 |
| KR102247940B1 (en) | 2021-05-07 |
| WO2016004573A1 (en) | 2016-01-14 |
| JP2017523610A (en) | 2017-08-17 |
| CN106463455B (en) | 2019-02-15 |
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Address after: 201203 building 4, No. 1690, Cailun Road, free trade zone, Pudong New Area, Shanghai Patentee after: Shengmei semiconductor equipment (Shanghai) Co., Ltd Address before: 201203 Shanghai City, Pudong New Area Chinese Shanghai Zhangjiang High Tech Park of Pudong New Area Cailun Road No. 1690 building fourth Patentee before: ACM (SHANGHAI) Inc. |