CN115881549A - Manufacturing method of semiconductor structure and semiconductor structure - Google Patents
Manufacturing method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN115881549A CN115881549A CN202310056579.2A CN202310056579A CN115881549A CN 115881549 A CN115881549 A CN 115881549A CN 202310056579 A CN202310056579 A CN 202310056579A CN 115881549 A CN115881549 A CN 115881549A
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Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps: providing a base structure, and forming a plurality of spaced metal parts on the base structure; forming a passivation layer on the exposed surface of the metal part and the exposed surface of the base structure; forming a mask layer on the exposed surface of the passivation layer; removing part of the passivation layer and part of the mask layer on the surface of the metal part, forming a first mask part by the remaining mask layer positioned on one side of the metal part far away from the substrate structure, and forming a second mask part by the mask layer positioned between two adjacent metal parts; the first mask portion and a portion of the second mask portion are removed. According to the manufacturing method, the gap between the metal parts is fully filled by the residual second mask part, so that the connection between the residual second mask part and the passivation part on the surface of the metal part is realized, and the problem that the passivation part is easy to collapse in the process of etching the top metal is solved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
The semiconductor device is composed of a metal layer, a passivation layer and a base structure, wherein the metal layer is composed of a plurality of metal parts with gaps. However, due to the fact that the thickness of the passivation layer is not enough, the gap between the metal part and the metal part is not filled enough, and in the process of etching the top metal, the rest passivation layer is prone to collapse, so that the top metal is damaged, the product performance is affected, and further, the yield of semiconductors is reduced.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to solve a problem that a remaining passivation portion is easy to collapse in a top metal etching process in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a semiconductor structure, including: providing a base structure and forming a plurality of spaced metal portions on the base structure; forming a passivation layer on an exposed surface of the metal part and an exposed surface of the base structure; forming a mask layer on the exposed surface of the passivation layer; removing part of the passivation layer and part of the mask layer on the surface of the metal part, wherein the rest of the passivation layer forms a passivation part, the rest of the mask layer positioned on one side of the metal part far away from the substrate structure forms a first mask part, and the mask layer positioned between two adjacent metal parts forms a second mask part; and removing the first mask portion and a part of the second mask portion, so that the surface of the remaining second mask portion, which is far away from the base structure, is a first distance from the base structure, the surface of the metal portion, which is far away from the base structure, is a second distance from the base structure, and the first distance is greater than the second distance.
Optionally, forming a passivation layer on an exposed surface of the metal part and an exposed surface of the base structure, including: forming a first sub-passivation layer on an exposed surface of the metal part and an exposed surface of the base structure; and forming a second sub-passivation layer on the surface of the first sub-passivation layer far away from the substrate structure, wherein the first sub-passivation layer and the second sub-passivation layer form the passivation layer.
Optionally, the material of the first sub-passivation layer includes at least one of silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride.
Optionally, a material of the second sub-passivation layer includes at least one of ozone and tetraethoxysilane.
Optionally, a distance between the surface of the mask layer far from the substrate structure and the substrate structure is a third distance, and the third distance is greater than the first distance.
Optionally, the material of the mask layer includes at least one of a photoresist and a silicon-glass bonded structure material.
Optionally, removing the first mask portion and a portion of the second mask portion includes: and cleaning the first mask part and the second mask part to remove the first mask part and part of the second mask part, and forming a third mask part by the remaining part of the second mask part.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor structure including: a base structure; a plurality of spaced apart metal portions on the base structure; the passivation part is positioned on the side wall of the metal part, the partial surface of the metal part far away from the base structure and the base structure between two adjacent metal parts; and the third mask part is positioned between two adjacent metal parts, wherein the distance between the surface of the third mask part far away from the base structure and the base structure is a first distance, the distance between the surface of the metal part far away from the base structure and the base structure is a second distance, and the first distance is greater than the second distance.
Optionally, the passivation portion comprises: a first sub-passivation portion located on a surface of the metal portion and a surface of the base structure; and the second sub-passivation part is positioned on the surface of the first sub-passivation layer far away from the base structure.
Optionally, the material of the first sub-passivation includes at least one of silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride, and the material of the second sub-passivation includes at least one of ozone and tetraethoxysilane.
According to the technical scheme, in the manufacturing method, firstly, a plurality of spaced metal parts are formed on the substrate structure, the passivation layer and the mask layer are sequentially formed on the metal parts and the exposed surfaces of the substrate structure, then, part of the passivation layer and the mask layer are removed, the rest parts form the first mask part and the second mask part, and finally, the first mask part and part of the second mask part are removed, so that the thickness from the rest second mask part to the substrate structure is larger than that of the metal parts. According to the manufacturing method, the gap between the metal parts is fully filled by the residual second mask part, so that the thickness from the third mask part to the substrate structure is greater than that of the metal parts, connection of the third mask part and the passivation part on the surface of the metal parts is realized, the passivation part is prevented from collapsing in the direction far away from the gap, and the problem that the residual passivation layer is easy to collapse in the process of etching the top metal layer in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic flow chart diagram of an embodiment of a method of fabricating a semiconductor structure according to the present application;
FIG. 2 shows a schematic view of a structure including a base structure and a metal portion according to the present application;
fig. 3 shows a schematic diagram of the structure of a passivation layer formed on the basis of fig. 2;
fig. 4 is a schematic diagram showing a structure of forming a first mask portion, a second mask portion, and a passivation portion on the basis of fig. 3;
fig. 5 is a schematic diagram illustrating a structure of forming a third mask portion based on the structure of fig. 4.
Wherein the figures include the following reference numerals:
10. a base structure; 20. a metal part; 21. a passivation layer; 30. a passivation portion; 40. a first mask portion; 50. a second mask portion; 60. a third mask portion.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure herein. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the description and claims, when an element is referred to as being "connected" to another element, it can be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the prior art, due to the insufficient thickness of the passivation layer, the gap between the metal portions is not filled enough, and during the etching of the top metal layer, the remaining passivation layer is easy to collapse, which may damage the top metal layer and affect the product performance. In order to solve the above technical problems, the present application provides a method for manufacturing a semiconductor structure and a semiconductor structure.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, providing a base structure 10, and forming a plurality of spaced metal portions 20 on the base structure 10, so as to obtain the structure shown in fig. 2;
in the above step, the plurality of metal parts formed at intervals may not cover the entire base structure, and the intervals between the metal parts may expose part of the base structure.
Step S102, forming a passivation layer 21 on the exposed surface of the metal portion 20 and the exposed surface of the base structure 10, so as to obtain the structure shown in fig. 3;
in the above steps, the passivation layer may be formed by atomic layer deposition, chemical vapor deposition, or other deposition methods, and the passivation layer may protect the metal portion and the substrate structure and prevent the metal portion and the substrate structure from being scratched by moisture or diffusing mobile ions.
In other embodiments, the passivation layer may be formed by any suitable method, such as epitaxial growth, in addition to the above-mentioned deposition method.
Step S103, forming a mask layer on the exposed surface of the passivation layer;
in the above step, the mask layer may protect the material covered by the mask layer from being damaged in a subsequent process (e.g., etching or ion implantation of the barrier layer). In general, the thickness of the mask layer is greater than 3um, and the specific thickness is determined according to the specific thickness of the metal portion.
Step S104, removing a portion of the passivation layer and a portion of the mask layer on the surface of the metal portion 20, forming a passivation portion 30 on the remaining passivation layer, forming a first mask portion 40 on the remaining mask layer located on the side of the metal portion 20 away from the base structure 10, and forming a second mask portion 50 on the mask layer located between two adjacent metal portions 20, so as to obtain the structure shown in fig. 4;
in one embodiment, the specific process of removing a portion of the passivation layer and a portion of the mask layer on the surface of the metal portion may be: forming a patterned mask plate on one side of the mask layer, which is far away from the passivation layer; and sequentially etching the mask layer and the passivation layer by taking the mask plate as a mask so as to remove part of the passivation layer and the mask layer on the surface of the metal part.
In the above steps, the mask layer is patterned by transferring the mask plate pattern to the mask layer, and then the patterned mask layer is used as a mask to remove part of the passivation layer. Specifically, a part of the passivation layer and the mask layer is removed in an etching mode to form a window region. The remaining passivation layer and the mask layer are divided into two parts, one part is located on the surface of the metal part far away from the substrate structure, and the other part is located in the interval between the metal parts.
Step S105, removing the first mask portion and a portion of the second mask portion, so that a distance between a surface of the remaining second mask portion away from the base structure and the base structure is a first distance H 1 The distance between the surface of the metal part far away from the base structure and the base structure is a second distance H 2 And the first distance H 1 Greater than the second distance H 2 。
In the above steps, a dry etching or wet etching method may be used to remove a part of the first mask portion and the second mask portion, and it is ensured that the remaining second mask portion overflows out of the gap between the two adjacent metal portions, so as to connect the passivation portions at the tops of the two adjacent metal portions and prevent the passivation portions from collapsing in a direction away from the gap.
In the manufacturing method, first, a plurality of spaced metal portions are formed on a substrate structure, a passivation layer and a mask layer are sequentially formed on the exposed surfaces of the metal portions and the substrate structure, then, a part of the passivation layer and the mask layer are removed, the remaining part of the passivation layer and the mask layer is formed into a first mask portion and a second mask portion, and finally, the first mask portion and a part of the second mask portion are removed, so that the thickness from the third mask portion to the substrate structure is larger than that of the metal portions. According to the manufacturing method, the gap between the metal parts is fully filled by the residual second mask part, so that the thickness from the third mask part to the substrate structure is greater than that of the metal parts, connection of the third mask part and the passivation part on the surface of the metal parts is realized, the passivation part is prevented from collapsing towards the direction far away from the gap, and the problem that the residual passivation layer is easy to collapse in the process of etching the top metal layer in the prior art is solved.
In a specific embodiment of the present application, the passivation layer may be a single-layer film structure or a multi-layer film structure, in an embodiment of the present application, the passivation layer is a multi-layer film structure, and as shown in fig. 3, the step of forming the passivation layer 21 specifically includes: forming a first sub-passivation layer on an exposed surface of the metal portion 20 and an exposed surface of the base structure 10; a second sub-passivation layer is formed on a surface of the first sub-passivation layer away from the base structure 10, and the first sub-passivation layer and the second sub-passivation layer constitute the passivation layer 21. In the above steps, two passivation layers are formed on the surface of the metal portion, which can further protect the metal and the substrate structure and prevent the metal and the substrate structure from being scratched by moisture or mobile ions from diffusing.
The material of the passivation layer in the present application may be any material that meets the above requirements in the prior art, and may be selected by a person skilled in the art according to practical situations, and in a specific embodiment of the present application, the material of the first sub-passivation layer includes at least one of silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride. These materials can further protect the metal and substrate structure from moisture, scratching, or diffusion of mobile ions, etc.
The material of the passivation layer in the present application may be any material that meets the above requirements in the prior art, and may be selected by those skilled in the art according to practical situations, and in a specific embodiment of the present application, the material of the second sub-passivation layer includes at least one of ozone and tetraethoxysilane. These materials can further protect the metal and substrate structure from moisture, scratching, or diffusion of mobile ions, etc.
In a specific embodiment of the present application, a distance between a surface of the mask layer away from the substrate structure and the substrate structure is a third distance, and the third distance is greater than the first distance. The method can ensure that the gap between the metal parts can be still fully filled by the residual second mask part after subsequent etching and cleaning, so that the thickness from the residual second mask part to the substrate structure is greater than that of the metal parts, the connection between the residual second mask part and the passivation part on the surface of the metal parts is realized, the passivation part is prevented from collapsing in the direction far away from the gap, and the problem of collapse of the passivation part is further avoided.
In a specific embodiment of the present application, the material of the mask layer includes at least one of a photoresist and a silicon-glass bonded structure material. In practical applications, the photoresist can be directly used in general, and the remaining photoresist can directly serve as a thin film. In addition, the material of the mask layer can also be a silicon-glass bonding structure material.
In order to remove the mask material possibly remaining on the metal portion, in a specific embodiment of the present application, on the basis of including the above steps S101 to S105, a detailed step S105 is further detailed, as shown in fig. 5, the step specifically includes: the first mask portion and the second mask portion are cleaned to remove the first mask portion and a part of the second mask portion, and a third mask portion 60 is formed by the remaining part of the second mask portion. After the cleaning, it is sufficient to ensure that the distance between the surface of the third mask portion 60 away from the base structure 10 and the base structure 10 is greater than the distance between the surface of the metal portion 20 away from the base structure 10 and the base structure 10.
In another exemplary embodiment of the present application, a semiconductor structure is provided, which is fabricated by any of the above-described fabrication methods.
The semiconductor structure is formed by adopting any method, and the residual mask part is filled in the gap between the metal parts, so that the connection between the residual second mask part and the passivation part on the surface of the metal part is realized, the passivation part is prevented from collapsing in the direction far away from the gap, and the problem that the residual passivation layer is easy to collapse in the process of etching the top metal in the prior art is solved.
In yet another exemplary embodiment of the present application, there is provided a semiconductor structure, as shown in fig. 5, the package structure including:
a base structure 10;
a plurality of spaced apart metal portions 20 on the base structure 10;
the plurality of spaced metal portions 20 may not be formed to cover the entire base structure 10, and the spacing between the metal portions 20 may result in a portion of the base structure 10 being exposed, as shown in fig. 2.
A passivation part located on the side wall of the metal part, the partial surface of the metal part far away from the base structure and the base structure between two adjacent metal parts;
the passivation layer can be formed by deposition such as atomic layer deposition, chemical vapor deposition, etc., and can protect the metal part and the substrate structure from being scratched by moisture or diffusing mobile ions. The passivation layer may be formed in any suitable manner other than by deposition, such as epitaxial growth. The passivation portion is in two parts, one part is located on the surface of the metal portion away from the base structure, and the other part is located in the space between the metal portions.
A third mask portion 60 located between two adjacent metal portions 20, wherein a distance between a surface of the third mask portion 60 far from the base structure 10 and the base structure 10 is a first distance, a distance between a surface of the metal portion 20 far from the base structure 10 and the base structure 10 is a second distance, and the first distance is greater than the second distance, as shown in fig. 5.
The third mask portion is formed by removing the rest of the second mask portion, and a part of the first mask portion and the second mask portion can be removed by adopting a dry etching or wet etching mode, so that the rest of the second mask portion is ensured to overflow a gap between two adjacent metal portions, the passivation portions at the tops of the two adjacent metal portions are connected, and the passivation portions are prevented from collapsing in a direction away from the gap. The material of the first mask portion, the second mask portion and the third mask portion includes at least one of a photoresist and a silicon-glass bonded structure material. In practical applications, the photoresist can be directly used in general, and the remaining photoresist can directly serve as a thin film. In addition, the material of the mask layer can also be a silicon-glass bonding structure material.
In another specific embodiment of the present application, the passivation layer may be a single-layer film structure or a multi-layer film structure, and in an embodiment of the present application, the passivation layer is a multi-layer film structure, and provides a semiconductor structure, and the passivation portion includes: a first sub-passivation portion located on a surface of the metal portion and a surface of the base structure; and the second sub-passivation part is positioned on the surface of the first sub-passivation layer far away from the substrate structure.
The material of the passivation layer in the present application may be any material in the prior art that meets the above requirements, and those skilled in the art can select the material according to practical situations. In still another exemplary embodiment of the present application, a semiconductor structure is provided, wherein the material of the first sub-passivation includes at least one of silicon dioxide, silicon nitride, silicon oxide and silicon oxynitride, and the material of the second sub-passivation includes at least one of ozone and tetraethoxysilane. These materials can further protect the metal and substrate structure from moisture, scratching, or diffusion of mobile ions, etc.
From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:
1) In the manufacturing method, firstly, a plurality of spaced metal parts are formed on the substrate structure, a passivation layer and a mask layer are sequentially formed on the exposed surfaces of the metal parts and the substrate structure, then, part of the passivation layer and the mask layer are removed, the rest parts form a first mask part and a second mask part, and finally, the first mask part and part of the second mask part are removed, so that the thickness from the rest second mask part to the substrate structure is larger than that of the metal parts. According to the manufacturing method, the gap between the metal parts is fully filled by the residual second mask part, so that the thickness from the residual second mask part to the substrate structure is greater than that of the metal parts, the connection of the third mask part and the passivation part on the surface of the metal parts is realized, the passivation part is prevented from collapsing in the direction far away from the gap, and the problem that the residual passivation layer is easy to collapse in the process of etching top metal in the prior art is solved.
2) In the semiconductor structure of this application, form passivation portion on a plurality of spaced metal portions blunt, passivation portion is located the lateral wall of above-mentioned metal portion, on the partial surface of above-mentioned metal portion and the substrate structure between two adjacent metal portions, third mask portion fills between two adjacent above-mentioned metal portions, and the upper surface of third mask portion is higher than the upper surface of metal portion, realized the abundant filling of space between the metal portion like this, realized that third mask portion is connected with the passivation portion on metal portion surface, avoid passivation portion to collapse to the direction of keeping away from above-mentioned space, in the in-process of having alleviated the etching top layer metal among the prior art, the problem that remaining passivation layer sinks easily.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a base structure and forming a plurality of spaced metal portions on the base structure;
forming a passivation layer on an exposed surface of the metal part and an exposed surface of the base structure;
forming a mask layer on the exposed surface of the passivation layer;
removing part of the passivation layer and part of the mask layer on the surface of the metal part, wherein the rest passivation layer forms a passivation part, the rest mask layer positioned on one side of the metal part, which is far away from the substrate structure, forms a first mask part, and the mask layer positioned between two adjacent metal parts forms a second mask part;
and removing the first mask portion and a part of the second mask portion, so that the surface of the remaining second mask portion, which is far away from the base structure, is a first distance from the base structure, the surface of the metal portion, which is far away from the base structure, is a second distance from the base structure, and the first distance is greater than the second distance.
2. The method of claim 1, wherein forming a passivation layer on exposed surfaces of the metal portion and the base structure comprises:
forming a first sub-passivation layer on an exposed surface of the metal part and an exposed surface of the base structure;
and forming a second sub-passivation layer on the surface of the first sub-passivation layer far away from the substrate structure, wherein the first sub-passivation layer and the second sub-passivation layer form the passivation layer.
3. The method of manufacturing according to claim 2, wherein the material of the first sub-passivation layer comprises at least one of silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride.
4. The method of claim 2, wherein the material of the second sub-passivation layer comprises at least one of ozone and tetraethoxysilane.
5. The method according to any one of claims 1 to 4, wherein a distance between a surface of the mask layer away from the substrate structure and the substrate structure is a third distance, and the third distance is greater than the first distance.
6. The method according to any one of claims 1 to 4, wherein a material of the mask layer includes at least one of a photoresist and a silicon-glass bonded structure material.
7. The method of manufacturing according to claim 1, wherein removing the first mask portion and a portion of the second mask portion comprises:
and cleaning the first mask portion and the second mask portion to remove the first mask portion and a part of the second mask portion, wherein the remaining part of the second mask portion forms a third mask portion.
8. A semiconductor structure, comprising:
a base structure;
a plurality of spaced apart metal portions on the base structure;
the passivation part is positioned on the side wall of the metal part, the partial surface of the metal part far away from the base structure and the base structure between two adjacent metal parts;
and the third mask part is positioned between two adjacent metal parts, wherein the distance between the surface of the third mask part far away from the base structure and the base structure is a first distance, the distance between the surface of the metal part far away from the base structure and the base structure is a second distance, and the first distance is greater than the second distance.
9. The semiconductor structure of claim 8, wherein the passivation portion comprises:
a first sub-passivation portion on a surface of the metal portion and a surface of the base structure;
and the second sub-passivation part is positioned on the surface of the first sub-passivation layer far away from the substrate structure.
10. The semiconductor structure of claim 9, wherein the material of the first sub-passivation comprises at least one of silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride, and the material of the second sub-passivation comprises at least one of ozone and tetraethoxysilane.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700737A (en) * | 1996-02-26 | 1997-12-23 | Taiwan Semiconductor Manufactured Company Ltd. | PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination |
| CN101099241A (en) * | 2004-12-07 | 2008-01-02 | 英特尔公司 | A method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
| CN101859697A (en) * | 2009-04-09 | 2010-10-13 | 旺宏电子股份有限公司 | Patterning method and integrated circuit structure |
| US20160027664A1 (en) * | 2014-07-24 | 2016-01-28 | International Business Machines Corporation | Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme |
| CN106463455A (en) * | 2014-07-08 | 2017-02-22 | 盛美半导体设备（上海）有限公司 | Method for forming metal interconnection |
| CN108122782A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| US20190333857A1 (en) * | 2018-04-25 | 2019-10-31 | International Business Machines Corporation | Metal interconnects |
| CN113451141A (en) * | 2020-03-26 | 2021-09-28 | 深圳市明微电子股份有限公司 | Double-passivation-layer structure of semiconductor device and preparation method thereof |
| CN115036215A (en) * | 2021-03-08 | 2022-09-09 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
-
2023
- 2023-01-19 CN CN202310056579.2A patent/CN115881549B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700737A (en) * | 1996-02-26 | 1997-12-23 | Taiwan Semiconductor Manufactured Company Ltd. | PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination |
| CN101099241A (en) * | 2004-12-07 | 2008-01-02 | 英特尔公司 | A method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
| CN101859697A (en) * | 2009-04-09 | 2010-10-13 | 旺宏电子股份有限公司 | Patterning method and integrated circuit structure |
| CN106463455A (en) * | 2014-07-08 | 2017-02-22 | 盛美半导体设备（上海）有限公司 | Method for forming metal interconnection |
| US20160027664A1 (en) * | 2014-07-24 | 2016-01-28 | International Business Machines Corporation | Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme |
| CN108122782A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| US20190333857A1 (en) * | 2018-04-25 | 2019-10-31 | International Business Machines Corporation | Metal interconnects |
| CN113451141A (en) * | 2020-03-26 | 2021-09-28 | 深圳市明微电子股份有限公司 | Double-passivation-layer structure of semiconductor device and preparation method thereof |
| CN115036215A (en) * | 2021-03-08 | 2022-09-09 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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