CN102420201B - Silicon through hole structure and manufacturing method thereof - Google Patents
Silicon through hole structure and manufacturing method thereof Download PDFInfo
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- CN102420201B CN102420201B CN 201110363430 CN201110363430A CN102420201B CN 102420201 B CN102420201 B CN 102420201B CN 201110363430 CN201110363430 CN 201110363430 CN 201110363430 A CN201110363430 A CN 201110363430A CN 102420201 B CN102420201 B CN 102420201B
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Abstract
The invention discloses a manufacturing method of a silicon through hole structure. The manufacturing method comprises the following steps of: reducing the thickness of a silicon chip to be 5-20 micrometers; removing all insulating layers on the surface of the silicon chip; manufacturing doping masks on the surface of a conducting region and the surface of an insulating region on the silicon chip for respectively carrying out particle doping on the conducting region and the insulating region, wherein the polarity of the particles doped in the insulating region is opposite to that of the particles doped in the conducting region; after the particle doping is finished, removing the doping masks; covering a metal electrode on the surface of the conducting region; and covering an insulating layer in a region on the surface of the silicon chip,, which is beyond a metal electrode. According to the manufacturing method disclosed by the invention, the process is simple; the damage to the silicon chip, caused by an etching process, an insulated treatment process and the like can be avoided; and the finished product rate of the silicon through hole structure can be increased. The invention further discloses the silicon through hole structure.
Description
Technical field
The present invention relates to a kind of through-silicon via structure and manufacture method thereof.
Background technology
Silicon through hole technology is a kind of encapsulation technology of hot topic, and its main technical flows is wafer thinning, etch silicon through hole, conductive materials filling silicon through holes and little capping and bonding with silicon through hole silicon chip.
There are some problems in present through-silicon via structure: first, the etch silicon through hole can be to the silicon chip injury, cause the silicon chip structural deterioration, and it is large to etch silicon through hole technical difficulty vertical and that the sidewall pattern good (level and smooth and the aperture is consistent), be difficult to realize the bad shape of silicon through hole and pattern having a significant impact the packaging performance; Second, the conductive materials of filling silicon through holes is mainly metal (such as copper and tungsten), and the thermal coefficient of expansion of they and silicon is different, therefore have electric current by the time have thermal stress between metal and silicon, seriously cause the silicon chip cracking, thus reliability and the life-span of reducing Vacuum Package.
Accordingly, also there is following problem in the manufacture method of silicon through hole at present: the first, and silicon via etch process consistency is difficult to resolve certainly, and etch period is long, and easily causes silicon chip to destroy, and has reduced rate of finished products; The second, with needing before the conductive materials filling silicon through holes that through-silicon via sidewall is carried out insulation processing, because the sidewall pattern of silicon through hole is not fully level and smooth with vertical, so be difficult to ensure that demonstrate,proving really through-silicon via sidewall all can realize good insulation; The 3rd, the conductive materials filling silicon through holes is generally to electroplate or the metals such as chemical vapour deposition (CVD) copper, tungsten are realized, but present this fill method easily produces the space, and the electrical property of packaging and the air-tightness of encapsulation are kept causing adverse effect; The 4th, no matter be etch silicon through hole or conductive materials fill process, processing step is loaded down with trivial details, and time-consuming is long, has affected manufacturing efficient.
Summary of the invention
One object of the present invention is to provide a kind of through-silicon via structure, and its manufacturing process is simple, reliability and the life-span that can improve Vacuum Package simultaneously.
Another object of the present invention is to provide a kind of manufacture method of through-silicon via structure, and its manufacturing process is simple, can avoid the techniques such as etching, insulation processing to the destruction of silicon chip, and can improve the rate of finished products of making through-silicon via structure.
Technical scheme of the present invention is as follows:
A kind of through-silicon via structure, it is formed on silicon chip, and comprise conduction region and the insulation layer that the doping particle consists of, it is characterized in that: insulation layer is opposite with the polarity of the particle of conduction region doping, the conduction region surface coverage has metal electrode, and the zone of the surface of silicon chip except metal electrode is coated with insulating barrier.
A kind of manufacture method of through-silicon via structure comprises the following steps: with the reduced thickness to 5 of silicon chip micron to 20 microns; Remove all insulating barriers of silicon chip surface; At conduction region surface and the insulation layer surface making doping mask of silicon chip, so that conduction region and insulation layer are carried out respectively the particle doping, insulation layer is opposite with the polarity of the particle of conduction region doping; After completing, the particle doping removes the doping mask; At conduction region surface coverage metal electrode; The zone of surface except metal electrode at silicon chip covers insulating barrier.
Adopt chemico-mechanical polishing, mechanical grinding or wet etching to carry out attenuate to silicon chip.
The step of removing all insulating barriers of silicon chip surface comprises: cleaning silicon chip, to remove the impurity such as its surperficial dust, particle; Remove all insulating barriers of silicon chip surface by etching technics.
The step of conduction region being carried out the particle doping comprises: cover one deck photoresist or metal on silicon chip surface; Remove the photoresist or the metal that cover on the conduction region surface of silicon chip; Conduction region to silicon chip carries out the particle doping.
The step of insulation layer being carried out the particle doping comprises: cover one deck photoresist or metal on silicon chip surface; Remove the photoresist or the metal that cover on the insulation layer surface of silicon chip; Insulation layer to silicon chip carries out the particle doping.
Step at conduction region surface coverage metal electrode comprises: cover one deck photoresist on silicon chip surface; By photoetching with develop to remove the photoresist on the conduction region surface of silicon chip; Cover layer of metal on silicon chip surface; The residue photoresist on stripping silicon chip surface.
Step at conduction region surface coverage metal electrode also can comprise: cover layer of metal on silicon chip surface; Cover one deck photoresist on metal; By photoetching with develop to remove photoresist outside the conduction region surface of silicon chip; Remove the metal outside the conduction region surface of silicon chip by etching technics; Remove the residue photoresist of silicon chip surface.
The step that covers insulating barrier in the zone of surface except metal electrode of silicon chip comprises: cover one deck photoresist on silicon chip surface; By photoetching with develop to remove photoresist outside the conduction region surface of silicon chip; Cover insulating barrier on silicon chip surface; The residue photoresist on stripping silicon chip surface.
The step that covers insulating barrier in the zone of surface except metal electrode of silicon chip also can comprise: cover layer of metal on silicon chip surface; Cover one deck photoresist on metal; By photoetching with develop to remove the photoresist on the conduction region surface of silicon chip; Remove the insulating barrier on the conduction region surface of silicon chip by etching technics; Remove the residue photoresist of silicon chip surface.
The advantage of through-silicon via structure of the present invention is: the conduction region and the insulation layer that form through-silicon via structure by the particle doping way, the matrix of conduction region and insulation layer all or silicon chip itself, avoid the metal thermal stress issues that cause different from the silicon chip thermal coefficient of expansion in present silicon through hole technology, can improve device reliability and life-span; Simultaneously, because the actual silicon through hole of through-silicon via structure of the present invention is replaced by conduction region and insulation layer through the particle doping, there is not the problem of gas leakage in through-silicon via structure, and its good air-tightness can apply to the Vacuum Package field and improve the air-tightness maintenance life-span of encapsulation.
The advantage of the manufacture method of through-silicon via structure of the present invention is: compare with the silicon through hole manufacturing technology of present main flow, the present invention does not need silicon chip is carried out the silicon via etch, also do not need the fill process such as through-silicon via sidewall insulation processing, adhesion layer, barrier metal sputter, silicon the electroplates in hole or chemical vapour deposition (CVD), reduced technology difficulty, improved manufacturing efficient, avoid simultaneously the destruction of the techniques such as etching, insulation processing to silicon chip, thereby can improve the rate of finished products of making through-silicon via structure.
Description of drawings
Fig. 1 is the schematic diagram of through-silicon via structure of the present invention.
Fig. 2 is the cutaway view of Fig. 1.
Fig. 3 is the flow chart of the manufacture method of through-silicon via structure of the present invention.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
As shown in Figure 1 and Figure 2, through-silicon via structure of the present invention is formed on silicon chip 1, and comprises conduction region 2 and insulation layer 3 that the doping particle consists of.Conduction region 2 surface coverage have metal electrode 4, and the zone of the surface of silicon chip except metal electrode 4 is coated with insulating barrier 5.
As shown in Figure 3, the manufacture method of silicon through hole of the present invention comprises the following steps:
(1) with the reduced thickness to 5 of silicon chip micron to 20 microns;
(2) remove all insulating barriers of silicon chip surface;
(3) at conduction region surface and the insulation layer surface making doping mask of silicon chip, so that conduction region and insulation layer are carried out respectively the particle doping, insulation layer is opposite with the polarity of the particle of conduction region doping;
(4) after completing, the particle doping removes the doping mask;
(5) at conduction region surface coverage metal electrode;
(6) cover insulating barrier in the zone of surface except metal electrode of silicon chip.
In step (1), be to adopt chemico-mechanical polishing, mechanical grinding or wet etching to carry out attenuate to silicon chip.
Step (2) further comprises following substep:
(21) cleaning silicon chip is to remove the impurity such as its surperficial dust, particle;
(22) remove all insulating barriers of silicon chip surface by etching technics.
In the present embodiment, etching technics comprises wet etching and dry etching.
In step (3), the step of conduction region being carried out the particle doping comprises following substep:
(31) cover one deck photoresist or metal on silicon chip surface;
(32) by photoetching with develop to remove photoresist or the metal that covers on the conduction region surface of silicon chip;
(33) conduction region of silicon chip carried out the particle doping.
In step (32), if silicon chip surface covers be photoresist, adopt the photoresist that covers on the conduction region surface of photoetching and developing method removal silicon chip; If what silicon chip surface covered be metal, adopt the metal that covers on the conduction region surface of photoetching, development and lithographic method removal silicon chip.
In step (3), the step of insulation layer being carried out the particle doping comprises following substep:
(34) cover one deck photoresist or metal on silicon chip surface;
(35) remove photoresist or the metal that covers on the insulation layer surface of silicon chip;
(36) insulation layer of silicon chip carried out the particle doping.
In step (35), if silicon chip surface covers be photoresist, adopt the photoresist that covers on the insulation layer surface of photoetching and developing method removal silicon chip; If what silicon chip surface covered be metal, adopt the metal that covers on the insulation layer surface of photoetching, development and lithographic method removal silicon chip.
The particle of doping is one or more in triad and pentad, and the doping mask is to be made by photoresist or metal.
Step (5) further comprises following substep:
(51) cover one deck photoresist on silicon chip surface;
(52) by photoetching with develop to remove the photoresist on the conduction region surface of silicon chip;
(53) cover layer of metal on silicon chip surface;
(54) the residue photoresist on stripping silicon chip surface.
Perhaps, step (5) can comprise following substep:
(51 ') covers layer of metal on silicon chip surface;
(52 ') covers one deck photoresist on metal;
(53 ') is by photoetching and develop to remove photoresist outside the conduction region surface of silicon chip;
(54 ') removes the metal outside the conduction region surface of silicon chip by etching technics;
(55 ') removes the residue photoresist of silicon chip surface.
Step (6) further comprises following substep:
(61) cover one deck photoresist on silicon chip surface;
(62) by photoetching with develop to remove photoresist outside the conduction region surface of silicon chip;
(63) cover insulating barrier on silicon chip surface;
(64) the residue photoresist on stripping silicon chip surface.
Perhaps, step (6) can comprise following substep:
(61 ') covers insulating barrier on silicon chip surface;
(62 ') covers one deck photoresist on insulating barrier;
(63 ') is by photoetching and develop to remove the photoresist on the conduction region surface of silicon chip;
(64 ') removes the insulating barrier on the conduction region surface of silicon chip by etching technics;
(65 ') removes the residue photoresist of silicon chip surface.
In the present embodiment, insulating barrier is to be made by silicon nitride or silicon dioxide.
Example 1:
At first, by chemico-mechanical polishing, silicon chip 1 twin polishing is thinned to 5 micron thickness.
Thereafter, cleaning silicon chip 1 to remove the impurity such as its surperficial dust, particle, is removed all insulating barriers on silicon chip 1 surface by reactive ion etching.
, cover one deck photoresist on silicon chip 1 surface, by photoetching with develop and remove the silicon chip 1 conduction region 2 upper photoresists that cover in surface, make the doping mask with remaining photoresist on silicon chip 1 thereafter, by Implantation to conduction region 2 doping pentad phosphorus.
Thereafter, the photoresist on removal silicon chip 1 surface after the particle doping is completed.
, cover one deck photoresist on silicon chip 1 surface, by photoetching with the insulation layer 3 upper photoresists that cover in surface that develop and remove silicon chip 1, make the doping mask with remaining photoresist on silicon chip 1 thereafter, by Implantation to insulation layer 3 doping triad boron.
Thereafter, the photoresist on removal silicon chip 1 surface after the particle doping is completed.
, on silicon chip 1 surface cover one deck photoresist thereafter, by photoetching with the photoresist on conduction region 2 surfaces of removing silicon chip of developing, then at silicon chip 1 upper surface sputter layer of metal copper, the photoresist on stripping silicon chip 1 surface.
At last, cover one deck photoresist on 1 surface on silicon chip, by photoetching with develop to remove photoresist outside conduction region 2 surfaces of silicon chip 1, at silicon chip 1 upper surface by the low-pressure chemical vapor deposition silicon dioxide insulating layer 5 of growing, the residue photoresist on stripping silicon chip 1 surface.
Example 2:
At first, by mechanical grinding, silicon chip 1 twin polishing is thinned to 20 micron thickness.
Thereafter, cleaning silicon chip 1 to remove the impurity such as its surperficial dust, particle, carries out wet etching by hydroflouric acid, to remove all insulating barriers on silicon chip 1 surface.
Thereafter, sputter one deck titanium on silicon chip 1 surface, cover one deck photoresist on titanium layer, by photoetching and the removal silicon chip 1 conduction region 2 upper photoresists that cover in surface that develop, remove the silicon chip 1 lip-deep titanium of conduction region 2 with induction ion coupling etching technics, make the doping mask with remaining titanium on silicon chip 1, by thermal diffusion process to conduction region 2 doping triad boron.
Thereafter, the titanium on removal silicon chip 1 surface after the particle doping is completed.
Thereafter, sputter one deck titanium on silicon chip 1 surface, cover one deck photoresist on titanium layer, by photoetching and the removal silicon chip 1 insulation layer 3 upper photoresists that cover in surface that develop, remove the silicon chip 1 lip-deep titanium of insulation layer 3 with induction ion coupling etching technics, make the doping mask with remaining titanium on silicon chip 1, by thermal diffusion process to insulation layer 3 doping pentad phosphorus.
Thereafter, the titanium on removal silicon chip 1 surface after the particle doping is completed.
Thereafter, sputter one deck titanium on silicon chip 1 surface covers one deck photoresist on titanium layer, by photoetching with develop and remove the photoresist that covers outside silicon chip 1 conduction region 2 surfaces, remove titanium outside 2 surfaces, conductive wafer district by induction ion coupling etching technics, the photoresist on stripping silicon chip 1 surface.
At last, covering insulating barrier on 1 surface on silicon chip, cover one deck photoresist on insulating barrier, the lip-deep photoresist of conduction region 2 by photoetching and the removal silicon chip 1 that develops, remove the insulating barrier on conduction region 2 surfaces of silicon chip by induction ion coupling etching technics, the residue photoresist on stripping silicon chip 1 surface.
Claims (9)
1. the manufacture method of a through-silicon via structure comprises the following steps:
With the reduced thickness to 5 of silicon chip micron to 20 microns;
Remove all insulating barriers of described silicon chip surface;
At conduction region surface and the insulation layer surface making doping mask of described silicon chip, so that described conduction region and described insulation layer are carried out respectively the particle doping, described insulation layer is opposite with the polarity of the particle of described conduction region doping;
After completing, the particle doping removes described doping mask;
At described conduction region surface coverage metal electrode;
The zone of surface except described metal electrode at described silicon chip covers insulating barrier.
2. manufacture method according to claim 1, is characterized in that: adopt chemico-mechanical polishing, mechanical grinding or wet etching to carry out attenuate to described silicon chip.
3. manufacture method according to claim 1, is characterized in that, the step of all insulating barriers of the described silicon chip surface of described removal comprises:
Clean described silicon chip, to remove its surperficial dust, granule foreign;
Remove all insulating barriers of described silicon chip surface by etching technics.
4. manufacture method according to claim 1, is characterized in that, the described step that described conduction region is carried out particle doping comprises:
Cover one deck photoresist or metal on described silicon chip surface;
Remove the photoresist or the metal that cover on the conduction region surface of described silicon chip;
Conduction region to described silicon chip carries out the particle doping.
5. manufacture method according to claim 1, is characterized in that, the described step that described insulation layer is carried out particle doping comprises:
Cover one deck photoresist or metal on described silicon chip surface;
Remove the photoresist or the metal that cover on the insulation layer surface of described silicon chip;
Insulation layer to described silicon chip carries out the particle doping.
6. manufacture method according to claim 1, is characterized in that, described step at described conduction region surface coverage metal electrode comprises:
Cover one deck photoresist on described silicon chip surface;
By photoetching with develop to remove the photoresist on the conduction region surface of described silicon chip;
Cover layer of metal on described silicon chip surface;
Peel off the residue photoresist of described silicon chip surface.
7. manufacture method according to claim 1, is characterized in that, described step at described conduction region surface coverage metal electrode comprises:
Cover layer of metal on described silicon chip surface;
Cover one deck photoresist on described metal;
By photoetching with develop to remove photoresist outside the conduction region surface of described silicon chip;
Remove the metal outside the conduction region surface of described silicon chip by etching technics;
Remove the residue photoresist of described silicon chip surface.
8. manufacture method according to claim 1 is characterized in that: the step that the described zone of surface except described metal electrode at described silicon chip covers insulating barrier comprises:
Cover one deck photoresist on described silicon chip surface;
By photoetching with develop to remove photoresist outside the conduction region surface of described silicon chip;
Cover insulating barrier on described silicon chip surface;
Peel off the residue photoresist on described silicon chip 1 surface.
9. manufacture method according to claim 1 is characterized in that: the step that the described zone of surface except described metal electrode at described silicon chip covers insulating barrier comprises:
Cover insulating barrier on described silicon chip surface;
Cover one deck photoresist on described insulating barrier;
By photoetching with develop to remove the photoresist on the conduction region surface of described silicon chip;
Remove the insulating barrier on the conduction region surface of described silicon chip by etching technics;
Remove the residue photoresist of described silicon chip surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110363430 CN102420201B (en) | 2011-11-16 | 2011-11-16 | Silicon through hole structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110363430 CN102420201B (en) | 2011-11-16 | 2011-11-16 | Silicon through hole structure and manufacturing method thereof |
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| CN102420201A CN102420201A (en) | 2012-04-18 |
| CN102420201B true CN102420201B (en) | 2013-05-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107843277A (en) * | 2017-12-25 | 2018-03-27 | 上海恩弼科技有限公司 | Optical encoder and preparation method thereof |
| CN109522649B (en) * | 2018-11-16 | 2023-03-14 | 西安电子科技大学 | Silicon through hole TSV array temperature optimization method based on orthogonal test |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
| US3988764A (en) * | 1973-10-30 | 1976-10-26 | General Electric Company | Deep diode solid state inductor coil |
| CN1261410A (en) * | 1997-06-20 | 2000-07-26 | 约翰内斯·海登海因博士有限公司 | Method and device for producing electrically conductive contiuity in semiconductor components. |
| CN101752277A (en) * | 2008-12-01 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | System-in-a-package method and structure thereof |
| CN202332838U (en) * | 2011-11-16 | 2012-07-11 | 华中科技大学 | Through silicon via structure |
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- 2011-11-16 CN CN 201110363430 patent/CN102420201B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
| US3988764A (en) * | 1973-10-30 | 1976-10-26 | General Electric Company | Deep diode solid state inductor coil |
| CN1261410A (en) * | 1997-06-20 | 2000-07-26 | 约翰内斯·海登海因博士有限公司 | Method and device for producing electrically conductive contiuity in semiconductor components. |
| CN101752277A (en) * | 2008-12-01 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | System-in-a-package method and structure thereof |
| CN202332838U (en) * | 2011-11-16 | 2012-07-11 | 华中科技大学 | Through silicon via structure |
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| CN102420201A (en) | 2012-04-18 |
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