JP2007335659A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2007335659A
JP2007335659A JP2006166178A JP2006166178A JP2007335659A JP 2007335659 A JP2007335659 A JP 2007335659A JP 2006166178 A JP2006166178 A JP 2006166178A JP 2006166178 A JP2006166178 A JP 2006166178A JP 2007335659 A JP2007335659 A JP 2007335659A
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wafer
etching
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semiconductor wafer
manufacturing
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JP4816278B2 (en
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Manabu Takei
学 武井
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Fuji Electric Co Ltd
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<P>PROBLEM TO BE SOLVED: To reduce cracking or warpage in a semiconductor wafer in steps of manufacturing a thin semiconductor device. <P>SOLUTION: An oxide film 13 as an etching resistance protective film is formed on front and rear surfaces of a wafer 11 having an element structure formed in its front side. The oxide film 13 formed on the rear surface of the wafer 11 is then removed while leaving a part of the wafer 11 corresponding to a predetermined width from its outer peripheral end. The rear surface of the wafer 11 is etched down to a predetermined depth and thereafter, the oxide films 13 are removed as left at the outer peripheral ends of the front and rear surfaces of the wafer 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、半導体装置の製造方法に関し、特に半導体ウエハーの薄層化によって特性が向上するパワー半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a power semiconductor device whose characteristics are improved by thinning a semiconductor wafer.

従来、半導体ウエハー(以下、「ウエハー」という)の薄層化は、チップ積層型のパッケージやパワー半導体装置の特性向上に不可欠の技術となっている。ウエハーを薄層化する際には、ウエハーを裏面から研削し(バックグラインド)、所望の厚さとするのが一般的である。しかし、単純にバックグラインドをおこなうと、ウエハーの機械的強度が低下して割れやすくなる。また、ウエハーの表面に形成した金属電極などの膜内の内部応力によってウエハーが反りやすくなる。例えば、直径6インチのシリコンウエハーを100μm以下の厚さに薄層化した場合、割れや反りによるウエハーの不良率が急激に増加してしまう。   Conventionally, the thinning of a semiconductor wafer (hereinafter referred to as “wafer”) has become an indispensable technique for improving the characteristics of chip stacked packages and power semiconductor devices. When thinning a wafer, it is common to grind the wafer from the back surface (back grind) to obtain a desired thickness. However, if the back grinding is simply performed, the mechanical strength of the wafer is reduced and the wafer is easily broken. In addition, the wafer is likely to warp due to internal stress in the film such as a metal electrode formed on the surface of the wafer. For example, when a silicon wafer having a diameter of 6 inches is thinned to a thickness of 100 μm or less, the defect rate of the wafer due to cracking or warping increases rapidly.

このようなウエハーの不良率を低減するため、ウエハーに支持基板を接着させて製造工程を進める支持基板方式が知られている。支持基板方式では、バックグラインド前のウエハーの表面に接着剤などによって支持基板を接着し、支持基板を接着した状態のウエハーに対して、バックグラインドおよびその後の製造工程をおこなう。この方式によれば、ウエハーが支持基板と接着されているため、製造工程におけるウエハーの割れや反りを低減することができる。   In order to reduce the defect rate of such a wafer, a support substrate system is known in which a support substrate is bonded to a wafer and a manufacturing process is advanced. In the support substrate method, the support substrate is bonded to the surface of the wafer before back grinding with an adhesive or the like, and the back grinding and the subsequent manufacturing process are performed on the wafer with the support substrate bonded thereto. According to this method, since the wafer is bonded to the support substrate, it is possible to reduce the cracking and warping of the wafer in the manufacturing process.

また、支持基板を用いずにウエハーを薄層化する方法として、TAIKOプロセスと呼ばれる方法が知られている(例えば、下記非特許文献1参照。)。TAIKOプロセスでは、ウエハーの外周を数mmを残してウエハー中央部のみを機械研削して、ウエハーを薄層化する。この方式によれば、ウエハーの外周端部は研削されずに元の厚さのまま残るので、機械的強度が保たれ、ウエハーの割れや反りを低減することができる。   As a method for thinning a wafer without using a support substrate, a method called a TAIKO process is known (for example, see Non-Patent Document 1 below). In the TAIKO process, the wafer is thinned by mechanically grinding only the central portion of the wafer, leaving a few mm on the outer periphery of the wafer. According to this method, the outer peripheral end portion of the wafer is not ground and remains in its original thickness, so that the mechanical strength is maintained and the cracking and warping of the wafer can be reduced.

また、ウエハーの両面にレジストを塗布した後、ウエハー裏面のレジストを外周端部を残して除去し、残ったレジストをマスクとして弗硝酸でエッチングしてウエハーを薄層化する方法や、ウエハーの両面に酸化膜を形成し、ウエハー裏面の膜を外周端部を残して除去し、残った酸化膜をマスクとして水酸化カリウムでエッチングしてウエハーを薄層化する方法が知られている(例えば、下記特許文献1参照。)。また、エッチングポットに設けられたシールパッキンでウエハーの外周端部をマスクし、ウエハー中央部の露出面をエッチング液にさらすことによって、ウエハーを薄層化する方法が知られている(例えば、下記特許文献2参照。)。   Also, after applying the resist on both sides of the wafer, the resist on the back side of the wafer is removed leaving the outer peripheral edge, and the remaining resist is used as a mask to etch the wafer with hydrofluoric acid, or both sides of the wafer. A method is known in which an oxide film is formed on the wafer, and the film on the back surface of the wafer is removed leaving the outer peripheral edge, and the wafer is thinned by etching with potassium hydroxide using the remaining oxide film as a mask (for example, (See Patent Document 1 below.) Also known is a method of thinning the wafer by masking the outer peripheral edge of the wafer with a seal packing provided in the etching pot and exposing the exposed surface of the wafer center to an etching solution (for example, the following) (See Patent Document 2).

特開2004−253527号公報JP 2004-253527 A 特許第3620528号公報Japanese Patent No. 3620528 ディスコ社ウェブサイト、[online]、[平成17年12月12日検索]、インターネット<URL:http://www.disco.co.jp/jp/news/product/20051128.html>Disco website, [online], [December 12, 2005 search], Internet <URL: http: // www. disco. co. jp / jp / news / product / 20051128. html>

しかしながら、上述した支持基板方式を用いると、ウエハーの割れや反りを低減できるものの、支持基板や接着剤の性質に影響を与えるような高温の熱処理をおこなうことができないため、製造工程でおこなう処理が制限されてしまうという問題点がある。また、支持基板の貼り付けおよび剥離に専用の装置が必要となるため、半導体装置の製造コストが上昇してしまうという問題点がある。   However, using the above-described support substrate method can reduce the cracking and warping of the wafer, but cannot perform high-temperature heat treatment that affects the properties of the support substrate and the adhesive, so the processing performed in the manufacturing process There is a problem that it is restricted. In addition, since a dedicated device is required for attaching and peeling the support substrate, there is a problem that the manufacturing cost of the semiconductor device increases.

また、上述したTAIKOプロセスでは、専用のグラインダーが必要となるため、半導体装置の製造コストが上昇してしまうという問題点がある。また、ウエハーのおもて面に形成された素子構造によって段差ができているため、機械的方法で研削をおこなうと、その段差に加わる力によってウエハーが割れてしまうという問題点がある。例えば、おもて面がポリイミド膜で保護されたパワー半導体装置では、おもて面の段差が5μm以上あるため、ウエハーを100μm以下の厚さに研削すると、大部分のウエハーが割れてしまう。   Further, the above-described TAIKO process requires a dedicated grinder, which increases the manufacturing cost of the semiconductor device. Further, since a step is formed by the element structure formed on the front surface of the wafer, there is a problem that when grinding is performed by a mechanical method, the wafer is broken by a force applied to the step. For example, in a power semiconductor device in which the front surface is protected by a polyimide film, since the step on the front surface is 5 μm or more, when the wafer is ground to a thickness of 100 μm or less, most of the wafers are broken.

また、上述した特許文献1の方法では、ウエハー裏面の酸化膜を除去する際、どのようにして外周端部に酸化膜を残すかが不明である。また、上述した特許文献2の方法では、エッチングポットが枚葉式であるため、バッチ処理をおこなえず、ディップ方式と比べて生産効率が悪いという問題点がある。   Further, in the method of Patent Document 1 described above, it is unclear how to leave the oxide film at the outer peripheral edge when removing the oxide film on the back surface of the wafer. Further, in the method of Patent Document 2 described above, since the etching pot is a single-wafer type, batch processing cannot be performed, and there is a problem that production efficiency is poor as compared with the dip method.

この発明は、上述した従来技術による問題点を解消するため、生産コストを抑えつつ、ウエハーの薄層化を含む製造工程における割れや反りを低減することができる半導体装置の製造方法を提供することを目的とする。   The present invention provides a method for manufacturing a semiconductor device capable of reducing cracks and warpage in a manufacturing process including wafer thinning while suppressing production costs in order to eliminate the above-described problems caused by the prior art. With the goal.

上述した課題を解決し、目的を達成するため、請求項1の発明にかかる半導体装置の製造方法は、半導体ウエハーの第1主面および第2主面に耐エッチング保護膜となる酸化膜または窒化膜を形成する形成工程と、前記耐エッチング保護膜をフォトレジストで被覆する被覆工程と、フォトリソグラフィによって、前記フォトレジストのうち、前記半導体ウエハーの第2主面側のフォトレジストを外周端部から所定の幅を残して除去するレジスト除去工程と、前記半導体ウエハーの第2主面側の外周端部に残る前記フォトレジストをマスクとして、前記耐エッチング保護膜のうち、前記半導体ウエハーの第2主面に形成された耐エッチング保護膜を外周端部から所定の幅を残して除去する第1の除去工程と、前記耐エッチング保護膜が外周端部を残して除去された前記半導体ウエハーの第2主面を所定の深さまでエッチングするエッチング工程と、エッチング後の前記半導体ウエハーの第1主面と第2主面の外周端部に残る前記耐エッチング保護膜を除去する第2の除去工程と、を含んだことを特徴とする。   In order to solve the above-described problems and achieve the object, a method of manufacturing a semiconductor device according to the invention of claim 1 includes an oxide film or a nitridation serving as an etching resistant protective film on the first main surface and the second main surface of a semiconductor wafer A forming step for forming a film, a covering step for covering the etching-resistant protective film with a photoresist, and a photoresist on the second main surface side of the semiconductor wafer from the outer peripheral end portion of the photoresist by photolithography. A resist removing step for removing the resist film while leaving a predetermined width, and a second main surface of the semiconductor wafer among the etching-resistant protective films, using the photoresist remaining at the outer peripheral end portion on the second main surface side of the semiconductor wafer as a mask. A first removing step of removing the etching-resistant protective film formed on the surface from the outer peripheral edge part leaving a predetermined width; and An etching process for etching the second main surface of the semiconductor wafer that has been removed and removed to a predetermined depth, and the anti-etching protection remaining on the outer peripheral ends of the first main surface and the second main surface of the semiconductor wafer after etching And a second removal step of removing the film.

この請求項1の発明によれば、半導体ウエハーを外周端部から所定の幅を残してエッチングして、厚さを減じる。これにより、厚さを減じて薄層化した半導体ウエハーの強度を保ち、半導体ウエハーの割れや反りを防止することができる。また、専用の装置を必要としないため、低コストで薄層化した半導体装置を製造することができる。   According to the first aspect of the present invention, the thickness of the semiconductor wafer is reduced by etching the semiconductor wafer leaving a predetermined width from the outer peripheral end portion. Thereby, the strength of the semiconductor wafer thinned by reducing the thickness can be maintained, and cracking and warping of the semiconductor wafer can be prevented. In addition, since a dedicated device is not required, a thin semiconductor device can be manufactured at low cost.

また、請求項2の発明にかかる半導体装置の製造方法は、請求項1に記載の発明において、あらかじめ前記半導体ウエハーの第1主面に半導体素子またはその一部が作製されていることを特徴とする。   According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein a semiconductor element or a part of the semiconductor element is fabricated on the first main surface of the semiconductor wafer in advance. To do.

この請求項2の発明によれば、半導体ウエハーの第1主面に作製された半導体素子またはその一部を保護しつつ、半導体ウエハーを薄層化することができる。   According to the second aspect of the present invention, the semiconductor wafer can be thinned while protecting the semiconductor element produced on the first main surface of the semiconductor wafer or a part thereof.

また、請求項3の発明にかかる半導体装置の製造方法は、請求項2に記載の発明において、前記耐エッチング保護膜は、500℃以下の熱処理によって形成されることを特徴とする。   According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the second aspect, wherein the etching-resistant protective film is formed by a heat treatment at 500 ° C. or lower.

この請求項3の発明によれば、半導体ウエハーの第1主面に作製された半導体素子またはその一部が、耐エッチング保護膜の形成時の熱処理によって変質するのを防止することができる。   According to the third aspect of the present invention, it is possible to prevent the semiconductor element produced on the first main surface of the semiconductor wafer or a part thereof from being deteriorated by the heat treatment during the formation of the etching resistant protective film.

また、請求項4の発明にかかる半導体装置の製造方法は、請求項1〜3のいずれか一つに記載の発明において、前記エッチング工程は、前記半導体ウエハー全体をエッチング溶液に浸して当該半導体ウエハーの第2主面を所定の深さまでエッチングすることを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the first to third aspects, wherein the etching step is performed by immersing the entire semiconductor wafer in an etching solution. The second main surface is etched to a predetermined depth.

この請求項4の発明によれば、半導体ウエハー全体をエッチング溶液に浸してエッチングをおこなうので、バッチ処理によってエッチング処理を効率的におこなうことができる。   According to the fourth aspect of the invention, since the entire semiconductor wafer is immersed in the etching solution for etching, the etching process can be efficiently performed by batch processing.

また、請求項5の発明にかかる半導体装置の製造方法は、請求項1〜4のいずれか一つに記載の発明において、前記エッチング工程は、アルカリ溶液をエッチング溶液として前記半導体ウエハーの第2主面を所定の深さまでエッチングすることを特徴とする。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the first to fourth aspects, wherein the etching step is performed by using the alkaline solution as an etching solution to etch the second main wafer. The surface is etched to a predetermined depth.

この請求項5の発明によれば、アルカリ溶液による異方性エッチングをおこなうことができる。   According to the invention of claim 5, anisotropic etching with an alkaline solution can be performed.

また、請求項6の発明にかかる半導体装置の製造方法は、請求項1〜5のいずれか一つに記載の発明において、前記第1の除去工程は、前記耐エッチング保護膜を前記半導体ウエハーの第2主面の外周端部から1mm〜20mm幅を残して除去することを特徴とする。   According to a sixth aspect of the present invention, in the semiconductor device manufacturing method according to any one of the first to fifth aspects of the present invention, the first removal step may include the step of removing the etching-resistant protective film on the semiconductor wafer. It is characterized by being removed leaving a width of 1 mm to 20 mm from the outer peripheral end of the second main surface.

この請求項6の発明によれば、半導体ウエハーの機械的強度を保ちつつ、半導体ウエハーの中心部を薄層化することができる。   According to the sixth aspect of the present invention, the central portion of the semiconductor wafer can be thinned while maintaining the mechanical strength of the semiconductor wafer.

また、請求項7の発明にかかる半導体装置の製造方法は、請求項1〜6のいずれか一つに記載の発明において、前記半導体ウエハーの第2主面の外周端部は、当該半導体ウエハーを支持する支持爪と接しており、前記レジスト除去工程は、前記支持爪と前記半導体ウエハーが接する部分から所定幅を残して前記フォトレジストを除去することを特徴とする。   According to a seventh aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the first to sixth aspects, wherein the outer peripheral end portion of the second main surface of the semiconductor wafer is the semiconductor wafer. The resist removing process is characterized in that the photoresist is removed leaving a predetermined width from a portion where the supporting claw and the semiconductor wafer are in contact with each other.

この請求項7の発明によれば、半導体ウエハーの裏面のうち、支持爪と接しているため耐エッチング保護膜が形成されない部分を避けて耐エッチング保護膜を除去することができ、半導体ウエハーの機械的強度を保つことができる。   According to the seventh aspect of the present invention, the etching-resistant protective film can be removed while avoiding the portion where the etching-resistant protective film is not formed on the back surface of the semiconductor wafer because it is in contact with the support claws. Strength can be maintained.

この発明にかかる半導体装置の製造方法によれば、生産コストを抑えつつ、ウエハーの薄層化を含む製造工程における割れや反りを低減することができるという効果を奏する。   According to the semiconductor device manufacturing method of the present invention, it is possible to reduce cracks and warpage in a manufacturing process including wafer thinning while suppressing production costs.

以下に添付図面を参照して、この発明にかかる半導体装置の製造方法の好適な実施の形態を詳細に説明する。   Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

(実施の形態)
図1〜図10は、実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。以下に説明する実施の形態では、直径6インチのウエハーを用いて耐圧600Vのフィールドストップ(FS)型IGBTを作製する場合を例にして説明する。
(Embodiment)
1 to 10 are diagrams illustrating a manufacturing process of the semiconductor device manufacturing method according to the embodiment. In the embodiment described below, a case where a field stop (FS) IGBT having a withstand voltage of 600 V is manufactured using a wafer having a diameter of 6 inches will be described as an example.

まず、従来と同様の工程によってウエハー11のおもて面半導体素子の表面構造部およびアルミ電極12を作製する(図1)。このとき、ウエハー11は薄層化されておらず、その厚さは例えば500μmである。また、ウエハー11の直径は6インチ(150mm)である。つぎに、ウエハー11の裏面に生成された酸化膜などを除去するため、ウエハー11の裏面を機械的に研削し、ウエハー11の厚さを例えば350μmとする(図2)。   First, the surface structure portion of the front surface semiconductor element and the aluminum electrode 12 of the wafer 11 are fabricated by the same process as in the prior art (FIG. 1). At this time, the wafer 11 is not thinned, and its thickness is, for example, 500 μm. The diameter of the wafer 11 is 6 inches (150 mm). Next, in order to remove an oxide film or the like generated on the back surface of the wafer 11, the back surface of the wafer 11 is mechanically ground to set the thickness of the wafer 11 to 350 μm, for example (FIG. 2).

つづいて、例えばTEOS(正珪酸四エチル)を原料としたプラズマCVD(Chemical Vapor Deposition)によって、例えば350℃の温度下でウエハー11の両面に、耐エッチング保護膜として例えば厚さ1μmの酸化膜13を形成する(図3)。このような方法で酸化膜13を形成するのは、ウエハー11の表面にアルミ電極12が形成されているので、500℃以下で処理するのが望ましいからである。また、耐エッチング保護膜としては、その他の酸化膜や窒素膜を採用することができる。この場合も、500℃以下の処理で形成できるものが望ましい。   Subsequently, for example, a plasma CVD (Chemical Vapor Deposition) using TEOS (tetraethyl tetrasilicate) as a raw material is performed on both surfaces of the wafer 11 at a temperature of 350 ° C., for example, as an anti-etching protective film having a thickness of 1 μm, for example. (FIG. 3). The reason why the oxide film 13 is formed by such a method is that, since the aluminum electrode 12 is formed on the surface of the wafer 11, it is desirable to perform the treatment at 500 ° C. or less. In addition, as the anti-etching protective film, other oxide films or nitrogen films can be employed. Also in this case, what can be formed by processing at 500 ° C. or lower is desirable.

そして、例えばスピンコータでウエハー11の両面にポジ型フォトレジスト14を塗布した後、ベークする(図4)。つづいて、ウエハー11の裏面の外周端部を例えば5mmの幅で遮光するマスク(図示省略)を用いて、ウエハー11の裏面を露光する。または、ポジ型フォトレジスト14を用いる代わりに、ネガ型フォトレジストをウエハー11の両面に塗布して、ウエハー11のおもて面全体と裏面の外周端部に例えば5mmの幅で光があたるようなマスクを用いて、ウエハー11の両面を露光してもよい。そして、レジスト14を現像して、ウエハー11裏面の中央部のレジスト14を除去する(図5)。   Then, for example, a positive photoresist 14 is applied on both surfaces of the wafer 11 by a spin coater and then baked (FIG. 4). Subsequently, the back surface of the wafer 11 is exposed using a mask (not shown) that shields the outer peripheral edge of the back surface of the wafer 11 with a width of, for example, 5 mm. Alternatively, instead of using the positive photoresist 14, a negative photoresist is applied to both surfaces of the wafer 11 so that the entire front surface of the wafer 11 and the outer peripheral edge of the back surface are exposed to light with a width of, for example, 5 mm. A simple mask may be used to expose both sides of the wafer 11. Then, the resist 14 is developed to remove the resist 14 at the center of the back surface of the wafer 11 (FIG. 5).

図6に、ウエハー11の裏面のレジストパターンを示す。なお、図6では、ウエハー11の裏面が上側になっている。ウエハー11の裏面では、その外周端部を例えば5mmの幅で残してレジスト14が除去され、中央部に酸化膜13が表出している。ここで、ウエハー11の裏面外周端部には、半導体製造装置のウエハー支持爪20が接している。このウエハー支持爪20と接している部分には、酸化膜13が形成されない。そのため、後の工程で強度が不足してウエハー11に割れや反りが生じてしまうおそれがある。   FIG. 6 shows a resist pattern on the back surface of the wafer 11. In FIG. 6, the back surface of the wafer 11 is on the upper side. On the back surface of the wafer 11, the resist 14 is removed leaving the outer peripheral edge of a width of, for example, 5 mm, and the oxide film 13 is exposed at the center. Here, the wafer support claw 20 of the semiconductor manufacturing apparatus is in contact with the outer peripheral edge of the back surface of the wafer 11. The oxide film 13 is not formed on the portion in contact with the wafer support claw 20. For this reason, there is a risk that the wafer 11 will be cracked or warped due to insufficient strength in a later process.

そこで、本実施の形態では、ウエハー11の外周端部のうちウエハー支持爪20と接している部分については、ウエハー支持爪20の形状に合わせてレジストパターンが変更されている。具体的には、ウエハー支持爪20とウエハー11とが接している部分を逃げたレジストパターンとなっている。これにより、後述する工程においてウエハー11裏面の中央部の酸化膜13を除去した後にも、ウエハー11の外周端部に沿って途切れることなく酸化膜13が残るので、ウエハー11の強度低下を防止することができる。なお、ウエハー支持爪20の影響を考慮しなくても充分な強度を確保できる場合には、ウエハー支持爪20とウエハー11とが接している部分を逃げたレジストパターンとしなくてもよい。   Therefore, in the present embodiment, the resist pattern of the outer peripheral end portion of the wafer 11 that is in contact with the wafer support claw 20 is changed according to the shape of the wafer support claw 20. Specifically, the resist pattern is formed by escaping a portion where the wafer support claw 20 and the wafer 11 are in contact with each other. As a result, the oxide film 13 remains without being interrupted along the outer peripheral edge of the wafer 11 even after the oxide film 13 at the center of the back surface of the wafer 11 is removed in a process described later, thereby preventing a reduction in the strength of the wafer 11. be able to. If sufficient strength can be secured without considering the influence of the wafer support claw 20, the resist pattern where the wafer support claw 20 and the wafer 11 are in contact with each other need not be formed.

つづいて、1:10に希釈したHF(ふっ化水素)溶液によって、ウエハー11の裏面中央部の酸化膜13を除去する(図7)。つぎに、レジスト剥離溶液によって、ウエハー11の両面のレジスト14を剥離する(図8)。   Subsequently, the oxide film 13 at the center of the back surface of the wafer 11 is removed with an HF (hydrogen fluoride) solution diluted 1:10 (FIG. 7). Next, the resist 14 on both surfaces of the wafer 11 is stripped with a resist stripping solution (FIG. 8).

そして、ウエハー11のおもて面と裏面の外周端部に残った酸化膜13をマスクとして、例えばディップ方式によってエッチングをおこない、ウエハー11の裏面中央部の厚さを減じる。具体的には、例えば温度80℃のTMAH(水酸化テトラメチルアンモニウム)溶液にウエハー11を約6時間浸して異方性エッチングをおこない、ウエハー11の裏面中央部の厚さを例えば60μmにする(図9)。TMAH溶液のようなアルカリ溶液によるエッチングでは、酸化膜とシリコンとの選択比が500以上である。したがって、酸化膜13の厚さが1μmであれば、500μmまでのシリコンエッチングに耐えることができる。   Then, using the oxide film 13 remaining on the outer peripheral edge portions of the front surface and the back surface of the wafer 11 as a mask, etching is performed, for example, by a dip method to reduce the thickness of the back surface center portion of the wafer 11. Specifically, for example, the wafer 11 is immersed in a TMAH (tetramethylammonium hydroxide) solution at a temperature of 80 ° C. for about 6 hours to perform anisotropic etching, so that the thickness of the center of the back surface of the wafer 11 is, for example, 60 μm ( FIG. 9). In etching with an alkaline solution such as a TMAH solution, the selectivity between the oxide film and silicon is 500 or more. Therefore, if the thickness of the oxide film 13 is 1 μm, it can withstand silicon etching up to 500 μm.

つづいて、ウエハー11を水洗し、1:10に希釈したHF溶液によって、ウエハー11の両面の酸化膜13を完全に除去する(図10)。ウエハー11の中央部の厚さは例えば60μmであるものの、ウエハー11の外周端部には例えば厚さ350μmのシリコンが例えば5mm幅で残っている。したがって、ウエハー11全体としての機械的強度を充分に確保することができる。また、ウエハー11の反りを500μm以下に抑えることができる。   Subsequently, the wafer 11 is washed with water, and the oxide film 13 on both surfaces of the wafer 11 is completely removed with an HF solution diluted 1:10 (FIG. 10). Although the thickness of the central portion of the wafer 11 is, for example, 60 μm, silicon having a thickness of, for example, 350 μm remains at a width of, for example, 5 mm at the outer peripheral end portion of the wafer 11. Therefore, the mechanical strength of the entire wafer 11 can be sufficiently ensured. Further, the warpage of the wafer 11 can be suppressed to 500 μm or less.

また、TMAH溶液によるエッチング中にウエハー11に反りが生じないので、エッチング保護膜である酸化膜13が割れてウエハー11のおもて面側にエッチング液が滲み込んでしまうことがなく、ウエハー11のおもて面をエッチング液から保護することができる。   Further, since the wafer 11 is not warped during the etching with the TMAH solution, the oxide film 13 which is an etching protective film is not broken and the etching solution does not penetrate into the front surface side of the wafer 11, and the wafer 11. The front surface can be protected from the etching solution.

以上説明したように、実施の形態にかかる半導体装置の製造方法によれば、専用の装置を用いることなくウエハーの外周端部の厚さを残しつつウエハーを薄層化して、半導体装置を製造することができる。これにより、支持基板方式やTAIKOプロセスのように専用の装置を用いた場合と比較して低コストでウエハーの割れや反りを低減して、半導体装置を生産することができる。   As described above, according to the method for manufacturing a semiconductor device according to the embodiment, the semiconductor device is manufactured by thinning the wafer while leaving the thickness of the outer peripheral edge of the wafer without using a dedicated device. be able to. As a result, it is possible to produce a semiconductor device by reducing wafer cracking and warping at a lower cost than when a dedicated device is used, such as a support substrate method or a TAIKO process.

また、半導体ウエハーの裏面をエッチングすることによってウエハーを薄層化するので、ウエハーのおもて面に素子構造による段差があっても圧力がかからない。したがって、薄層化の際にウエハーが割れてしまうことがない。また、ディップ方式によってエッチングをおこない、ウエハーを薄層化するので、枚葉式と比べて生産効率を向上させることができる。   Further, since the wafer is thinned by etching the back surface of the semiconductor wafer, no pressure is applied even if there is a step due to the element structure on the front surface of the wafer. Therefore, the wafer is not broken during the thinning. Moreover, since the wafer is thinned by etching by the dip method, the production efficiency can be improved as compared with the single wafer method.

また、製造工程において500℃程度までの熱処理をおこなうことができるので、薄層化工程以外の処理の内容が制限されることなく、半導体装置の製造工程を設計することができる。   Further, since the heat treatment up to about 500 ° C. can be performed in the manufacturing process, the manufacturing process of the semiconductor device can be designed without restricting the contents of the processes other than the thinning process.

以上のように、本発明にかかる半導体装置の製造方法は、デバイス厚の薄い半導体装置を製造するのに有用であり、特に、汎用インバータ、ACサーボ、無停電電源(UPS)またはスイッチング電源などの産業分野や、電子レンジ、炊飯器またはストロボなどの民生機器分野に用いられるIGBTなどの電力用半導体装置の製造に適している。   As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device with a thin device thickness. In particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for manufacturing power semiconductor devices such as IGBTs used in industrial fields and consumer equipment fields such as microwave ovens, rice cookers or strobes.

実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造方法の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment.

符号の説明Explanation of symbols

11 ウエハー
12 アルミ電極
13 酸化膜
14 レジスト
20 ウエハー支持爪
11 Wafer 12 Aluminum electrode 13 Oxide film 14 Resist 20 Wafer support nail

Claims (7)

半導体ウエハーの第1主面および第2主面に耐エッチング保護膜となる酸化膜または窒化膜を形成する形成工程と、
前記耐エッチング保護膜をフォトレジストで被覆する被覆工程と、
フォトリソグラフィによって前記フォトレジストのうち、前記半導体ウエハーの第2主面側のフォトレジストを外周端部から所定の幅を残して除去するレジスト除去工程と、
前記半導体ウエハーの第2主面側の外周端部に残る前記フォトレジストをマスクとして、前記耐エッチング保護膜のうち、前記半導体ウエハーの第2主面に形成された耐エッチング保護膜を外周端部から所定の幅を残して除去する第1の除去工程と、
前記耐エッチング保護膜が外周端部を残して除去された前記半導体ウエハーの第2主面を所定の深さまでエッチングするエッチング工程と、
エッチング後の前記半導体ウエハーの第1主面と第2主面の外周端部に残る前記耐エッチング保護膜を除去する第2の除去工程と、
を含んだことを特徴とする半導体装置の製造方法。
Forming an oxide film or a nitride film serving as an etching-resistant protective film on the first main surface and the second main surface of the semiconductor wafer;
A coating step of coating the etching-resistant protective film with a photoresist;
A resist removing step of removing the photoresist on the second main surface side of the semiconductor wafer from the outer peripheral end portion by leaving a predetermined width out of the photoresist by photolithography;
Using the photoresist remaining on the outer peripheral edge of the second main surface side of the semiconductor wafer as a mask, the etching resistant protective film formed on the second main surface of the semiconductor wafer is the outer edge of the etching resistant protective film. A first removing step for removing a predetermined width from the first,
An etching step of etching the second main surface of the semiconductor wafer from which the etching-resistant protective film has been removed leaving an outer peripheral edge to a predetermined depth;
A second removal step of removing the etching-resistant protective film remaining on the outer peripheral ends of the first main surface and the second main surface of the semiconductor wafer after etching;
A method for manufacturing a semiconductor device, comprising:
あらかじめ前記半導体ウエハーの第1主面に半導体素子またはその一部が作製されていることを特徴とする請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein a semiconductor element or a part thereof is formed in advance on the first main surface of the semiconductor wafer. 前記耐エッチング保護膜は、500℃以下の熱処理によって形成されることを特徴とする請求項2に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 2, wherein the etching-resistant protective film is formed by a heat treatment at 500 ° C. or less. 前記エッチング工程は、前記半導体ウエハー全体をエッチング溶液に浸して当該半導体ウエハーの第2主面を所定の深さまでエッチングすることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。   4. The semiconductor device according to claim 1, wherein the etching step includes immersing the entire semiconductor wafer in an etching solution to etch the second main surface of the semiconductor wafer to a predetermined depth. 5. Manufacturing method. 前記エッチング工程は、アルカリ溶液をエッチング溶液として前記半導体ウエハーの第2主面を所定の深さまでエッチングすることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein in the etching step, the second main surface of the semiconductor wafer is etched to a predetermined depth using an alkaline solution as an etching solution. 前記第1の除去工程は、前記耐エッチング保護膜を前記半導体ウエハーの第2主面の外周端部から1mm〜20mm幅を残して除去することを特徴とする請求項1〜5のいずれか一つに記載の半導体装置の製造方法。   The said 1st removal process removes the said etching-resistant protective film, leaving 1 mm-20 mm width from the outer peripheral edge part of the 2nd main surface of the said semiconductor wafer. The manufacturing method of the semiconductor device as described in one. 前記半導体ウエハーの第2主面の外周端部は、当該半導体ウエハーを支持する支持爪と接しており、
前記レジスト除去工程は、前記支持爪と前記半導体ウエハーが接する部分から所定幅を残して前記フォトレジストを除去することを特徴とする請求項1〜6のいずれか一つに記載の半導体装置の製造方法。


The outer peripheral end of the second main surface of the semiconductor wafer is in contact with a support claw that supports the semiconductor wafer,
The semiconductor device manufacturing method according to claim 1, wherein the resist removing step removes the photoresist leaving a predetermined width from a portion where the support claw and the semiconductor wafer are in contact with each other. Method.


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