CN101276766B - Crystal coated sealing method - Google Patents
Crystal coated sealing method Download PDFInfo
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- CN101276766B CN101276766B CN2008100996055A CN200810099605A CN101276766B CN 101276766 B CN101276766 B CN 101276766B CN 2008100996055 A CN2008100996055 A CN 2008100996055A CN 200810099605 A CN200810099605 A CN 200810099605A CN 101276766 B CN101276766 B CN 101276766B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention discloses a flip chip package method, comprising the steps of providing a substrate which has a cutting channel; forming on the substrate an insulating layer with a groove located on the cutting channel; disposing a chip on the substrate, the disposal position of the chip is located at one side of the groove and adjacent to the groove, the chip is electrically connected with the substrate in a manner of flip chip joint; and forming a bottom glue between the chip and the substrate starting with one side of the chip adjacent to the cutting channel.
Description
[technical field]
The invention relates to a kind of crystal coated encapsulation method, and particularly relevant for a kind of crystal coated encapsulation method that improves the substrate utilization rate.
[background technology]
In the generation that science and technology is maked rapid progress, the electronic product that utilizes integrated circuit package to form has become instrument indispensable in modern's daily life.Along with the march toward trend of compact design of electronic product, semiconductor packaging is also relatively developed the form of many highdensity semiconductor packages, for example flip chip.
Need to form primer in the flip chip assembly process between chip and substrate.When yet very thin or area is big when chip, be easy to take place the glue problem of overflowing.And the glue that overflows can pollute the weld pad of adjacent chips, and the weld pad that causes adjacent chips is when routing operation subsequently, and gold thread is difficult for being fixed on the contaminated weld pad.And recently the customer requirement chip size dwindles day by day, makes that the distance between the weld pad of chip and adjacent chips and then cooperates shortening, so causes the easier weld pad that pollutes adjacent chips of primer that overflows.
[summary of the invention]
In view of this, the present invention is providing a kind of crystal coated encapsulation method exactly, in begin to form primer locate and the weld pad of adjacent chips between form a groove, when the excessive glue of primer takes place, overflow glue in can first filling groove the space and can not flow to the weld pad of adjacent chips, therefore reduced the chance of polluting the weld pad of adjacent chips, and improved the success rate of adjacent chips, to improve product percent of pass and to reduce cost in the routing operation.And, because the formation of groove, also make the distance of chip chamber to further and do not have the problem that weld pad suffers the excessive glue pollution of primer, so the same substrate area can hold more chip, make the substrate utilization rate promote.
According to an aspect of the present invention, propose a kind of crystal coated encapsulation method, comprise a substrate is provided, substrate has a Cutting Road; Form an insulating barrier on substrate, insulating barrier has a groove, and groove is positioned on the Cutting Road; One chip is arranged on the substrate, and the position that is provided with of chip is positioned at a side of groove and is adjacent to groove, and chip is electrically connected at substrate in the mode of chip bonding; And, begin to form a primer between chip and substrate from a side of the chip of contiguous Cutting Road.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
[description of drawings]
Fig. 1 illustrates the flow chart according to the crystal coated encapsulation method of preferred embodiment of the present invention.
Fig. 2 A illustrates the vertical view of the substrate of present embodiment.
Fig. 2 B illustrates the front view of substrate among Fig. 2 A.
Fig. 3 A illustrates the vertical view of the substrate that is formed with insulating barrier and weld pad of present embodiment.
Fig. 3 B illustrates among Fig. 3 A substrate along the cutaway view of 1A-1A '.
Fig. 4 A illustrates the vertical view of the substrate that is provided with chip of present embodiment.
Fig. 4 B illustrates among Fig. 4 A substrate along the cutaway view of 1B-1B '.
The vertical view of the substrate when Fig. 5 illustrates the formation primer of present embodiment.
Fig. 6 A illustrates when not forming groove, the schematic diagram that the glue that overflows distributes.
Fig. 6 B illustrates the excessive glue distribution schematic diagram of the reeded crystal coated encapsulation method of formation of present embodiment.
Fig. 7 A illustrates the vertical view of the substrate that is formed with many gold threads of present embodiment.
Fig. 7 B illustrates among Fig. 7 A substrate along the cutaway view of person 1C-1C '.
Fig. 8 illustrates the schematic diagram of the flip chip of present embodiment.
Fig. 9 illustrates the schematic diagram of another structure of the groove of present embodiment.
[embodiment]
The present invention proposes a kind of crystal coated encapsulation method, and comprising provides a substrate, and substrate has a Cutting Road; Form an insulating barrier on substrate, insulating barrier has a groove, and groove is positioned on the Cutting Road; One chip is arranged on the substrate, and the position that is provided with of chip is positioned at a side of groove and is adjacent to groove, and chip is electrically connected at substrate in the mode of chip bonding; And, begin to form a primer between chip and substrate from a side of the chip of contiguous Cutting Road.When the excessive glue of primer takes place, the glue that overflows can first filling groove in space and can not flow to the weld pad of adjacent chips, therefore reduced the chance of polluting the weld pad of adjacent chips.Below enumerate a preferred embodiment and elaborate, so this embodiment only is one of several execution modes under the invention spirit of the present invention, and the literal of its explanation and icon can't carry out limit to desire protection range of the present invention.
Please refer to Fig. 1, it illustrates the flow chart according to the crystal coated encapsulation method of preferred embodiment of the present invention.Crystal coated encapsulation method may further comprise the steps.At first, please be simultaneously with reference to Fig. 2 A and Fig. 2 B, Fig. 2 A illustrates the vertical view of the substrate of present embodiment, and Fig. 2 B illustrates the front view of substrate among Fig. 2 A.In step 102, a substrate 202 is provided, substrate 202 has a Cutting Road 204.
Then, please be simultaneously with reference to Fig. 3 A and Fig. 3 B, Fig. 3 A illustrates the vertical view of the substrate that is formed with insulating barrier and weld pad of present embodiment, and Fig. 3 B illustrates among Fig. 3 A substrate along the cutaway view of 1A-1A '.In step 104, form an insulating barrier 206 on substrate 202, insulating barrier 206 has a groove 208, and groove 208 is positioned on the Cutting Road 204.Wherein, insulating barrier 206 comprises green lacquer, separator, ABF dielectric layer (Ajinomoto Build-up film) or other dielectric material.The width of groove 208 can be less than or equal to the width of Cutting Road 204, and the length of groove 208 can be less than or equal to the length of Cutting Road 204, and present embodiment is that example explains less than the width and the length of Cutting Road 204 respectively with the width and the length of groove 208.In addition, in this step, crystal coated encapsulation method more comprises and forms a plurality of weld pads 214 on substrate 202, and groove 208 for example forms with an exposure imaging technology, and groove 208 can correspond in forming insulating barrier 206 in the processing procedure of opening 213 of weld pad 214 and finish in the lump.Therefore, the formation of groove is quite simple, and can additionally not increase the processing procedure cost.
In addition, groove 208 formed dented space have absorbed the thermal expansion amount that substrate 202 is produced because of the heating action in successive process, make the amount of warpage (Warpage) of substrate 202 integral body reduce, and have therefore promoted the processing procedure qualification rate of flip chip.
Then, please be simultaneously with reference to Fig. 4 A and Fig. 4 B, Fig. 4 A illustrates the vertical view of the substrate that is provided with chip of present embodiment, and Fig. 4 B illustrates among Fig. 4 A substrate along the cutaway view of 1B-1B '.In step 106, a chip 210 is arranged on the substrate 202, the position that is provided with of chip 210 is positioned at a side of groove 208 and is adjacent to groove 208, and chip 210 is electrically connected at substrate 202 in the mode of chip bonding.In addition, chip 210 has more a plurality of tin balls 211, and chip 210 electrically connects by tin ball 211 and substrate 202.In addition, in this step, also can form another chip 212 on substrate 202, chip 210 and chip 212 lay respectively at the both sides of Cutting Road 204.Chip 212 can directly be arranged on the substrate 202 or storehouse on the crystal covering type chip, present embodiment is that example explains with storehouse in the form of crystal covering type chip 215.The weld pad 214 that has on the substrate 202 is in order to electrically connect with chip 212, and the mode of electric connection can adopt the routing technology to finish, and in order to make the moderate length of gold thread, weld pad 214 is formed between Cutting Road 204 and the chip 212.
Then, please be simultaneously with reference to Fig. 5 the vertical view of the substrate when it illustrates the formation primer of present embodiment.In step 108, begin to form primer 216 between chip 210 and substrate 202 from a side 219 of the chip 210 of contiguous Cutting Road 204, when primer 216 begins to be placed on a side 219 that is adjacent to chip 210, by siphon principle, primer 216 can slowly be inhaled between chip 210 and the substrate 202.Wherein, the mode that forms primer 216 can adopt injection (Jetting) mode or some glue mode (Dispensing or No-Flow).
Under the situation that does not form groove, in the middle of the process that forms primer, if there is excessive glue to produce, the glue that then overflows may pollute weld pad.Please refer to Fig. 6 A, it illustrates when not forming groove, the schematic diagram that the glue that overflows distributes.When insulating barrier 206 was not had groove, one of primer overflow glue 221 because there is not groove to be received, and flow to adjacent chips so can only take advantage of a situation, and for example is chip 212, weld pad 214 on, and weld pad 214 is polluted.Therefore cause in follow-up routing operation, gold thread can't firmly be attached on the weld pad 214.In this case, then must add between large chip 210 and the weld pad 214 apart from reducing the probability that weld pad 214 is polluted.So, will waste the spendable space of substrate 202.
In the middle of the process that forms primer, if there is excessive glue to produce, present embodiment can make the glue that overflows avoid polluteing the weld pad of adjacent chips effectively.Please refer to Fig. 6 B, it illustrates the excessive glue distribution schematic diagram of the reeded crystal coated encapsulation method of formation of present embodiment.One excessive glue 218 of primer 216 can flow to earlier in the space of groove 208, and has avoided excessive glue 218 to flow to weld pad 214 and pollution weld pad 214, and so, distance need not strengthen between crystal grain 210 and the weld pad 214, so and the spendable space of saving substrate 202.
In addition, in order to electrically connect chip 212 and weld pad 214, after step 108, crystal coated encapsulation method more can comprise the step that forms many gold threads 217.Please refer to Fig. 7 A and Fig. 7 B, Fig. 7 A illustrates the vertical view of the substrate that is formed with many gold threads of present embodiment, and Fig. 7 B illustrates among Fig. 7 A substrate along the cutaway view of person 1C-1C '.By the routing operation, form many gold threads 217 and connect chip 212 and weld pad 214, so that chip 212 electrically connects via gold thread 217 and weld pad 214.
In addition, after step 108, crystal coated encapsulation method more can comprise along Cutting Road 204 cutting substrates 202, to form the step of flip chip 220.Please refer to Fig. 8, it illustrates the schematic diagram of the flip chip of present embodiment.After using cutter 222 cutting substrates 202, form flip chip 220 and 224, wherein,, before cutting, cover chip 212 and gold threads 217 with sealing 226 in order to protect gold thread 217 to avoid making moist and the foreign object erosion.
In addition, in cutting process,, after having cut, be easy at edge formation burr because the quality of insulating barrier 206 is softer.Yet, because the formation of groove, make that the insulating barrier composition that Cutting Road had with groove is also few compared to the insulating barrier composition that Cutting Road had that does not have groove, when the composition of insulating barrier more after a little while, the flip chip after the cutting residual burr also become less naturally.So, help the lifting of flip chip quality of finished.
In the routing operation, can be firmly on weld pad 214 in order to make gold thread, it is clean that weld pad must keep, and impurity can not be arranged on weld pad, otherwise gold thread can't be stabilized on the weld pad.If it is too serious that weld pad pollutes, and for example is the excessive solation (as shown in Figure 6A) to weld pad 214 of primer 216, in addition can take place can't routing bad problem.So formation of the groove 208 of present embodiment, make when the excessive glue 218 of primer 216 takes place, overflow glue 218 meetings first filling groove 208 interior spaces and can not flow on the weld pad 214, therefore reduced the chance of polluting weld pad 214, make the gold thread 217 in the follow-up routing operation, can stably be fixed on the weld pad 214.In addition, because the formation of groove makes that the regional extent of excessive glue also can be controlled less, the distance of chip chamber is furthered, and improves the utilization rate of substrate so that substrate holds more chip.
Please refer to Fig. 9, it illustrates the schematic diagram of another structure of the groove of present embodiment.Insulating barrier 302 has a plurality of grooves 304, and groove 304 is positioned on the Cutting Road 306.The formed groove of crystal coated encapsulation method of the present invention does not limit to the groove form of Fig. 1, the distribution of groove can along with flip chip on substrate distribution mode and cooperate change.Therefore, the configuration mode of multiple groove has increased the planning elasticity of processing procedure.
In addition, the size of groove can cooperate the adjustment of primer amount, and for example, the primer amount needs more for a long time because of cooperating product size, and the size of groove then can cooperate the bigger groove of formation volume to hold the more glue amount of overflowing.So, make that the regional extent of excessive glue still can be controlled less.
The disclosed crystal coated encapsulation method of the above embodiment of the present invention has multiple advantages, below only enumerates the part advantage and is described as follows:
1) formation of groove makes the weld pad of adjacent chips be subjected to the probability reduction that primer pollutes, and has improved the success rate of follow-up routing operation and has guaranteed the routing quality.
2) formation of groove, the regional extent of the glue that make to overflow can be dwindled, so the distance of chip chamber shortened, and makes identical substrate area can hold the less crystal grain of more sizes.Therefore improved the utilization rate of substrate.
3) formation of groove makes the softer insulating barrier quantity of quality reduce, after substrate cut becomes flip chip, the cut edge of flip chip residual burr also reduced, therefore promoted the quality of finished of flip chip.
4) formation of groove makes the substrate warp amount reduce, and has therefore promoted the processing procedure qualification rate of flip chip.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (11)
1. crystal coated encapsulation method comprises:
(a) provide a substrate, have a Cutting Road;
(b) form an insulating barrier on this substrate, this insulating barrier has a groove, and this groove is positioned on this Cutting Road;
(c) chip is arranged on this substrate, the position that is provided with of this chip is positioned at a side of this groove and is adjacent to this groove, and this chip is electrically connected at this substrate in the mode of chip bonding; And
(d) side from this chip of contiguous this Cutting Road begins to form a primer between this chip and this substrate; When glue took place to overflow, this excessive solation was gone into described groove and can not flow to the weld pad that is close to this chip.
2. crystal coated encapsulation method comprises:
(a) provide a substrate, have a Cutting Road;
(b) form an insulating barrier on this substrate, this insulating barrier has a plurality of grooves, and described groove is positioned on this Cutting Road;
(c) chip is arranged on this substrate, the position that is provided with of this chip is positioned at a side of described groove and is adjacent to described groove, and this chip is electrically connected at this substrate in the mode of chip bonding; And
(d) side from this chip of contiguous this Cutting Road begins to form a primer between this chip and this substrate; When glue took place to overflow, this excessive solation was gone into described groove and can not flow to the weld pad that closes on this chip.
3. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, the width of this groove is less than or equal to the width of this Cutting Road.
4. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, the length of this groove is less than or equal to the length of this Cutting Road.
5. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, in this step (c), this chip has a plurality of tin balls, and this chip electrically connects by described tin ball and this substrate.
6. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, in this step (b), this groove forms with an exposure imaging technology.
7. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, in this step (d), forms this primer with spray regime.
8. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, in this step (d), forms this primer in a glue mode.
9. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, in this step (d) afterwards, this method more comprises:
Cut this substrate along this Cutting Road, to form a flip chip.
10. crystal coated encapsulation method according to claim 1 and 2 is characterized in that, more comprises:
Form another chip on this substrate, this chip and this another chip lay respectively at the both sides of this Cutting Road.
11. crystal coated encapsulation method according to claim 10 is characterized in that, has more a plurality of weld pads on this substrate, described a plurality of pad-shaped are formed between this Cutting Road and this another chip, and this method more comprises:
Form many gold threads, so that this another chip electrically connects via described gold thread and described a plurality of weld pad respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100996055A CN101276766B (en) | 2008-05-16 | 2008-05-16 | Crystal coated sealing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100996055A CN101276766B (en) | 2008-05-16 | 2008-05-16 | Crystal coated sealing method |
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| CN101276766A CN101276766A (en) | 2008-10-01 |
| CN101276766B true CN101276766B (en) | 2010-09-08 |
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| CN105225974A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| CN105225973A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| CN105390429A (en) * | 2015-11-05 | 2016-03-09 | 南通富士通微电子股份有限公司 | Packaging method |
| KR102595896B1 (en) * | 2016-08-08 | 2023-10-30 | 삼성전자 주식회사 | Printed Circuit Board, and semiconductor package having the same |
| TWI707408B (en) * | 2019-04-10 | 2020-10-11 | 力成科技股份有限公司 | Integrated antenna package structure and manufacturing method thereof |
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