CN105390429A - Packaging method - Google Patents
Packaging method Download PDFInfo
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- CN105390429A CN105390429A CN201510747322.7A CN201510747322A CN105390429A CN 105390429 A CN105390429 A CN 105390429A CN 201510747322 A CN201510747322 A CN 201510747322A CN 105390429 A CN105390429 A CN 105390429A
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- chip
- support plate
- plastic packaging
- packaging layer
- packing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention relates to a packaging method. The method comprise: a support plate is provided, wherein the support plate contains a plurality of chip zones and cutting zones arranged between the adjacent chip zones and has a first surface; a plurality of grooves are formed in the cutting zones of the first surface of the support plate; a chip is provided, wherein the chip contains a functional plane and a non-functional plane opposite to the functional plane; the non-functional plane of the chip and the first surface of the chip zone of the support plate are fixed; after fixation of the non-functional plane of the chip with the first surface of the chip zone of the support plate, salient points are formed on the surface of the functional plane of the chip; a plastic packaging layer is formed on the first surface of the support plate and the surface of the chip and the top surfaces of the salient points are exposed by the plastic packaging layer; after forming of the plastic packaging layer, the support plate is removed; a re-wiring structure is formed on the surface of the plastic packaging layer and the top surfaces of the salient points; and the plastic packaging layer and the re-wiring structure are cut and thus a plurality of chips are discrete mutually, thereby forming an independent packaging structure. With the method, the formed packaging product has a high yield and high reliability.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method for packing.
Background technology
Wafer-level packaging (WaferLevelPackaging, be called for short WLP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, the chip size after encapsulation and nude film completely the same.Compared with ceramic leadless chip carrier (CeramicLeadlessChipCarrier) or organic leadless chip carrier (OrganicLeadlessChipCarrier) isotype, the advantages such as Wafer level packaging has gentlier, less, shorter, thinner and more cheap.Chip size after Wafer level packaging encapsulation can reach highly microminiaturized, then the manufacturing cost of chip significantly reduces along with the reduction of chip size and the increase of wafer size.Wafer level packaging be IC can be designed, technology that wafer manufacture, packaging and testing, Substrate manufacture integrate, be the focus in current encapsulation field and the trend of future development.
Fan-out wafer encapsulation is the one of wafer-level packaging.Fan-out wafer method for packing comprises following processing step: form stripping film at carrier surface, and forms first medium layer on stripping film surface, and first medium layer is formed the first graph layer, and described first graph layer has the first opening; In the first opening, form the first metal electrode being used for being connected with edge of substrate, form interconnection metal layer again on the first graph layer surface; Form second dielectric layer on the first surface of metal electrode, again interconnection metal layer surface and first medium layer surface, and form second graph layer on second dielectric layer surface, described second graph layer has the second opening; The second metal electrode being used for being connected with die terminals is formed in the second opening; After flip-chip to the second metal electrode, form plastic packaging layer in second dielectric layer and chip surface, described plastic packaging layer surrounds described chip, forms encapsulating structure; Carrier is separated with encapsulating structure with stripping film; Plant ball backflow, form soldered ball; Monolithic cuts, and forms fan-out chip packaging structure.
But the reliability of existing Wafer level packaging is poor, the encapsulating structure yield formed with existing Wafer level packaging is lower.
Summary of the invention
The problem that the present invention solves is to provide a kind of method for packing, improves yield and the reliability of encapsulating products.
For solving the problem, the invention provides a kind of method for packing, comprising:
There is provided support plate, described support plate comprises some chip region and the cutting area between adjacent core section, and described support plate comprises first surface;
Some grooves are formed in the cutting area of described support plate first surface;
There is provided chip, described chip comprises relative functional surfaces and non-functional;
Non-functional of described chip is fixed with the first surface in carrier chip district;
After fixing with the first surface in carrier chip district by non-functional of chip, form salient point on the functional surfaces surface of described chip;
Form plastic packaging layer at described support plate first surface and chip surface, described plastic packaging layer exposes the top surface of described salient point;
After the described plastic packaging layer of formation, remove described support plate;
Wire structures is again formed at the top surface of described plastic packaging layer surface and salient point;
To described plastic packaging layer and again wire structures cut, make some chips mutually discrete, form independently encapsulating structure.
Optionally, the formation process of described salient point comprises lead key closing process.
Optionally, the material of described salient point is gold, silver, copper, billon, silver alloy or copper alloy.
Optionally, described salient point comprises some stacking sub-salient points; After often once go between key and technique form sub-salient point, formed sub-salient point is flattened.
Optionally, the functional surfaces surface of described chip exposes weld pad; Described weld pad surface lower than or the functional surfaces that flushes in described chip; Described salient point is positioned at described weld pad surface.
Optionally, the step that non-functional of described chip is fixed with the first surface in carrier chip district is comprised: paste the first tack coat for non-functional at described chip; Described first tack coat is mutually bonding with the first surface in carrier chip district, with the first surface in non-functional of fixed chip and carrier chip district.
Optionally, the step that non-functional of described chip is fixed with the first surface in carrier chip district is comprised: be coated with the second tack coat at the first surface of described support plate; The non-functional face of chip is adhered to described second tie layer surface, and makes described chip be positioned at carrier chip district.
Optionally, the technique forming some grooves in the cutting area of described support plate first surface is laser cutting parameter.
Optionally, the step forming some grooves in the cutting area of described support plate first surface comprises: form mask layer at the first surface of described support plate, described mask layer exposes the cutting area of support plate; With described mask layer for mask, etch described support plate, form groove at the first surface of described support plate.
Optionally, described etching technics is dry etch process or wet-etching technology.
Optionally, the shape of cross section of described texturearunaperpendicular in support plate first surface direction is V-type or U-shaped; When the shape of cross section of described groove is V-type, the bottom size of described groove is less than top dimension, and described bottom portion of groove has drift angle; When the shape of cross section of described groove is U-shaped, the sidewalls orthogonal of described groove is in the first surface of support plate.
Optionally, the forming step of described plastic packaging layer comprises: adopt plastic package process to form initial plastic packaging layer at described support plate first surface and chip surface, described initial plastic packaging layer covers functional surfaces and the salient point of described chip; Initial plastic packaging layer described in planarization, till exposing described salient point top, forms described plastic packaging layer.
Optionally, also comprise: after the described support plate of removal, described in formation again before wire structures, described plastic packaging layer surface and chip surface are cleaned.
Optionally, described plastic packaging layer is also positioned at described groove; After the described support plate of removal, the part plastic packaging layer being positioned at described groove forms projection; Again before wire structures, also comprise and remove described projection described in formation.
Optionally, also comprise: described in formation again before wire structures, form the first insulating barrier on described plastic packaging layer surface, there is in described first insulating barrier the first through hole exposing described chip surface salient point; In described first through hole and part first surface of insulating layer formed described in wire structures again.
Optionally, also comprise: described in formation again after wire structures, to described support plate, plastic packaging layer with before wire structures cuts again, form soldered ball on the described surface of wire structures again.
Optionally, also comprise: before the described soldered ball of formation, form the second insulating barrier on the described surface of wire structures again, there is in described second insulating barrier the second through hole exposing partly again wire structures; Described soldered ball is formed in described second through hole.
Compared with prior art, technical scheme of the present invention has the following advantages:
In method for packing of the present invention, before the first surface in carrier chip district is fixed in the non-functional face of chip, some grooves are formed in the cutting area of support plate, described groove can be passed through, make between the plastic packaging layer of follow-up formation and described support plate, the stress produced because of thermal expansion coefficient difference is released, and eliminates with this die drift problem and plastic packaging layer warped problem that are caused by stress.Described groove type is formed in cutting area, and described cutting area is between adjacent core section, and described chip region is used for fixed chip, then in the support plate of described groove between adjacent chips.In the process forming described plastic packaging layer, space has been reserved in the thermal expansion being support plate due to described groove, thus can discharge the stress because producing because of thermal dilation difference between support plate and plastic packaging layer, thus suppresses the chip generation drift phenomenon being fixed on support plate surface.Meanwhile, because described stress is released, thus formed plastic packaging layer generation warped problem can be suppressed.Position alignment then between the wire structures again of follow-up formation and described chip is accurate.Therefore, the yield of the encapsulating structure formed improves, and reliability strengthens.
Further, the technique forming some grooves in the cutting area of described support plate first surface is laser cutting parameter, described laser cutting parameter can directly carry out aiming at and cutting at the first surface of described support plate, therefore, described laser cutting parameter is adopted to form groove more simple, and the groove location formed is more accurate, and less for the damage on support plate surface.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of wafer level packaging structure embodiment;
Fig. 2 to Figure 15 is the structural representation of the encapsulation process of the embodiment of the present invention.
Embodiment
As stated in the Background Art, the reliability of existing Wafer level packaging is poor, and the encapsulating structure yield formed with existing Wafer level packaging is lower.
Please refer to Fig. 1, Fig. 1 is a kind of cross-sectional view of wafer level packaging structure embodiment, comprising: support plate 100; Be fixed on some chips 101 on support plate 100 surface, described chip 101 comprises functional surfaces; Be covered in the plastic packaging layer 102 on described support plate 100 and some chips 101 surface.Wherein, after the surperficial adhering chip 101 of described support plate 100, form described plastic packaging layer 102 by the plastic package process such as injection moulding or metaideophone, and described plastic packaging layer 102 wraps up described chip 101.After formation plastic packaging layer 102, also comprise: remove described support plate 100, and expose the functional surfaces of chip 101; Wiring layer is again formed at plastic packaging layer 102 and chip 101 functional surfaces surface; Ball is planted on the described surface of wiring layer again; After planting ball, described wiring layer again and plastic packaging layer 102 are cut, make some chips 101 mutually discrete, and each chip 101 surface is wrapped up by plastic packaging layer 102.
But, find through research, because the material of described support plate 100 is generally PCB substrate, glass substrate, metal substrate or semiconductor substrate, described chip 101 is formed by wafer manufacture usually, and the material of the described plastic packaging layer 102 normally polymeric material such as resin, therefore, between described plastic packaging layer 102 and support plate 100, or all easily between plastic packaging layer 102 and chip 101 produce stress because of the thermal dilation difference between material.And for full wafer support plate 100, described stress can build up to edge from support plate 100 center, causes the edge stress of support plate 100 to be greater than the stress at center.And described support plate 100 surface is bonded with some chips 101, due to the stress difference of described support plate 100 center and peripheral, easily cause die drift, especially the closer to the edge of described support plate 100, the phenomenon that drift occurs described chip 101 is more serious.
Described chip 101 once drift about, then can counteract the aligning accuracy of subsequent technique; Such as, after removal support plate 100, when plastic packaging layer 102 and chip 101 functional surfaces surface form wiring layer again, or when ball is planted on the described surface of wiring layer again, due to the drift of chip 101, easily make again the contraposition of wiring layer or plant ball contraposition generation deviation, thus reduce the yield of product.
Secondly, due to the stress influence between described support plate 100 and plastic packaging layer 102, also easy after employing plastic package process forms described plastic packaging layer 102, cause plastic packaging layer 102, relative to full wafer support plate 100, warpage occurs, the easy equally aligning accuracy to subsequent technique causes harmful effect, causes product yield to reduce.
In order to solve the problem, the invention provides a kind of method for packing, comprising: providing support plate, described support plate comprises some chip region and the cutting area between adjacent core section, and described support plate comprises first surface; Some grooves are formed in the cutting area of described support plate first surface; There is provided chip, described chip comprises relative functional surfaces and non-functional; Non-functional of described chip is fixed with the first surface in carrier chip district; After fixing with the first surface in carrier chip district by non-functional of chip, form salient point on the functional surfaces surface of described chip; Form plastic packaging layer at described support plate first surface and chip surface, described plastic packaging layer exposes the top surface of described salient point; After the described plastic packaging layer of formation, remove described support plate; Wire structures is again formed at the top surface of described plastic packaging layer surface and salient point; To described plastic packaging layer and again wire structures cut, make some chips mutually discrete, form independently encapsulating structure.
Wherein, before the first surface functional surfaces of chip being fixed on carrier chip district, some grooves are formed in the cutting area of support plate, described groove can be passed through, make between the plastic packaging layer of follow-up formation and described support plate, the stress produced because of thermal expansion coefficient difference is released, and eliminates with this die drift problem and plastic packaging layer warped problem that are caused by stress.Described groove type is formed in cutting area, and described cutting area is between adjacent core section, and described chip region is used for fixed chip, then in the support plate of described groove between adjacent chips.In the process forming described plastic packaging layer, space has been reserved in the thermal expansion being support plate due to described groove, thus can discharge the stress because producing because of thermal dilation difference between support plate and plastic packaging layer, thus suppresses the chip generation drift phenomenon being fixed on support plate surface.Meanwhile, because described stress is released, thus formed plastic packaging layer generation warped problem can be suppressed.Position alignment then between the wire structures again of follow-up formation and described chip is accurate.Therefore, the yield of the encapsulating structure formed improves, and reliability strengthens.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 to Figure 15 is the structural representation of the encapsulation process of the embodiment of the present invention.
Please refer to Fig. 2, provide support plate 200, described support plate 200 comprises some chip region 201 and the cutting area between adjacent core section 201 202, and described support plate 200 comprises first surface 203.
Described support plate 200 provides workbench for subsequent technique, for the plastic packaging layer of carries chips and follow-up formation.In the present embodiment, described support plate also comprises the second surface relative with first surface.
In the present embodiment, described support plate 200 is rigid substrate, and described rigid substrate is PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates.Described rigid substrate has higher hardness, not easily deformation occurs, and is enough to supporting chip and plastic packaging layer in subsequent technique.In other embodiments, described support plate 200 can also be flexible base plate.
The first surface 203 of described support plate 200 is for fixed chip.The plastic packaging layer of follow-up formation is positioned at the first surface 203 of described support plate 200.The chip region 201 of described support plate 200 is follow-up for fixed chip; The plastic packaging layer region of cutting area 202 correspondence of described support plate 200 is follow-up position of carrying out cutting, and makes the chip being positioned at each chip region 201 separate, to form encapsulating structure by cutting.
Please refer to Fig. 3, in the cutting area 202 of described support plate 200 first surface 203, form some grooves 204.
Described groove 204 is positioned at cutting area 202, and described cutting area 202 is between adjacent core section 201, and namely described groove 204 is between adjacent core section 201.The first surface 203 of described chip region 201 is at follow-up fixed chip, then described groove 204 is between the follow-up adjacent chips being fixed on support plate 200 surface.
Owing to there is thermal expansion coefficient difference between described support plate 200 and the plastic packaging layer of follow-up formation, described groove 204 can be then the thermal expansion headspace of support plate 200.Formed in the process of plastic packaging layer follow-up in support plate 200 first surface 203 and chip surface, because described groove 204 can offset the thermal dilation difference between described support plate 200 and plastic packaging layer, thus the stress of described support plate 200 can be discharged, and then the drift phenomenon of chip generation surperficial relative to support plate 200 can be suppressed, make after formation plastic packaging layer, described chip is still accurate relative to the position of support plate 200.Thus, follow-up formation again wire structures time be easy to exactitude position, the status of electrically connecting described in making again between wire structures and described chip is good, improves the reliability of encapsulating structure.
And, because the groove 204 formed in described support plate 200 can discharge the stress of support plate 200, thus be conducive to suppressing the warping phenomenon that the plastic packaging layer of follow-up formation occurs, be conducive to equally follow-up formation again wire structures time carry out exactitude position, and improving the pattern of encapsulating structure of follow-up formation, the encapsulating structure yield formed improves.
In the present embodiment, the technique forming some grooves 204 in the cutting area 202 of described support plate 200 first surface 203 is laser cutting parameter.Described laser cutting parameter can directly carry out aiming at and cutting at the first surface 203 of support plate 200, therefore operates comparatively easy, and groove 204 position formed is accurate, and the damage for support plate 200 first surface 203 is also less.
In one embodiment, when adopting described laser cutting parameter to form groove 204, the first surface 203 of described laser cutting parameter in support plate 200 chip region 201 can also be adopted to form alignment mark; Described alignment mark is used for aiming at when follow-up adhering chip, makes the position of chip in chip region 201 accurate.Because described groove 204 and alignment mark are formed simultaneously, can Simplified flowsheet step.
In another embodiment, the step forming some grooves 204 in the cutting area 202 of described support plate 200 first surface 203 comprises: form mask layer at the first surface 203 of described support plate 200, described mask layer exposes the cutting area 202 of support plate; With described mask layer for mask, etch described support plate 200, form groove 204 at the first surface 203 of described support plate 200.
Described etching technics is dry etch process or wet-etching technology.In one embodiment, the technique that etching forms described groove 204 is anisotropic dry etch process, and described anisotropic dry etch process accurately can control formed groove 204 sidewall.In other embodiments, described dry etch process can also be isotropic dry etch process.
In the present embodiment, the ratio between the degree of depth of described groove 204 and described support plate 200 thickness is less than or equal to 3/4.If the degree of depth of described groove 204 is excessive, then easily in subsequent technique, described support plate 200 is caused to rupture; And the ratio between the degree of depth and support plate 200 thickness of described groove 204 is when being less than or equal to 3/4, described groove 204 while guarantee is enough to release support plate 200 stress, can ensure that described support plate 200 not easily ruptures in subsequent technique.
Described groove 204 is V-type or U-shaped perpendicular to the shape of cross section in support plate 200 first surface 203 direction.In the present embodiment, the shape of cross section of described groove 204 is V-type, and namely the bottom size of described groove 204 is less than top dimension, has drift angle bottom described groove 204.In another embodiment, when the shape of cross section of described groove 204 is U-shaped, the sidewalls orthogonal of described groove 204 is in the first surface 203 of support plate 200.
Please refer to Fig. 4, Fig. 4 is the plan structure schematic diagram of support plate 200 described in full wafer towards first surface 203, and described some chip region 201 are arrayed along first direction X and second direction Y, and described first direction X is mutually vertical with second direction Y.
Described groove 204 is parallel to first direction X and second direction Y respectively, distributes as net shape.Surround by described groove 204 around each chip region 201 of described support plate 200, then follow-up after first surface 203 fixed chip of described chip region 201, described chip circumference is surrounded by described groove 204, the stress equilibrium of support plate 200 chip region 201 ground can be made to discharge towards periphery, help avoid the follow-up chip being fixed on chip region 201 and drift about because of the unbalanced stress of chip region 201.
In other embodiments, equally distributed some discrete grooves can also be formed in the cutting area around described chip region.
Please refer to Fig. 5, provide chip 210, described chip 210 comprises relative functional surfaces 211 and non-functional face 212.
Described chip 210 can be sensor chip, logic circuit chip, storage chip etc.Can have in transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, transducer, electric interconnection structure in the functional surfaces 211 of described chip 210 one or more.The forming step of described chip 210 comprises: provide substrate, and described substrate has some chip region; Described substrate is cut, some chip region are separated from each other, form independently chip 210.
In the present embodiment, functional surfaces 211 surface of described chip 210 exposes weld pad 213.Described weld pad 213 surface higher than, lower than or the functional surfaces 211 that flushes in described chip 210.The material of described weld pad 213 comprise in copper, aluminium, silver, gold, tin, titanium, tantalum, silicon nitride or tantalum nitride one or more.Described weld pad 213 can realize being electrically connected with the circuit in functional surfaces 211 or device.Described weld pad 213 for being electrically connected with the wire structures again of follow-up formation, thus realizes the electrical connection between the functional surfaces 211 of chip 210 and other chip or external circuit.
In other embodiments, described functional surfaces 211 can also comprise sensor region, has transducer in described sensor region, and described transducer is for obtaining the information in external environment condition.
The follow-up functional surfaces 211 by described chip 210 is fixed with the first surface 203 (as shown in Figure 3) of support plate 200 (as shown in Figure 3) chip region 201 (as shown in Figure 3).Be described below with reference to accompanying drawing.
Please refer to Fig. 6, paste the first tack coat 214 in the non-functional face 212 of described chip 210.
In the present embodiment, described first tack coat 214, for being be combined with each other with the first surface 203 of support plate 200 in the non-functional face 212 of chip 210, makes described chip 210 realize formal dress.
In one embodiment, the material of described first tack coat 214 is UV glue, and described UV glue viscosity after Ultraviolet radiation reduces, and is peeled off by support plate 200 so that follow-up from encapsulating structure.
In another embodiment, described first tack coat 214 can be formed at the functional surfaces 211 of chip 210 by coating process.In other embodiments, described first tack coat 214 can also be viscous material layer, is directly attached at the non-functional face 212 of described chip 210.
Please refer to Fig. 7, by mutually bonding with the first surface 203 of support plate 200 chip region 201 for described first tack coat 214, with the first surface 203 of the non-functional face 212 of fixed chip 210 and support plate 200 chip region 201.
In the present embodiment, the non-functional face 212 of described chip 210 combines with support plate 200 first surface 203, namely realizes chip 210 formal dress.
Support plate 200 surface is adhered to again after forming the first tack coat 214 in the non-functional face 212 of chip 210, make described first tack coat 214 can only between support plate 200 and chip 210, thus the groove 204 of support plate 200 can be exposed, not only be conducive to the combination between the plastic packaging layer of follow-up formation and support plate 200, also help the stress that described groove 204 discharges support plate 200.
In another embodiment, the step that the first surface in the functional surfaces of described chip and carrier chip district is fixing is comprised: be coated with the second tack coat at the first surface of described support plate; The functional surfaces of chip is adhered to described second tie layer surface, and makes described chip be positioned at carrier chip district.
Please refer to Fig. 8, after being fixed with the first surface 203 of support plate 200 chip region 201 in the non-functional face 212 of chip 210, form salient point 215 (studbond) on functional surfaces 211 surface of described chip 210.
In the present embodiment, the functional surfaces 211 of described chip 210 exposes weld pad 213, and described salient point 215 is formed at described solder joint 213 surface.
The material of described salient point 215 is gold, silver, copper, billon, silver alloy or copper alloy.In one embodiment, the formation process of described salient point 215 is lead key closing process; Described lead key closing process comprises thermocompression bonding, supersonic bonding or Heat Ultrasonic Bonding.In the present embodiment, described salient point 215 adopts thermosonic bonding process to be formed.In described lead key closing process, the chopper adopted is wedge shape or spherical.
In other embodiments, described salient point 215 can also form conductive layer by plating or depositing operation, and etches to form salient point 215 to described conductive layer.
In the present embodiment, described salient point 215 comprises some stacking sub-salient points, and each sub-salient point is with key and the technique formation of once going between.The salient point 215 adopting lead key closing process to be formed or sub-salient point comprise salient point body and are positioned at the protuberance of salient point body surface.In the present embodiment, described chopper is spherical, and the salient point body formed is column.In one embodiment, after often once go between key and technique form sub-salient point, formed sub-salient point is flattened.In other embodiments, can not also flatten after opening lead key closing process.
Be fixed on the sub-salient point that the salient point 215 that the chip 210 on same support plate 200 surface is formed has equal number.In the present embodiment, be fixed on the salient point 215 that the chip 210 on same support plate 200 surface is formed and all there are two stacking sub-salient points.In other embodiments, described salient point 215 is single independent salient point.
Please refer to Fig. 9, form plastic packaging layer 220 at described support plate 200 first surface 203 and chip 210 surface, described plastic packaging layer 220 exposes the top surface of described salient point 215.
The forming step of described plastic packaging layer 220 comprises: adopt plastic package process to form initial plastic packaging layer at described support plate 200 first surface 203 and chip 210 surface, described initial plastic packaging layer covers functional surfaces 211 and the salient point 215 of described chip 210; Initial plastic packaging layer described in planarization, till exposing described salient point 215 top, forms described plastic packaging layer 220.In the present embodiment, described flatening process is CMP (Chemical Mechanical Polishing) process (ChemicalMechanicalPolishing is called for short CMP); And described flatening process can also remove the top of the described salient point 215 of part, make exposed salient point 215 top surface smooth.
In the present embodiment, because non-functional face 212 and support plate 200 first surface 203 of described chip 210 interfix, then described initial plastic packaging layer covers functional surfaces 211 and the salient point 215 of described chip 210.After follow-up removal support plate 200, described plastic packaging layer 220 surface directly can expose the non-functional face 212 of chip 210.
In the present embodiment, described plastic packaging layer 220 exposes the surface of salient point 215 is the 3rd surface; In addition, described plastic packaging floor 220 can also comprise Cutting Road district, and the Cutting Road district of described plastic packaging floor 220 is positioned at cutting area 202 surface of described support plate 200.
Described plastic packaging layer 220 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, described plastic packaging layer 220 is photosensitive dry film; The formation process of described initial plastic packaging layer is vacuum film coating process.
In another is implemented, the material of described plastic packaging layer 220 is capsulation material, and described capsulation material comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of described initial plastic packaging layer comprises Shooting Technique (injectionmolding), turns and mould technique (transfermolding) or silk-screen printing technique.Described Shooting Technique comprises: provide mould; Fill capsulation material in the mold, make the coated described chip 210 of described capsulation material; Elevated cure is carried out to described capsulation material, forms initial plastic packaging layer.
In the process of described elevated cure, have groove 204 in the first surface 203 due to described support plate 200 cutting area 202, described groove 204 can offset the thermal dilation difference between described support plate 200 and initial plastic packaging layer, discharges the stress of support plate 200 thus.Thus chip 210 position being positioned at support plate 200 first surface 203 can be avoided to drift about, can also avoid described plastic packaging layer 220, relative to support plate 200, warpage occurs.Therefore, the contraposition between the wire structures again of follow-up formation and described chip 210 functional surfaces 211 is more accurate, makes the electrical connection properties between wire structures and salient point 215 more excellent again.
In other embodiments, the material of described plastic packaging layer 220 also can be other insulating material.
In the present embodiment, in first surface 203 due to described support plate 200 cutting area 202, also there is groove 204, the plastic packaging layer 220 formed also is positioned at described groove 204 (as shown in Figure 8), and the part plastic packaging layer 220 being positioned at groove 204 forms the projection protruding from plastic packaging layer 220 surface.
Please refer to Figure 10, remove described support plate 200 (as shown in Figure 9).
In one embodiment, because the material of described first tack coat 214 (as shown in Figure 9) is UV glue, by carrying out UV-irradiation to described first tack coat 214, the viscosity of described first tack coat 214 can be made to reduce; Again by the functional surfaces 211 of described support plate 200 from described chip 210 and the 3rd sur-face peeling of plastic packaging layer 220.
In other embodiments, described support plate 200 can also be removed by etching technics or CMP (Chemical Mechanical Polishing) process.
After the described support plate 200 of removal, described in follow-up formation again before wire structures, also comprise and the functional surfaces 211 of described plastic packaging layer 220 surface and chip 210 is cleaned, remove the first residual tack coat 214 material with this.
In the present embodiment, after the described support plate 200 of removal, also comprise and remove the part plastic packaging layer 220 being positioned at described groove 204 and form projection; The technique removing described projection can be glossing, etching technics or plasma-treating technology.
Follow-uply form wire structures again on described plastic packaging layer 220 the 3rd surface and salient point 215 top surface.Be described below with reference to accompanying drawing.
Please refer to Figure 11, form the first insulating barrier 230 on described plastic packaging layer 220 surface, there is in described first insulating barrier 230 the first through hole 231 exposing described salient point 215 top surface.
Described first insulating barrier 230 is for the protection of described plastic packaging layer 220 surface.In the present embodiment, described first through hole 231 exposes described salient point 215 top surface, and described first through hole 231 can enable the wire structures again of follow-up formation be electrically connected with salient point 215.
The forming step of described first insulating barrier 230 comprises: form the first dielectric film on described plastic packaging layer 220 the 3rd surface and salient point 215 surface; Carry out graphically, forming the first insulating barrier 230 to described first dielectric film, and in described first insulating barrier 230, there is the first through hole 231.
In one embodiment, the material of described first insulating barrier 230 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described first dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the first insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described first dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH
4, CHF
3, CH
3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of the first insulating barrier 230 is photoresist, and described first through hole 231 adopts photoetching process to be formed.
Please refer to Figure 12, in described first through hole 231 (as shown in figure 11) and part first insulating barrier 230 surface formed described in wire structures 232 again.
The forming step of described wire structures again 232 comprises: in described first through hole 231 and the first insulating barrier 230 surface form conducting film, described conducting film fills full described first through hole 231; Conducting film described in planarization; After flatening process, form patterned layer, described patterned layer cover part conducting film on described conducting film surface; With described patterned layer for mask, etch described conducting film, till exposing the first insulating barrier 230; After the described conducting film of etching, remove described patterned layer.
In the present embodiment, described first through hole 231 exposes salient point 215, then the wire structures again 232 be formed in described first through hole 231 can be electrically connected with described salient point 215.
The material of described conducting film comprise in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver one or more; The technique etching described conducting film is anisotropic dry etch process or wet processing; Described patterned layer can be patterned photoresist layer, can also be patterned hard mask, the material of described hard mask be a kind of in silica, silicon nitride, silicon oxynitride or multiple; Described flatening process can be CMP (Chemical Mechanical Polishing) process.
Described wire structures again 232 can be single layer structure or sandwich construction, and the wire structures again 232 of described single layer structure or sandwich construction is for realizing specific circuit function.In the present embodiment, described wire structures again 232 is single layer structure.In other embodiments, described wire structures again can comprise multiple wiring layer, and with insulating barrier electric isolution between adjacent two layers wiring layer.
In another embodiment, described wire structures is more directly formed at the top surface of plastic packaging layer surface and described salient point.
Please refer to Figure 13, form the second insulating barrier 233 on described wire structures again 232 surface, there is in described second insulating barrier 233 the second through hole 234 exposing partly again wire structures 232.
Described second insulating barrier 233 is solder mask, and described second insulating barrier 233 is for the protection of wire structures 232 again described in layer, and the second through hole 234 in described second insulating barrier 233 is for defining the position of the soldered ball of follow-up formation.
The forming step of described second insulating barrier 233 comprises: form the second dielectric film at wire structures 232 again and the first insulating barrier 230 surface; Carry out graphically, forming the second insulating barrier 233 to described second dielectric film, and in described second insulating barrier 233, there is described second through hole 234.
In one embodiment, the material of described second insulating barrier 233 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described second dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the second insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described second dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH
4, CHF
3, CH
3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of described second insulating barrier 233 is photoresist, and described second through hole 234 adopts photoetching process to be formed.
Please refer to Figure 14, in described second through hole 234 (as shown in figure 13), form described soldered ball 235, described soldered ball 235 is positioned at wire structures 232 surface again.
The material of described soldered ball 235 comprises tin.The forming step of described soldered ball 235 comprises: the wire structures again 232 surface printing tin cream bottom described second through hole 234, then carries out high temperature reflux, under surface tension effects, forms soldered ball 235.
In another embodiment, can also wire structures again 232 surface printing scaling powder first bottom described second through hole 234 and soldered ball particle, then high temperature reflux forms soldered ball 235.In other embodiments, can also on described wire structures again 232 electrotinning post, then high temperature reflux formed soldered ball 235.
In one embodiment, between described wire structures again 233 and described soldered ball 235, metal structure under ball (UnderBallMetal is called for short UBM) can also be had; Under described ball, metal structure can comprise the metal level of single metal layer or multiple-layer overlapped; The material of described single metal layer or more metal layers comprises one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
In one embodiment; after removal support plate 200 (as shown in Figure 9); follow-up carry out cutting technique before; the surface, non-functional face 212 being also included in described chip 210 and plastic packaging layer 220 surface exposing described non-functional face 212 form protective layer (not shown); described protective layer is for the protection of the non-functional face 212 of the chip 210 exposed; and described protective layer can also be used for identification markings, for recording the label of formed encapsulating structure.
Please refer to Figure 15, to described plastic packaging layer 220 and again wire structures 232 cut, make some chips 210 mutually discrete, form independently encapsulating structure.
In the present embodiment, the part that described plastic packaging floor 220 is positioned at support plate 200 (as shown in Figure 9) cutting area 202 surface is Cutting Road district, namely described cutting technique cuts the described wire structures again cut plastic packaging Ceng220Ge road district and be positioned at surface, Cutting Road district, thus some chips 210 can be made separate, form described encapsulating structure with this; Described encapsulating structure comprises chip 210, wraps up the plastic packaging layer 220 of described chip 210 and is positioned at the wire structures again 232 on plastic packaging layer 220 and chip 210 surface.
To sum up, in the present embodiment, before the first surface functional surfaces of chip being fixed on carrier chip district, some grooves are formed in the cutting area of support plate, described groove can be passed through, make between the plastic packaging layer of follow-up formation and described support plate, the stress produced because of thermal expansion coefficient difference is released, and eliminates with this die drift problem and plastic packaging layer warped problem that are caused by stress.Described groove type is formed in cutting area, and described cutting area is between adjacent core section, and described chip region is used for fixed chip, then in the support plate of described groove between adjacent chips.In the process forming described plastic packaging layer, space has been reserved in the thermal expansion being support plate due to described groove, thus can discharge the stress because producing because of thermal dilation difference between support plate and plastic packaging layer, thus suppresses the chip generation drift phenomenon being fixed on support plate surface.Meanwhile, because described stress is released, thus formed plastic packaging layer generation warped problem can be suppressed.Position alignment then between the wire structures again of follow-up formation and described chip is accurate.Therefore, the yield of the encapsulating structure formed improves, and reliability strengthens.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a method for packing, is characterized in that, comprising:
There is provided support plate, described support plate comprises some chip region and the cutting area between adjacent core section, and described support plate comprises first surface;
Some grooves are formed in the cutting area of described support plate first surface;
There is provided chip, described chip comprises relative functional surfaces and non-functional;
Non-functional of described chip is fixed with the first surface in carrier chip district;
After fixing with the first surface in carrier chip district by non-functional of chip, form salient point on the functional surfaces surface of described chip;
Form plastic packaging layer at described support plate first surface and chip surface, described plastic packaging layer exposes the top surface of described salient point;
After the described plastic packaging layer of formation, remove described support plate;
Wire structures is again formed at the top surface of described plastic packaging layer surface and salient point;
To described plastic packaging layer and again wire structures cut, make some chips mutually discrete, form independently encapsulating structure.
2. method for packing as claimed in claim 1, it is characterized in that, the formation process of described salient point comprises lead key closing process.
3. method for packing as claimed in claim 1, it is characterized in that, the material of described salient point is gold, silver, copper, billon, silver alloy or copper alloy.
4. method for packing as claimed in claim 1, it is characterized in that, described salient point comprises some stacking sub-salient points; After often once go between key and technique form sub-salient point, formed sub-salient point is flattened.
5. method for packing as claimed in claim 1, it is characterized in that, the functional surfaces surface of described chip exposes weld pad; Described weld pad surface lower than or the functional surfaces that flushes in described chip; Described salient point is positioned at described weld pad surface.
6. method for packing as claimed in claim 1, is characterized in that, the step that non-functional of described chip is fixed with the first surface in carrier chip district is comprised: paste the first tack coat for non-functional at described chip; Described first tack coat is mutually bonding with the first surface in carrier chip district, with the first surface in non-functional of fixed chip and carrier chip district.
7. method for packing as claimed in claim 1, is characterized in that, the step that non-functional of described chip is fixed with the first surface in carrier chip district is comprised: be coated with the second tack coat at the first surface of described support plate; The non-functional face of chip is adhered to described second tie layer surface, and makes described chip be positioned at carrier chip district.
8. method for packing as claimed in claim 1, it is characterized in that, the technique forming some grooves in the cutting area of described support plate first surface is laser cutting parameter.
9. method for packing as claimed in claim 1, it is characterized in that, the step forming some grooves in the cutting area of described support plate first surface comprises: form mask layer at the first surface of described support plate, described mask layer exposes the cutting area of support plate; With described mask layer for mask, etch described support plate, form groove at the first surface of described support plate.
10. method for packing as claimed in claim 9, it is characterized in that, described etching technics is dry etch process or wet-etching technology.
11. method for packing as claimed in claim 1, is characterized in that, the shape of cross section of described texturearunaperpendicular in support plate first surface direction is V-type or U-shaped; When the shape of cross section of described groove is V-type, the bottom size of described groove is less than top dimension, and described bottom portion of groove has drift angle; When the shape of cross section of described groove is U-shaped, the sidewalls orthogonal of described groove is in the first surface of support plate.
12. method for packing as claimed in claim 1, it is characterized in that, the forming step of described plastic packaging layer comprises: adopt plastic package process to form initial plastic packaging layer at described support plate first surface and chip surface, described initial plastic packaging layer covers functional surfaces and the salient point of described chip; Initial plastic packaging layer described in planarization, till exposing described salient point top, forms described plastic packaging layer.
13. method for packing as claimed in claim 1, is characterized in that, also comprise: after the described support plate of removal, described in formation again before wire structures, clean described plastic packaging layer surface and chip surface.
14. method for packing as claimed in claim 1, it is characterized in that, described plastic packaging layer is also positioned at described groove; After the described support plate of removal, the part plastic packaging layer being positioned at described groove forms projection; Again before wire structures, also comprise and remove described projection described in formation.
15. method for packing as claimed in claim 1, is characterized in that, also comprise: described in formation again before wire structures, form the first insulating barrier, have the first through hole exposing described chip surface salient point in described first insulating barrier on described plastic packaging layer surface; In described first through hole and part first surface of insulating layer formed described in wire structures again.
16. method for packing as claimed in claim 1, is characterized in that, also comprise: described in formation again after wire structures, to described support plate, plastic packaging layer with before wire structures cuts again, form soldered ball on the described surface of wire structures again.
17. method for packing as claimed in claim 1, is characterized in that, also comprise: before the described soldered ball of formation, form the second insulating barrier, have the second through hole exposing partly again wire structures in described second insulating barrier on the described surface of wire structures again; Described soldered ball is formed in described second through hole.
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| CN201510747322.7A CN105390429A (en) | 2015-11-05 | 2015-11-05 | Packaging method |
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