CN114361051A - Multi-chip normal-mounting reset wafer-level packaging structure and method - Google Patents
Multi-chip normal-mounting reset wafer-level packaging structure and method Download PDFInfo
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- CN114361051A CN114361051A CN202111599166.6A CN202111599166A CN114361051A CN 114361051 A CN114361051 A CN 114361051A CN 202111599166 A CN202111599166 A CN 202111599166A CN 114361051 A CN114361051 A CN 114361051A
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Abstract
The invention discloses a multi-chip positive mounting reset wafer level packaging structure and a method, which comprises the following steps: the multi-chip resetting layout is characterized in that different types of chips 1 are placed on a substrate 12 pasted with a temporary bonding film 11 by adopting a chip pasting process, the front sides of the chips are upward, and the back sides of the chips are pasted on the temporary bonding film on the substrate; the front surface of the chip comprises an electrode and a key functional area; manufacturing a first insulating layer, namely manufacturing the first insulating layer 15 on the chip surface of the substrate 12 by using coating, spraying and laminating processes, and performing patterning treatment by using photoetching and other processes to expose partial electrodes and all key functional areas of the chip; and finally, finishing the re-wiring process, finishing the main packaging process, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding. The multi-chip packaging process belongs to one-time packaging of a plurality of chips, simplifies the packaging process of the plurality of chips and improves the packaging efficiency.
Description
Technical Field
The invention belongs to the field of semiconductors, particularly relates to different types of chip resetting and multi-chip packaging technologies of a filter wafer, and relates to a wafer-level packaging structure and a wafer-level packaging method of a filter.
Background
The present packaging technology adopts the flip-chip tectorial membrane to form the cavity, has certain requirement to the chip clearance, and the flip-chip base plate also need predetermine and corresponds the figure, and the technology is complicated, and application number is 201621225249.3 patent, and this patent discloses a multi-chip module packaging structure including film body acoustic wave device bare chip, including base plate and bare chip, the bare chip includes film body acoustic wave device bare chip and other function bare chips, is equipped with corresponding electrode, its characterized in that on base plate and all bare chips: all the bare chip electrodes are correspondingly connected with the substrate electrode through gold balls by flip-chip welding, a film layer is fixedly bonded on the surface of the substrate, the film layer is tightly attached to the surface of the substrate and wraps all the bare chips at the same time, all the bare chips are arranged at intervals and separated through the film layer, and a vacuum cavity is formed between all the bare chips and the substrate. The invention directly adopts bare chip package, which greatly reduces the volume compared with the original secondary package; the patent application No. 202020151459.2 discloses a modular package structure comprising: a substrate, wherein the substrate is provided with a first welding pad, a second welding pad and at least one anti-overflow assembly; the surface of the at least one first electronic component is provided with a plurality of first conductive contacts, and the first conductive contacts are attached and welded in an area surrounded by the anti-overflow components; a first encapsulation layer located among the at least one anti-overflow assembly, the at least one first electronic assembly and the substrate; at least one second electronic component, a plurality of second conductive contacts are formed on the surface of the second electronic component.
Firstly, the anti-overflow assembly is preset on the packaging substrate, so that the chip spacing is large and the whole packaging volume is large; moreover, the chip is preset in the substrate groove, the surface of the chip cannot be protected, and the process difficulty of placing the groove on the chip is high.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the filter wafer level packaging structure and the method which are flexible in combination packaging, can screen out damaged chips, simplify the packaging process and improve the packaging efficiency and yield.
The technical scheme of the invention is as follows: a multi-chip forward-mounting reset wafer level packaging method comprises the following steps:
step 1, resetting layout of multiple chips, namely placing the chips 1 of different types on a substrate 12 pasted with a temporary bonding film 11 by adopting a chip pasting process, wherein the front sides of the chips are upward, and the back sides of the chips are pasted on the temporary bonding film on the substrate; the front surface of the chip comprises an electrode and a key functional area;
step 2, manufacturing a first insulating layer, namely manufacturing a first insulating layer 15 on the chip surface of the substrate 12 by using coating, spraying and laminating processes, and performing patterning treatment by using photoetching and other processes to expose partial electrodes and all key functional areas of the chip;
step 3, manufacturing a substrate on the first insulating layer, attaching a temporary bonding film 11 and a substrate 12 on the first insulating layer on the front side of the chip by adopting a temporary bonding process, and then removing the temporary bonding film and the substrate on the back side of the chip;
step 4, manufacturing protection by using the chip back surface integral plastic package layer 161, and integrally encapsulating a layer of plastic package layer 16 on the back surface and the side wall of the chip by using a wafer-level injection molding process to protect the chip;
step 5, removing the substrate 12 and the temporary bonding film 11 on the first insulating layer 15 on the front surface of the chip, and exposing the electrode and the key function area of the chip;
step 6, manufacturing a second insulating layer 17, attaching the second insulating layer 17 on the first insulating layer 15 by using a laminating process, exposing the cutting channel and a part of the electrode area by using a photoetching process, and forming a sealed cavity structure with the first insulating layer to protect a key function area without exposing the key function area;
step 7, manufacturing a metal interconnection line 18, namely manufacturing the metal interconnection line 18 on the electrode by using PVD (physical vapor deposition), electroplating, photoetching and etching processes, namely manufacturing the metal interconnection line 18 in a through hole formed by the first insulating layer 15 and the second insulating layer 17, wherein the height of the metal interconnection line is higher than the surface of the second insulating layer;
step 8, manufacturing a chip front surface plastic package layer 162, namely manufacturing the chip front surface plastic package layer 162 by using a wafer-level injection molding process, wherein the plastic package layer 162 encapsulates the electrode, the surface of the second insulating layer 17 and the side wall of the second insulating layer; and is communicated with the plastic packaging layer 161 on the back side at the cutting path;
step 9, performing a head exposing process on the metal interconnection line 18, namely thinning the plastic packaging layer 162 on the front surface of the chip by adopting a grinding process to leak the encapsulated metal interconnection line 18, wherein the metal interconnection line 18 and the upper surface of the plastic packaging layer 162 are on the same plane;
step 10, manufacturing a metal interconnection line rewiring layer 19, and performing a rewiring process on the plastic packaging layer 162 and the metal interconnection lines 18 by utilizing PVD (physical vapor deposition), electroplating, photoetching and etching processes to redefine the rewiring layer 19 at the positions of the metal interconnection lines;
and 11, finishing the main packaging process after finishing the rewiring process, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
Further, the key functional areas are an IDT area of the surface acoustic wave filter and a resonant cavity area of the bulk acoustic wave filter.
Further, the thickness of the first insulating layer is more than 1 um.
Furthermore, the thickness of the plastic packaging layer is larger than 1um, and the material of the plastic packaging layer is any one of plastic packaging material, polymer and resin.
Further, the thickness of the second insulating layer is larger than 1 um.
Further, the metal of the metal interconnection line is any one of Al, Cu, Ti, Ni, and Sn, and an alloy thereof.
Further, the thickness of the chip front molding layer 162 is greater than 1 um.
Further, the thickness of the rewiring layer 19 is more than 1 um; the material is any one of Al, Cu, Ti, Ni and Sn and alloy thereof.
The invention discloses a multi-chip positive mounting resetting wafer level packaging structure which comprises a multi-chip resetting layout, wherein the front surface of a chip is upward and comprises an electrode and a key function area;
the front surface of the chip is adhered with a first insulating layer 15, and partial electrodes and all key functional areas of the chip are exposed; a plastic layer 161 is integrally encapsulated on the back surface and the side wall of the chip; a second insulating layer 17 is attached to the first insulating layer 15, and the cutting channels and partial electrode areas are exposed, so that a sealed cavity structure is formed by the key function area, the first insulating layer 15 and the second insulating layer 17; a metal interconnection line 18 is arranged in a through hole formed by the first insulating layer 15 and the second insulating layer 17, and the height of the metal interconnection line 18 is higher than the surface of the second insulating layer; the front surface of the chip is pasted with a plastic packaging layer 162, and the plastic packaging layer 162 encapsulates the electrode, the surface of the second insulating layer 17 and the side wall; and is communicated with the plastic packaging layer 161 on the back side at the cutting path; the encapsulated metal interconnection line 18 leaks out of the plastic packaging layer 162 on the front surface of the thinned chip, and at the moment, the metal interconnection line 18 and the upper surface of the plastic packaging layer 162 are on the same plane; a rewiring layer 19 is arranged on the plastic packaging layer 162 and the metal interconnection line 18; and cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
The invention has the beneficial effects that: the multi-chip packaging process belongs to one-time packaging of a plurality of chips, simplifies the packaging process of the plurality of chips and improves the packaging efficiency. The chips of multiple types can be combined freely, the realized functions are more flexible and diversified, and the abundant terminal requirements are met. The multi-chip resetting package can screen the chips before the chips are packaged, reject bad chips and improve the packaging yield. The type of the material to be cut is single, and the cutting difficulty is reduced.
Drawings
FIG. 1 is a schematic diagram of a multi-chip reset layout according to the present invention;
FIG. 2 is a schematic diagram illustrating the fabrication of a first insulating layer according to the present invention;
FIG. 3 is a schematic diagram of a first insulating layer on a substrate according to the present invention;
fig. 4 is a schematic view illustrating the protection of the chip backside integral molding layer 161;
FIG. 5 is a schematic view showing the electrodes and critical functional areas of the chip exposed;
FIG. 6 is a schematic view of fabricating the second insulating layer 17;
FIG. 7 is a schematic diagram of the fabrication of metal interconnection lines 18;
fig. 8 is a schematic diagram illustrating the fabrication of the front molding layer 162;
FIG. 9 is a schematic view of a metal interconnection line 18 outcrop process;
FIG. 10 is a schematic diagram of the fabrication of a redistribution layer 19 for metal interconnection lines.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
1. The multi-chip reset layout adopts a chip mounting process to place different types of chips (the number of the chips can be flexibly matched, here, 3 chips (101, 102, 103) are provided, the front surface of the chip is upward, the back surface of the chip is attached to the temporary bonding film on the substrate, the front surface of the chip comprises electrodes (each chip comprises electrodes 131, 132, 133), a key function region (for example, an IDT region of a surface acoustic wave filter, a resonant cavity region of a bulk acoustic wave filter, and the different chips comprise regions such as key function regions (141, 142, 143).
2. Manufacturing a first insulating layer, namely manufacturing the first insulating layer 15 on the chip surface of the substrate 12 by using the processes of coating, spraying, laminating and the like, and performing patterning treatment by using the processes of photoetching and the like to expose partial electrodes and all functional areas of the chip; the thickness of the first insulating layer is more than 1 um. As shown in fig. 2.
2. And (3) manufacturing a substrate on the first insulating layer, attaching a temporary bonding film 11 and a substrate 12 on the first insulating layer on the front side of the chip by adopting a temporary bonding process, and then removing the temporary bonding film and the substrate on the back side of the chip. As shown in fig. 3.
3. The chip back side integral plastic package layer 161 is used for protecting, and a wafer level injection molding process is adopted to integrally encapsulate a layer of plastic package layer 16 on the chip back side and the side wall to protect the chip; the thickness of the plastic package layer is larger than 1um, and the material of the plastic package layer can be plastic package material, polymer, resin and the like, which are not limited herein. As shown in fig. 4.
4. And removing the substrate 12 and the temporary bonding film 11 on the first insulating layer 15 on the front surface of the chip to expose the electrodes and the key functional area of the chip. As shown in fig. 5.
5. And manufacturing a second insulating layer 17, attaching the second insulating layer 17 on the first insulating layer 15 by using a laminating process, exposing the cutting channel and part of the electrode area by using a photoetching process, and forming a sealed cavity structure with the first insulating layer to protect the key function area without exposing the key function area. The thickness of the second insulating layer is greater than 1 um. As shown in fig. 6.
6. And (3) manufacturing a metal interconnection line 18, namely manufacturing the metal interconnection line 18 on the electrode by using the processes of PVD, electroplating, photoetching, etching and the like, namely, in the through hole formed by the first insulating layer 15 and the second insulating layer 17, wherein the height of the metal interconnection line is higher than the surface of the second insulating layer. The metal of the metal interconnection line may be Al, Cu, Ti, Ni, Sn metal, an alloy thereof, and the like, and is not limited herein. As shown in fig. 7.
7. Manufacturing a chip front surface plastic package layer 162, namely manufacturing the chip front surface plastic package layer 162 by using a wafer-level injection molding process, wherein the plastic package layer 162 encapsulates the electrode, the surface of the second insulating layer 17 and the side wall; and communicates with the back molding layer 161 at the dicing lane. The thickness of the chip front molding layer 162 is greater than 1 um. As shown in fig. 8.
8. The metal interconnection line 18 is exposed, and the encapsulated metal interconnection line 18 is exposed by adopting a grinding process to thin the plastic packaging layer 162 on the front surface of the chip. The metal interconnection line 18 is in the same plane as the upper surface of the molding layer 162. As shown in fig. 9.
9. And manufacturing the metal interconnection line rewiring layer 19, and performing a rewiring process on the plastic packaging layer 162 and the metal interconnection lines 18 by utilizing the processes of PVD, electroplating, photoetching, etching and the like to redefine the rewiring layer 19 at the positions of the metal interconnection lines. The thickness of the rewiring layer 19 is more than 1 um; the material may be Al, Cu, Ti, Ni, Sn metal, and alloy thereof, and is not limited herein. As shown in fig. 10.
And finishing the re-wiring process and then finishing the main packaging process, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
If the chip is required to be packaged in an ultrathin mode, thinning and re-packaging can be carried out from the back face after the 10 th re-wiring process is completed, and packaging requirements of different thicknesses are met.
Therefore, the innovation points of the invention are mainly reflected in the following points:
1. a multi-chip wafer level packaging method for bonding multiple bare chips on a substrate to form a packaging region.
2. And (3) a packaging process for forming a cavity structure of the support and the cover by using a double-layer structure.
3. The bilayer membrane is perforated and eventually filled to lead out a PAD-like lead scheme.
4. And a double-sided plastic packaging sealing process is adopted to realize a 6-sided chip packaging scheme.
The packaging process of the whole set of the filter formed by the multi-chip wafer level packaging technology.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (7)
1. A multi-chip forward-mounting reset wafer level packaging method is characterized by comprising the following steps:
step 1, resetting layout of multiple chips, namely placing the chips 1 of different types on a substrate 12 pasted with a temporary bonding film 11 by adopting a chip pasting process, wherein the front sides of the chips are upward, and the back sides of the chips are pasted on the temporary bonding film on the substrate; the front surface of the chip comprises an electrode and a key functional area;
step 2, manufacturing a first insulating layer, namely manufacturing a first insulating layer 15 on the chip surface of the substrate 12 by using coating, spraying and laminating processes, and performing patterning treatment by using photoetching and other processes to expose partial electrodes and all key functional areas of the chip;
step 3, manufacturing a substrate on the first insulating layer, attaching a temporary bonding film 11 and a substrate 12 on the first insulating layer on the front side of the chip by adopting a temporary bonding process, and then removing the temporary bonding film and the substrate on the back side of the chip;
step 4, the integral plastic layer 161 on the back of the chip is used for protecting, and a plastic packaging layer 16 is integrally packaged on the back and the side wall of the chip by adopting a wafer-level injection molding process to protect the chip;
step 5, removing the substrate 12 and the temporary bonding film 11 on the first insulating layer 15 on the front surface of the chip, and exposing the electrode and the key function area of the chip 10;
step 6, manufacturing a second insulating layer 17, attaching the second insulating layer 17 on the first insulating layer 15 by using a laminating process, exposing the cutting channel and a part of the electrode area by using a photoetching process, and forming a sealed cavity structure with the first insulating layer to protect a key function area without exposing the key function area;
step 7, manufacturing a metal interconnection line 18, namely manufacturing the metal interconnection line 18 on the electrode by using PVD (physical vapor deposition), electroplating, photoetching and etching processes, namely manufacturing the metal interconnection line 18 in a through hole formed by the first insulating layer 15 and the second insulating layer 17, wherein the height of the metal interconnection line is higher than the surface of the second insulating layer;
step 8, manufacturing a chip front surface plastic package layer 162, namely manufacturing the chip front surface plastic package layer 162 by using a wafer-level injection molding process, wherein the plastic package layer 162 encapsulates the electrode, the surface of the second insulating layer 17 and the side wall of the second insulating layer; and is communicated with the plastic packaging layer 161 on the back side at the cutting path;
step 9, performing a head exposing process on the metal interconnection line 18, namely thinning the plastic packaging layer 162 on the front surface of the chip by adopting a grinding process to leak the encapsulated metal interconnection line 18, wherein the metal interconnection line 18 and the upper surface of the plastic packaging layer 162 are on the same plane;
step 10, manufacturing a metal interconnection line rewiring layer 19, and performing a rewiring process on the plastic packaging layer 162 and the metal interconnection lines 18 by utilizing PVD (physical vapor deposition), electroplating, photoetching and etching processes to redefine the rewiring layer 19 at the positions of the metal interconnection lines;
and 11, finishing the main packaging process after finishing the rewiring process, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
2. The method as claimed in claim 1, wherein the key functional regions are IDT region of SAW filter and resonator region of bulk acoustic wave filter.
3. The method as claimed in claim 1, wherein the first insulating layer has a thickness of > 1 um.
4. The method as claimed in claim 1, wherein the thickness of the plastic package layer is greater than 1um, and the plastic package layer is made of any one of plastic package material, polymer and resin.
5. The method as claimed in claim 1, wherein the second insulating layer has a thickness greater than 1 um.
6. The multi-chip normal mounting reset wafer level packaging method as claimed in claim 1, wherein the metal of the metal interconnection line is any one of Al, Cu, Ti, Ni, Sn and alloy thereof; the thickness of the chip front plastic package layer 162 is more than 1 um; the thickness of the rewiring layer 19 is more than 1 um; the material is any one of Al, Cu, Ti, Ni and Sn and alloy thereof.
7. A multi-chip forward-mounting reset wafer-level packaging structure is characterized by comprising a multi-chip reset layout, wherein the front surface of a chip is upward and comprises an electrode and a key function area;
the front surface of the chip is adhered with a first insulating layer 15, and partial electrodes and all key functional areas of the chip are exposed; a plastic packaging layer 161 is integrally packaged on the back surface and the side wall of the chip; a second insulating layer 17 is attached to the first insulating layer 15, and the cutting channels and partial electrode areas are exposed, so that a sealed cavity structure is formed by the key function area, the first insulating layer 15 and the second insulating layer 17; a metal interconnection line 18 is arranged in a through hole formed by the first insulating layer 15 and the second insulating layer 17, and the height of the metal interconnection line 18 is higher than the surface of the second insulating layer; the front surface of the chip is pasted with a plastic packaging layer 162, and the plastic packaging layer 162 encapsulates the electrode, the surface of the second insulating layer 17 and the side wall; and is communicated with the plastic packaging layer 161 on the back side at the cutting path; the encapsulated metal interconnection line 18 leaks out of the plastic packaging layer 162 on the front surface of the thinned chip, and at the moment, the metal interconnection line 18 and the upper surface of the plastic packaging layer 162 are on the same plane; a rewiring layer 19 is arranged on the plastic packaging layer 162 and the metal interconnection line 18; and cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
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| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN105390429A (en) * | 2015-11-05 | 2016-03-09 | 南通富士通微电子股份有限公司 | Packaging method |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN209880659U (en) * | 2019-06-06 | 2019-12-31 | 厦门云天半导体科技有限公司 | Wafer-level packaging structure of filter |
| CN111599702A (en) * | 2019-04-24 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Manufacturing method of fan-out type chip packaging structure |
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- 2021-12-24 CN CN202111599166.6A patent/CN114361051B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN105390429A (en) * | 2015-11-05 | 2016-03-09 | 南通富士通微电子股份有限公司 | Packaging method |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN111599702A (en) * | 2019-04-24 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Manufacturing method of fan-out type chip packaging structure |
| CN209880659U (en) * | 2019-06-06 | 2019-12-31 | 厦门云天半导体科技有限公司 | Wafer-level packaging structure of filter |
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