CN114361050A - Multi-chip flip reset wafer level packaging structure and method - Google Patents
Multi-chip flip reset wafer level packaging structure and method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000004033 plastic Substances 0.000 claims abstract description 17
- 229920003023 plastic Polymers 0.000 claims abstract description 17
- 238000005520 cutting process Methods 0.000 claims abstract description 13
- 238000010030 laminating Methods 0.000 claims abstract description 11
- 238000005538 encapsulation Methods 0.000 claims abstract description 10
- 238000012858 packaging process Methods 0.000 claims abstract description 8
- 238000003466 welding Methods 0.000 claims abstract description 8
- 238000007789 sealing Methods 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 93
- 239000002184 metal Substances 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000007888 film coating Substances 0.000 claims description 6
- 238000009501 film coating Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000001746 injection moulding Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- 239000005416 organic matter Substances 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000005245 sintering Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229920000307 polymer substrate Polymers 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a multi-chip flip reset wafer level packaging structure and a method, wherein the structure comprises the following steps: a multi-chip resetting layout, wherein different types of chips 10 are placed on the substrate 02 pasted with the temporary bonding film 01 by adopting a chip pasting process, the back surfaces of the chips are upward, and the front surfaces of the chips are pasted on the temporary bonding film 01 on the substrate; the front surface of the chip comprises electrodes 11 and a key function area 12, and a plurality of groups are regularly arranged on the substrate 02 on the basis of arranging the whole substrate 02; manufacturing a chip back protective film layer, namely manufacturing a first organic film layer 15 on the back of the chip on the substrate 02 by using a laminating and film covering process, and sealing each chip by using the organic film layer 15 to prevent materials from permeating in the subsequent plastic package; and finally, completing the packaging process after the salient points are manufactured, and subsequently cutting the chips into single chips according to the size of each group of chips to perform subsequent PCB welding. The multi-surface encapsulation of the invention can realize side surface encapsulation even if the chip distance is smaller, thereby enhancing the reliability of the chip.
Description
Technical Field
The invention belongs to the field of semiconductors, in particular to a wafer-level packaging method for a filter, and relates to different chip resetting and multi-chip packaging technologies for a filter wafer.
Background
After the chips are respectively manufactured with the bumps in the current packaging process, the chips are pasted on the substrate by using an inverted process, and then a film is coated to form a cavity; the patent with application number 201621225249.3 discloses a multi-chip module packaging structure including a film body acoustic wave device bare chip, which comprises a substrate and bare chips, wherein the bare chips comprise the film body acoustic wave device bare chip and other functional bare chips, and corresponding electrodes are arranged on the substrate and all the bare chips; the patent with application number 202020151459.2, the utility model discloses a modular packaging structure, through the at least one anti-overflow subassembly, improves the phenomenon that the colloid of the molding material is easy to diffuse outward before curing in the prior art, which affects the welding effect of the adjacent subassembly; and no additional mold is needed for packaging. The above patents have more or less problems of complex process and high cost; and the anti-overflow assembly is preset on the packaging substrate, so that the chip spacing is larger, and the whole packaging volume is larger.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a multi-chip flip reset wafer level packaging method which simplifies the packaging process and improves the packaging efficiency and the yield.
The technical scheme of the invention comprises the following steps:
step 1, resetting layout of multiple chips, namely placing different types of chips 10 on a substrate 02 pasted with a temporary bonding film 01 by adopting a chip pasting process, wherein the back surfaces of the chips are upward, and the front surfaces of the chips are pasted on the temporary bonding film 01 on the substrate; the front surface of each chip comprises an electrode 11 and a key function area 12, a plurality of groups are regularly arranged on the substrate 02, each group comprises a plurality of chips, and the whole substrate 02 is arranged fully;
step 2, manufacturing a chip back protective film layer, namely manufacturing a first organic film layer 15 on the back of the chip on the substrate 02 by using a laminating and laminating process, and sealing each chip by using the organic film layer 15 to prevent materials from permeating in the subsequent plastic package;
step 3, encapsulating the whole back of the chip, and completely encapsulating the back of the chip by using a plastic encapsulation layer 16 by using an injection molding process;
step 4, removing the substrate 02 and the temporary bonding film 01 on the front surface of the chip, and removing the substrate 02 and the temporary bonding film 01 by using a temporary bonding removal process to leak out of the front surface of the chip 10, so as to expose the electrode 11 and the key functional region 12;
step 5, manufacturing a first insulating layer 17 on the front surface of the chip, and manufacturing a first insulating layer 17 protection layer on the front surface of the chip by using processes such as coating, laminating and the like; patterning the first insulating layer by using a photoetching process to expose the electrode 11 and the key functional region 12 of the chip;
step 6, manufacturing a second insulating layer 18, attaching the second insulating layer 18 on the first insulating layer 17 by using a lamination film coating process, and performing patterning treatment on a protective layer manufactured by using the lamination film coating process by using a photoetching process to expose the position of the electrode 11 and protect and seal the position of the key functional region 12; or bonding a second insulating layer 18 on the first insulating layer 17 by using a bonding process, and exposing the position of the electrode 11 by using an etching or laser perforation process, wherein the position of the key functional region 12 is not opened and is protected by sealing;
step 7, manufacturing a metal interconnection line 19, namely manufacturing the metal interconnection line 19 on the electrode 11, namely in a through hole formed by the first insulating layer 17 and the second insulating layer 18, by using PVD (physical vapor deposition), electroplating, photoetching and etching processes;
step 8, manufacturing bumps 20 on the front surface of the chip, and manufacturing bumps on a chip metal interconnection line by using printing, electroplating and metal sintering processes;
and 9, finishing the packaging process after the salient points are manufactured, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
Further, the critical function region 12 includes an IDT region of the surface acoustic wave filter and a cavity region of the bulk acoustic wave filter.
Further, the thickness of the organic film layer 15 is larger than 1 um.
Further, the thickness of the plastic package layer 16 is larger than 1um, and the material is any one of epoxy resin, polymer and plastic organic material.
Furthermore, the thickness of the first layer of insulating layer is larger than 1um, the thickness of the second layer of insulating layer is larger than 1um, and the material is any one of organic matter, Si and glass and ceramic cover plate materials.
Furthermore, the metal of the metal interconnection line is any one of Al, Cu, Ti, Ni and Sn, or an alloy thereof, and the height of the metal interconnection line is more than 1um of the second insulating layer.
Furthermore, the bump material is any one of Au, Sn, Cu and Ag simple substances or alloy thereof.
And further, the method also comprises the step of integrally encapsulating the front surface of the chip, wherein the front surface of the chip is also encapsulated by adopting a plastic encapsulation process, and all the chips including the metal interconnection lines are encapsulated.
Further, the chip metal interconnection line leakage process is characterized in that the chip metal interconnection line leakage process is used for thinning the front surface of the chip to form the leaked metal interconnection line, and if no special requirement is imposed on the thickness of the chip, the chip can be cut according to each group after the step is finished to finish chip processing.
Further, if the chip is required to be ultra-thin packaged, the back of the chip can be thinned, and the thickness of the packaging body is integrally reduced; and after thinning, coating a layer of packaging material on the back of the chip, realizing integral packaging again, and completing packaging after cutting.
The invention discloses a multi-chip flip reset wafer level packaging structure which comprises a multi-chip reset layout, wherein the back surface of a chip is arranged upwards, and the front surface of the chip comprises an electrode 11 and a key function area 12; the back of the chip is adhered with a first organic film layer 15, the organic film layer 15 seals each chip, and the back of the chip is encapsulated with a plastic packaging layer 16; a first insulating layer 17 protective layer is attached to the front surface of the chip; attaching a second insulating layer 18 on the first insulating layer 17 to expose the electrode 11 and protect and seal the critical function region 12; a metal interconnection line 19 is arranged in a through hole formed by the first insulating layer 17 and the second insulating layer 18; and encapsulating the front surface of the chip, wrapping all the chips including metal interconnection lines, and cutting the chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
The beneficial effects of the invention include: the multiple chips are flexibly combined and packaged, damaged chips can be screened, the packaging process is simplified, and the packaging efficiency and yield are improved; the packaging process has no additional substrate and protection device, and the protection layer is processed on the chip, so that the packaging volume of the chip is further reduced; and the multi-surface packaging can realize the side packaging even if the chip distance is smaller, thereby enhancing the reliability of the chip.
Drawings
FIG. 1 is a schematic diagram of a multi-chip reset layout according to the present invention;
FIG. 2 is a schematic view of a chip backside protection film according to the present invention;
FIG. 3 is a schematic diagram of the back side of a chip of the present invention;
fig. 4 is a schematic diagram of the substrate 02 and the temporary bonding film 01 with the front surface of the chip removed according to the present invention;
FIG. 5 is a schematic diagram of the fabrication of a first insulating layer 17 on the front surface of the chip according to the present invention;
FIG. 6 is a schematic diagram of the fabrication of a second insulating layer 18 according to the present invention;
FIG. 7 is a schematic diagram of the fabrication of metal interconnect lines 19 according to the present invention;
FIG. 8 is a schematic diagram of the fabrication of bumps 20 on the front side of the chip according to the present invention;
FIG. 9 is a schematic diagram of the fabrication of metal interconnects on the electrodes of a chip according to the present invention;
FIG. 10 is a schematic diagram of the front side of the chip of the present invention;
FIG. 11 is a schematic diagram of a die metal interconnect line breakout process of the present invention;
FIG. 12 is a schematic diagram of thinning the backside of a chip according to the present invention.
Detailed Description
1. A multi-chip reset layout, in which different types of chips (the number of chips can be flexibly matched, for example, 3 chips 101, 102, and 103) are placed on a substrate 02 to which a temporary bonding film 01 is attached by using a chip mounting process, the back surface of each chip is upward, and the front surface of each chip is attached to the temporary bonding film 01 on the substrate; the front surface of the chip contains electrodes 11 (each chip contains such electrodes), critical function regions 12 (e.g., IDT region of surface acoustic wave filter, resonator region of bulk acoustic wave filter), and the like. Taking the 3 chips as one group as an example, a plurality of groups are regularly arranged on the substrate 02, so as to fill the whole substrate 02. As shown in fig. 1.
2. Manufacturing a chip back protective film layer, namely manufacturing a first organic film layer 15 on the back of the chip on the substrate 02 by using a laminating and film covering process, and sealing each chip by using the organic film layer 15 to prevent materials from permeating in the subsequent plastic package; the thickness of the organic film layer 15 is larger than 1 um. As shown in fig. 2.
3. The back of the chip is encapsulated on the whole surface, and the back of the chip is completely encapsulated by a plastic encapsulation layer 16 by using an injection molding process. The thickness of the plastic package layer 16 is larger than 1um, and the material can be epoxy resin, polymer, plastic and other organic materials. As shown in fig. 3.
4. And removing the substrate 02 and the temporary bonding film 01 on the front surface of the chip, and removing the substrate 02 and the temporary bonding film 01 by using a temporary bonding removal process to leak out of the front surface of the chip, so as to expose the electrode 11 and the key functional region 12. As shown in fig. 4.
5. Manufacturing a first insulating layer 17 on the front surface of the chip, and manufacturing a first insulating layer 17 protective layer on the front surface of the chip by using processes such as coating, laminating and film covering; and patterning the first insulating layer by using a photoetching process to expose the electrode 11, the key functional region 12 and other positions of the chip. The thickness of the first insulating layer is larger than 1 um. As shown in fig. 5.
6. And manufacturing a second insulating layer 18, namely attaching the second insulating layer 18 on the first insulating layer 17 by using a laminating film coating process, and performing patterning treatment on a protective layer manufactured by using the laminating film coating process by using a photoetching process to expose the position of the electrode 11 and protect and seal the position of the key functional region 12. Or bonding the second insulating layer 18 on the first insulating layer 17 by using a bonding process, and exposing the electrode 11 by using etching or laser perforation, wherein the position of the key functional region 12 is not opened and is protected by sealing. The thickness of the second insulating layer is larger than 1um, and the material can be organic matter, Si, glass, ceramic cover plate and other materials, and is not limited herein. As shown in fig. 6.
7. The metal interconnection line 19 is formed by using PVD, electroplating, photolithography, etching, etc. to form the metal interconnection line 19 in the via hole formed by the first insulating layer 17 and the second insulating layer 18 on the electrode 11. The metal of the metal interconnection line may be Al, Cu, Ti, Ni, Sn metal, an alloy thereof, and the like, and is not limited herein. (see fig. 7)
8. The bumps 20 on the front surface of the chip are made by using processes such as printing, electroplating, metal sintering and the like, and the bumps on the metal interconnection line of the chip are made of a single substance or an alloy such as Au, Sn, Cu, Ag and the like, which is not limited herein. (see fig. 8)
9. And finishing the packaging process after the salient points are manufactured, and subsequently cutting the chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
Firstly, for products with higher requirements on chip tightness and reliability, etching is carried out to carry out double-sided encapsulation process, and the specific implementation mode is as follows:
and repeating the process from the step 7 to the process of the step 7, manufacturing the metal interconnection line on the electrode of the chip in the step 7, and manufacturing the metal interconnection line on the electrode by adopting PVD (physical vapor deposition), electroplating, photoetching and etching processes, wherein the height of the metal interconnection line is more than 1um of the second insulating layer. (as in FIG. 9)
And (3) integrally encapsulating the front surface of the chip, and encapsulating the front surface of the chip by adopting a plastic encapsulation process to encapsulate all the chips including the metal interconnection lines.
(see fig. 10)
And (3) a chip metal interconnection line leakage process, namely thinning the front surface of the chip to leak the metal interconnection line by adopting a thinning process, and if no special requirement is imposed on the thickness of the chip, cutting according to each group after the step is finished to finish the chip processing. (see fig. 11)
If the chip is required to be packaged in an ultrathin way, the back of the chip can be thinned, and the thickness of the packaging body is integrally reduced; after thinning, coating a layer of packaging material on the back of the chip, and realizing integral packaging again; and finishing packaging after cutting. (see fig. 12)
The invention discloses a multi-chip flip reset wafer level packaging structure which comprises a multi-chip reset layout, wherein the back surface of a chip is arranged upwards, and the front surface of the chip comprises an electrode 11 and a key function area 12; the back of the chip is adhered with a first organic film layer 15, the organic film layer 15 seals each chip, and the back of the chip is encapsulated with a plastic packaging layer 16; a first insulating layer 17 protective layer is attached to the front surface of the chip; attaching a second insulating layer 18 on the first insulating layer 17 to expose the electrode 11 and protect and seal the critical function region 12; a metal interconnection line 19 is arranged in a through hole formed by the first insulating layer 17 and the second insulating layer 18; and encapsulating the front surface of the chip, wrapping all the chips including metal interconnection lines, and cutting the chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (9)
1. A multi-chip flip-chip reset wafer level packaging method is characterized by comprising the following steps:
step 1, resetting layout of multiple chips, namely placing different types of chips 10 on a substrate 02 pasted with a temporary bonding film 01 by adopting a chip pasting process, wherein the back surfaces of the chips are upward, and the front surfaces of the chips are pasted on the temporary bonding film 01 on the substrate; the front surface of each chip comprises an electrode 11 and a key function area 12, a plurality of groups are regularly arranged on the substrate 02, each group comprises a plurality of chips, and the whole substrate 02 is arranged fully;
step 2, manufacturing a chip back protective film layer, namely manufacturing a first organic film layer 15 on the back of the chip on the substrate 02 by using a laminating and laminating process, and sealing each chip by using the organic film layer 15 to prevent materials from permeating in the subsequent plastic package;
step 3, encapsulating the whole back of the chip, and completely encapsulating the back of the chip by using a plastic encapsulation layer 16 by using an injection molding process;
step 4, removing the substrate 02 and the temporary bonding film 01 on the front surface of the chip, and removing the substrate 02 and the temporary bonding film 01 by using a temporary bonding removal process to leak out of the front surface of the chip 10, so as to expose the electrode 11 and the key functional region 12;
step 5, manufacturing a first insulating layer 17 on the front surface of the chip, and manufacturing a first insulating layer 17 protection layer on the front surface of the chip by using processes such as coating, laminating and the like; patterning the first insulating layer by using a photoetching process to expose the electrode 11 and the key functional region 12 of the chip;
step 6, manufacturing a second insulating layer 18, attaching the second insulating layer 18 on the first insulating layer 17 by using a lamination film coating process, and performing patterning treatment on a protective layer manufactured by using the lamination film coating process by using a photoetching process to expose the position of the electrode 11 and protect and seal the position of the key functional region 12; or bonding a second insulating layer 18 on the first insulating layer 17 by using a bonding process, and exposing the position of the electrode 11 by using an etching or laser perforation process, wherein the position of the key functional region 12 is not opened and is protected by sealing;
step 7, manufacturing a metal interconnection line 19, namely manufacturing the metal interconnection line 19 on the electrode 11, namely in a through hole formed by the first insulating layer 17 and the second insulating layer 18, by using PVD (physical vapor deposition), electroplating, photoetching and etching processes;
step 8, manufacturing bumps 20 on the front surface of the chip, and manufacturing bumps on a chip metal interconnection line by using printing, electroplating and metal sintering processes;
and 9, finishing the packaging process after the salient points are manufactured, and subsequently cutting each group of chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
2. The method of claim 1, wherein the critical function area 12 comprises an IDT area of a SAW filter and a cavity area of a bulk acoustic wave filter.
3. The method of claim 1, wherein the organic film 15 is thicker than 1 um; the thickness of the plastic packaging layer 16 is more than 1um, and the material is any one of epoxy resin, polymer and plastic organic material; the thickness of the first layer of insulating layer is larger than 1um, the thickness of the second layer of insulating layer is larger than 1um, and the material is any one of organic matter, Si, glass and ceramic cover plate material; the metal of the metal interconnection line is any one of Al, Cu, Ti, Ni and Sn or an alloy thereof, and the height of the metal interconnection line is more than 1um of the second insulating layer; the bump material is any one of Au, Sn, Cu and Ag simple substances or alloy thereof.
4. The method as claimed in claim 1, further comprising encapsulating the entire front surface of the chip, wherein the front surface of the chip is encapsulated by a plastic encapsulation process, and all the chips are encapsulated by metal interconnects.
5. The method as claimed in claim 4, wherein the step of leaking the metal interconnection lines of the chip comprises the step of thinning the leaked metal interconnection lines on the front surface of the chip by using a thinning process, and if no special requirement is imposed on the thickness of the chip, the step of processing the chip can be completed by cutting each group.
6. The method of claim 4, further comprising thinning the backside of the chip to reduce the overall package thickness if the chip is required to be ultra-thin; and after thinning, coating a layer of packaging material on the back of the chip, realizing integral packaging again, and completing packaging after cutting.
7. A multi-chip flip reset wafer level packaging structure is characterized by comprising a multi-chip reset layout, wherein the back of a chip is arranged upwards, and the front of the chip comprises an electrode 11 and a key function area 12;
the back of the chip is adhered with a first organic film layer 15, the organic film layer 15 seals each chip, and the back of the chip is encapsulated with a plastic packaging layer 16; a first insulating layer 17 protective layer is attached to the front surface of the chip; attaching a second insulating layer 18 on the first insulating layer 17 to expose the electrode 11 and protect and seal the critical function region 12; a metal interconnection line 19 is arranged in a through hole formed by the first insulating layer 17 and the second insulating layer 18; and encapsulating the front surface of the chip, wrapping all the chips including metal interconnection lines, and cutting the chips into single chips according to the size of each group of chips to perform subsequent PCB welding.
8. The multi-chip flip-chip re-configurable wafer-level package structure of claim 7, further comprising thinning the front side of the chip to expose the metal interconnects.
9. The multi-chip flip-chip reset wafer-level packaging structure of claim 7, further comprising thinning the back surface of the chip to reduce the thickness of the package body as a whole, and coating a layer of encapsulating material on the back surface of the chip after thinning to realize integral encapsulation again; and finishing packaging after cutting.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
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