KR20130054115A - Semiconductor packages and methods of packaging semiconductor devices - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for packaging a semiconductor device are provided to increase heat dissipation by using a die stack having a first and a second surface. CONSTITUTION: A first and a second surface(111,112) are formed in a die(150). A conductive pad is formed in the second surface of the die. A permanent carrier is provided. The die is adhered to the permanent carrier. A cap having a first surface(190a) and a second surface(190b) is formed.

Description

Semiconductor package and semiconductor device packaging method {SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES}

Cross-reference to related application

This application is filed on November 15, 2010, and claims priority to US Provisional Application No. 61 / 413,577, entitled "Built-in Die Fan-out Packaging Structure and Method," 2011 11 Some serial applications of US patent application Ser. No. 13 / 295,097, filed May 14, which are incorporated herein for all purposes.

Industrial fan-out solutions include high capital investment costs for new wafer relocation layers (RDLs) and bumping facilities. Moreover, new equipment and retrofit kits for compression molding systems are required to enable wafer handling in pick and place systems for fan-out solutions.

It is desirable to improve the fan-out semiconductor packaging process that can utilize existing tools and processes associated with current wafer-level fan-out solutions to minimize or avoid the aforementioned costs. It is also desirable to produce fan-out semiconductor packages with very thin package profiles, higher I / O counts for wafer level chip scale packaging, multi-level redistribution layers, and possible systems in the field of packaging. Moreover, it is also desirable to produce semiconductor packages with enhanced heat dissipation capability.

Embodiments generally relate to semiconductor packaging. In one embodiment, a method for forming a semiconductor package exists. The method includes providing one or more die having a first surface and a second surface. The second surface of the die includes a plurality of conductive pads. The method also includes providing a permanent carrier and attaching one or more dies to the permanent carrier. The first surface of the one or more dies faces the support carrier. A cap having a first surface and a second surface is formed to encapsulate one or more dies. The first surface of the cap is in contact with the permanent carrier and the second surface of the cap is disposed in a different plane than the second surface of the die.

In yet another embodiment, a method of forming a semiconductor package is disclosed. The method includes providing one or more die stacks having a first surface and a second surface. The second surface of the die stack includes a plurality of conductive pads. A permanent carrier is provided and one or more die stacks are attached to the permanent carrier. The first surface of the one or more die stacks faces the permanent carrier. A cap having a first surface and a second surface is formed to encapsulate one or more die stacks. The second surface of the cap is disposed in a plane different from the second surface of the die stack. The first surface of the cap is in contact with the permanent carrier and the second surface of the cap is disposed in a different plane than the second surface of the die.

In accordance with other advantages and features of the disclosed subject matter, these embodiments will become apparent by reference to the following detailed description and the accompanying drawings. Moreover, it is to be understood that the features of the various embodiments disclosed herein are not mutually exclusive and may exist in various combinations and modifications.

In the drawings, like reference numerals generally refer to the same parts throughout the different views. In addition, the drawings are not necessarily drawn to scale, but instead highlighted generally in describing the principles of the invention. In the following detailed description, various embodiments of the invention are described with reference to the following figures.
1 and 2 show various embodiments of a semiconductor package,
3A-3H and 4A-4C show various embodiments of a method for forming a semiconductor package.

Embodiments relate to a semiconductor package and a method for forming a semiconductor package. The package is used to package one or more semiconductor dies or chips. For the case of one or more dies, the dies may be arranged in a planar arrangement, a vertical arrangement, or a combination thereof. Dies may include, for example, memory devices, logic devices, communication devices, optoelectronic devices, digital signal processors (DSPs), microcontrollers, system-on-chips (SOCs), as well as other types of devices or combinations thereof. Can be. Such packages can be integrated into equipment such as electronics or phones, computers, as well as mobile and mobile smart products. Integration of packages into other types of products may also be useful.

1 shows a simplified cross-sectional view of one embodiment of a semiconductor package 100 showing portion A 'in more detail. The package includes a built-up or integrated wiring substrate 110. The wiring substrate includes first and second major surfaces 111 and 112. The first major surface may for example be referred to as the top side and the second major surface may for example be referred to as the bottom side. Other names for the surfaces may also be useful. In one embodiment, the first major surface of the wiring substrate includes first and second regions 111a and 111b. The first region is for example a die or chip region, and die 150 is mounted on the die or chip region and the second region is for example a non-die region. In one embodiment, the non-die region surrounds the die region. The die region may be disposed, for example, in the central portion where the die 150 is mounted and in the non-die region 111b outside of the die attach region. The die regions may be disposed concentrically in the periphery of the wiring substrate, for example. Other configurations of die and non-die regions may also be useful.

The die may be a semiconductor die or a chip. Dies are of various types, including, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and programmable read-on memory (PROM) and flash memory. Any integrated circuit (IC) such as memory devices, optoelectronic devices, logic devices, communication devices, digital signal processors (DSPs), microcontrollers, system-on-chips, as well as other types of devices It may be of type.

The die includes a first surface 150a and a second major surface 150b. The first surface is for example the inactive or backside of the die and the second surface is the active surface of the die. Other names of the surfaces of the die may also be useful. The active surface of the die is in contact with the die area of the wiring substrate. The active surface includes an opening in a final passivation layer (not shown), for example to expose conductive die pads 155. The surface of the conductive die pad, for example, the can on the second main surface (150b) is substantially the same one plane of the die. It may also be useful to provide a surface of a conductive pad that is not coplanar with the second major surface of the die. The die pad provides a connection to the circuit of the die. The die pad is formed of a conductive material such as, for example, copper, aluminum, gold, nickel or alloys thereof. Other types of conductive materials may also be used for the die pads. The pattern of the die pads may be one or more rows arranged at or centered on opposite sides of the active surface. Other pad patterns such as grid or matrix arrangements may also be useful.

In one embodiment, the wiring substrate comprises a multi-layer substrate. Multi-layer substrates include first and second insulating substrate layers 113 and 117 in one embodiment. The first layer includes a first surface 113a and a second surface 113b. The first surface may be referred to as the top surface and the second surface may be referred to as the bottom surface. Other names for the surfaces of the first layer may also be useful. The first surface is in contact with the die. In one embodiment, the first layer includes a through via contact 130 extending from the first surface to the second surface of the first layer. The via contact is formed of a conductive material. For example, the via contact may be formed of copper, aluminum, gold, nickel or an alloy thereof. Other types of conductive materials may also be useful. The via contacts are insulated from each other by a first insulating substrate layer.

Conductive trace 140 is disposed on the second surface of the first insulating substrate layer. The conductive traces are formed of a conductive material, such as copper, aluminum, gold, nickel or alloys thereof. Other types of conductive materials may also be useful. The conductive traces are coupled to substrate via contacts forming interconnects that are coupled to die pads of the same die. The conductive traces can include conductive pads 168.

The first substrate layer may be a dielectric layer. The dielectric layer is disposed on the second surface of the die, for example. Other types of first substrate layers may also be useful. In another embodiment, the substrate layer may be patterned to provide vias in which substrate via contacts are disposed. The formation of vias in the first substrate layer may be accomplished by any suitable technique including laser and mechanical drilling, but is not limited to laser and mechanical drilling.

The second insulating layer layer includes a first surface 117a and a second surface 117b. The first surface may be referred to as the top surface and the second surface may be referred to as the bottom surface. Other names for the surface of the second insulating substrate layer may also be useful. The first surface of the second insulating layer is disposed on the conductive trace and the second surface of the first substrate layer: the second surface serves as the bottom surface of the package. The second substrate layer insulates the conductive traces from each other. The second substrate layer may be formed of a solder mask or other dielectric material. Other types of second substrate layers may also be useful.

An opening is provided in the second substrate layer where the package contact 170 is disposed. The opening exposes the conductive pad, for example, on the conductive trace. The pattern of openings can be designed to provide a desired package contact pattern. For example, contact openings may be disposed in the grid pattern to form a BGA type package. Other contact opening patterns may also be useful. The conductive pad is for example on the same plane as the conductive trace. In other embodiments, the conductive pad can include a protruding conductive pad. The conductive pad may be further covered with a surface protective material such as OSP or metal coating or plating.

The outer package contact 170 is disposed on the second substrate layer in the opening. Package contacts are, for example, spherical structures or balls. The package contact protrudes from the bottom surface of the second substrate layer. It may also be useful to provide a package contact that does not protrude from the bottom surface of the second substrate layer, such as a solder land. The package contact is formed of a conductive material. Package contacts may be formed by soldering in one embodiment. Various types of solder can be used to form package contacts. For example, the solder can be lead-based or non-lead-based soldering. Other types of conductive materials can also be used to form package contacts.

In other embodiments, package contacts may include other types of package contacts, such as copper pillers or gold stud bumps (not shown). Copper fillers are excellent when they do not collide after reflow. Thus, the copper filler can enable the production of semiconductor packages with a much-titled pitch and a more uniform standoff height. On the other hand, gold stud bumps can sometimes be used in conjunction with effervescent conductive adhesives and thermal compression welding methods to achieve a title pitch. This is excellent when an IC chip originally designed as a peripheral bond pad for the purpose of wire bonding can be used as flip chips. Other suitable types of package contacts can also be used.

Package contacts provide external access to the die via conductive traces, substrate via contacts, and die pads. The package can be electrically coupled to an external device (not shown), such as a circuit board, by the package contact.

In one embodiment, the built-up wiring substrate is an integrated package substrate. As discussed above, the package substrate is in direct contact with the die in the die region, and the conductive trace and via contacts are coupled to the die pad of the same die. In one embodiment, the integrated package substrate includes via contacts coupled directly to the die pads of the same die. The wiring substrate functions as a fan out redistribution structure for the die, enabling redistributed fan-out external package connections.

As mentioned above, the first substrate layer is a single layer. In another embodiment, the first substrate layer 113 may include a plurality of second sub-layers. For example, the first substrate layer may include first and second first sub-layers. It may also be useful to provide a first substrate layer with other numbers of first sublayers. The first and second first sub-layers may comprise the same material, for example. It may also be useful to provide a first sub-layer having a different material than the second sub-layer. The first sub-layer is similar to the first substrate layer. For example, the first sub-layer includes first and second surfaces and the substrate via contact extends through conductive traces and surfaces on the second surface. The first surface of the sub-layer is in contact with the die or the second surface of the adjacent first sub-layer. This creates a layered stack with a first substrate layer or multiple conductive layers. Providing a first substrate layer having multiple built-up conductive layers may facilitate packaging for dies with higher density die contacts and package contacts.

In one embodiment, the cap 190 is formed over the second region 111b of the first major surface 111 of the package substrate. The cap functions to protect the die from the environment. For example, the cap can protect the die from moisture. The cap is formed, for example, of encapsulation material. The encapsulation material can be, for example, a molding epoxy resin material. Other types of encapsulation materials may also be useful.

The cap includes first and second major surfaces 190a-190b. The first surface may for example be a top surface and the second surface may be a bottom surface. Other names for the surface of the cap may also be useful. In one embodiment, the cap at least surrounds the die. For example, bottom surface 190b is disposed on the package substrate on the non-die region of the package substrate. The cap protects the die by surrounding the die.

In one embodiment, the non-die region is disposed in a different plane than the die region. For example, as shown by portion A ', the die and non-die regions form a step 187 in the package substrate. In one embodiment, the die region is disposed or recessed into the encapsulation material with respect to the first major surface 190a of the cap. For example, the die region 111a has a greater distance from the bottom 117b of the package substrate than the non-die region 111b. The non-die region is for example over the conductive die pad or die region with respect to the first major surface 190a of the cap. Referring to FIG. 1A, the second surface of the die is disposed in a plane different from the second surface of the cap. Providing the bottom surface of the cap in a different plane than the die advantageously relieves mechanical stress on the die by thermal mismatch of the package material.

In one embodiment, the cap does not cover the first or rear surface of the die, as shown in FIG. 1. For example, the top surface 190a of the cap is approximately coplanar with the back surface 150a of the die. Alternatively, the top surface of the cap need not be coplanar with the back surface of the die. For example, the first surface 190a of the cap is on the back surface 150a of the die, depending on the thickness of the adhesive layer disposed on the back surface of the die.

In one embodiment, the carrier 185 is permanently disposed on the rear face 150a of the die and the top or first surface 190a of the cap. For example, the carrier remains as part of the packaged die. The carrier comprises a first and a second major surface. The first major surface 180a For example, the top surface of the carrier and the second major surface 180b are the bottom surface of the carrier. Other designs for the surface of the carrier can also be used. In one embodiment, the second surface of the carrier is in contact with at least the first surface of the cap, while the first surface of the carrier is exposed. The second surface of the carrier substantially covers the entire first surfaces of the cap and die, for example.

In one embodiment, adhesive 175 is provided on the second surface of the carrier. The adhesive, for example, bonds at least the carrier and the die. In one embodiment, an adhesive is provided between at least the second surface of the carrier and the first surface of the die. In another embodiment, an adhesive may also be provided between the second surface of the carrier and the first surface of the cap and die. Adhesives include, for example, films, pastes, liquids or thermally conductive adhesives. Other suitable types of adhesives may also be used that facilitate at least bonding between the carrier and the die. The adhesive may comprise a suitable thickness such that it can at least permanently bond the die and the carrier during processing.

As shown in FIG. 1, the carrier almost covers the entire first surfaces of the die and the cap. In one embodiment, the carrier can be sufficiently rigid to function as a permanent carrier or permanent support for holding the die or die stack during assembly. This will be described in detail later. Alternatively or additionally, the carrier can also function as a thermal conductor to dissipate heat from the die or die stack of the semiconductor package. By way of non-limiting example, the carrier may comprise a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Other suitable types of materials may also be used to form the carrier. The semiconductor package may also include additional heat sinks or heat spreaders to reinforce heat dissipation. For example, a thermal sprayer (not shown) may be attached over the carrier to further improve heat dissipation.

2 shows another embodiment of a semiconductor package 200. The semiconductor package is similar to that shown in FIG. As such, common elements may or may not be described in detail.

The semiconductor package 200 includes a die stack 210 mounted on the die region 111a of the wiring substrate 110. The die stack comprises n dies, where n is at least two. The bottom die may for example be referred to as first (eg n = 1) and the top die is n. It may also be useful to refer to the die of the die stack using other conventions. The die stack may be formed by, for example, any suitable type of die stacking method. As shown, the die stack includes first and second die 250 ₁ and 250 ₂ . The second die 250 ₂ is attached onto the first die 250 ₁ , and the first die is attached to the die region 111a of the wiring substrate 110. The die used for the die stack may be a TSV or non-TSV die. In one embodiment, both the top die and the bottom die can be TSV dies. In another embodiment, the bottom die may comprise a TSV die and the top die may comprise a non-TSV die. Non-TSV dies may include, for example, bonded wires, direct connections, flip chip dies, and the like. For die stacks with more than two dies, the bottom die (bottom and middle die except the top die) is usually a TSV die while the top die is a non-TSV die. Other configurations or types of die in the die stack may also be useful.

The TSV die includes first and second major surfaces 250a-b. The first surface includes a first die contact 233 and the second major surface includes a second die contact 235. The die contact has, for example, an upper surface that is coplanar with the first major surface 250a and the second major surface 250b of the die. It may also be useful to provide a surface of a contact pad that is not coplanar with the surfaces of the die. Other configurations of die contacts or die contact pads may also be useful. The first and second die contacts are interconnected by through via contacts 230. Other configurations of TSV dies may also be useful. Via contacts and contact pads are formed, for example, of conductive material. The conductive material may include copper for example. Other types of conductive materials can also be used for via contacts and contact pads.

As shown, the second die contact 235 of the bottom die is mounted onto the die region 111a of the wiring substrate. The first die contact 233 is coincident with the upper die of the die stack. In one embodiment, a die attach film or underfill 217 may be provided in a cavity formed between the dies to facilitate stacking and to conduct conductive dies of the first die contacts 233 and the second die of the first die. To protect the bonding contact 240 coupling the pad 155. Redistribution layers may also be provided. Similar to FIG. 1, the die and non-die regions of semiconductor package 200 form step 187 in the package substrate. For the case of two or more dies used to form the die stack, the bottom and middle dies may include TSV dies. It may also be useful to provide a bottom and intermediate die with non-TSV dies. The second die contact of the upper n ^th + 1 die is connected to the first die contact of the lower n ^th die.

Cap 190 is provided to encapsulate die stack 210. In one embodiment, the cap surrounds at least the die stack. For example, the cap surrounds and protects at least the sides of the first and second die 250 ₁ , 250 ₂ of the die stack. Similar to FIG. 1, the die region is disposed or recessed into the capsule material relative to the first major surface 190a of the cap 190. In one embodiment, the first surface 190a of the cap is substantially coplanar with the first surface 150a of the second end of the die stack. The cap does not cover, for example, the first surface or the back side of the second die of the die stack. Alternatively, the first surface of the cap need not be coplanar with the first surface of the second die of the die stack. For example, the first surface of the cap is disposed above the rear face of the second die and disposed above the rear face of the second die of the die stack, depending on the thickness of the adhesive layer therewith, as described below. The bottom surface of the cap is disposed on the non-die area of the wiring substrate.

In one embodiment, a carrier 185, similar to the carrier described in FIG. 1, is permanently disposed above the second die of the die stack and the first surface of the cap. The second surface 180b of the carrier contacts at least the first surface 190a of the cap, while the first surface 185a of the carrier is exposed. The second surface of the carrier substantially covers the entire first surfaces of the cap and die, for example. Adhesive 175, similar to the adhesive as described in FIG. 1, is provided on the second surface of the carrier. In one embodiment, an adhesive is provided between at least the second surface 185b of the carrier and the first surface 150a of the die. In another embodiment, an adhesive may also be provided between the second surface of the carrier and the first surfaces of the cap and the die. The adhesive, for example, permanently bonds at least between the carrier and the die.

3A-3H illustrate one embodiment of a method for forming a semiconductor package 300. 3A shows a wafer 301 having a first surface 301a and a second surface 301b. The wafer functions as a substrate for forming the die 350. The first surface is for example an inactive surface 350a while the second surface is an active surface 350b. Other names of surfaces may also be useful. The wafer can be, for example, a silicon wafer. Other types of semiconductor wafers may also be useful. In one embodiment, the wafer is processed to include a plurality of dies or chips. For example, a plurality of dies are processed in parallel on the wafer. Illustratively, the wafer includes three dies processed in parallel. It may also be useful to provide wafers with other numbers of dies or chips.

Die 350 includes circuit components formed on a wafer or substrate. Circuit components include, for example, transistors, resistors, capacitors, and interconnects to form ICs. The final passivation layer can be formed over the die. The final passivation layer includes an opening for exposing the die pad 355. The surface of the substrate or wafer that includes an opening for the die pad may be referred to as the active surface of the wafer.

In one embodiment, sacrificial layer 377 is formed over the active surface of wafer 301b. The sacrificial layer is a temporary layer that is subsequently removed. The sacrificial layer is for example an adhesive material. Other types of sacrificial layers can also be used. The sacrificial layer can be formed on the substrate using various techniques. For example, the sacrificial layer can be provided by spin coating or lamination. Other techniques for forming the sacrificial layer may also be useful. The technique may depend, for example, on the type of sacrificial layer. In one embodiment, the sacrificial layer can be semi-cured to become less tacky during the capsule process. In another embodiment, the sacrificial layer remains tacky to improve adhesion to the support carrier when used.

The process continues by dicing the wafer being processed with the sacrificial layer and die over the active surface of the wafer. Dicing the wafer separates the die into individual dies with a sacrificial layer on the active surface. In another embodiment, sacrificial layer 377 may be formed over the active surface of the die after dicing the wafer into individual dies.

Referring to FIG. 3B, a carrier 385 is provided. In one embodiment, the carrier is a permanent carrier or permanent support used for processing a chip package, for example. In one embodiment the carrier must have sufficient rigidity to withstand further processing steps and serve as a support that permanently holds the die. For example, the carrier should have sufficient rigidity to reduce or prevent warpage of the chip assemblies during the assembly process. Alternatively or additionally, the carrier may also function as a thermal conductor, for example to dissipate heat from the die of the semiconductor package. By way of non-limiting example, the carrier may be a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Various other types of materials can be used to form the carrier.

The carrier includes a first surface 385b in which the die is processed to form a package. The carrier may be configured in a strip format to process a row of dies. In another embodiment, the carrier is configured to process a plurality of rows of die. For example, the carrier may have a panel format to form a package of two dimensional arrays. It may also be useful to provide a carrier configured in a wafer format to form a plurality of packages. In some embodiments, the carrier may be configured to form one package, for example a single format. The type of format chosen may depend, for example, on the requirements of the process, available equipment or cost considerations.

By way of example, the carrier is configured in a strip format with zones 380a-380c for forming three pocket regions or three pockets. It may also be useful to provide a carrier with other numbers of pocket areas or formats. The package area includes a die area and a non-die area. The size of the package area is about the same as the size of the package. Die 350 coated with sacrificial layer 377 on active surface 350b is attached to the die region. For example, three dies 350 _1-3 are attached to the die area on the permanent carrier.

In one embodiment, adhesive 375 is provided on the first surface 385b of the carrier to facilitate die attach. Other bonding techniques may also be used to attach the die to the carrier. The adhesive is provided at least in the die area on the carrier, for example to permanently hold the chip assembly thereon. In one embodiment, the adhesive is only provided in the die area. In another embodiment, the adhesive is mostly provided on the entire first surface 385b of the carrier.

In another embodiment, adhesive 375 may be provided over the inert surface of the wafer. The adhesive can be applied, for example, before or after dicing the wafer into individual dies.

The adhesive can be any type of adhesive that provides permanent bonding of the chip assembly to the chip assembly surface of the carrier. The adhesive 375 may comprise the same material as the sacrificial layer 377, for example. In other embodiments, the adhesive 375 may comprise a different material than the sacrificial layer. The adhesive may comprise a suitable thickness such that it can permanently bond the die and the carrier during processing. The adhesive can be of different types. For example, the adhesive can be a film, liquid or thermally conductive adhesive. The adhesive may be provided to the inert surface or carrier of the wafer or die using various techniques. The technique applied may depend on the type or type of adhesive. For example, the tape adhesive may be provided on the carrier by a stack, and the paste adhesive may be provided on the carrier by printing, while the liquid adhesive may be provided on the carrier by spin-coating. It may also be useful to provide adhesive to the inert surface, carrier of the wafer or die using other techniques.

In one embodiment, the inactive surface 350a or the back side of the die is attached to the die region of the carrier. The die is attached to the die area using any suitable technique depending on the type of equipment and the equipment used.

Referring to FIG. 3C, a cap 390 is formed to encapsulate the die. In one embodiment, the cap is disposed in the non-die region of the permanent carrier. For example, encapsulation material is dispensed to fill the space between the dies. In one embodiment, the encapsulation material is a mold compound, such as a molding epoxy resin material. It may also be useful to provide other types of encapsulation material.

In one embodiment, the cap is formed by transfer molding techniques. In one embodiment, the cap is formed by a film assisted transfer molding technique. For example, the film 393 is disposed in contact with the outline of the mold (not shown). In one embodiment, when the carrier and the die are placed against the mold, the film contacts the sacrificial layer on the active surface of the die, leaving a space therebetween within the non-die region. Encapsulation material, such as a mold compound, is dispensed into the mold assembly to fill the space in the non-die region to form a cap. The sacrificial layer protects the active layer of the die from the encapsulation material. After molding, the molded panel of the die is separated from the mold. The sacrificial layer also facilitates the release of the molded panel from the molding tool. Other techniques for forming the cap may also be useful. For example, the cap can be formed by printing or compression molding.

Removal of the mold leaves a plurality of dies attached to each other by the cap 390 and the carrier 385. The carrier provides additional mechanical support for the chip for further processing. The surface of the cap is in one embodiment coplanar with the surfaces of the die. For example, the first surface 390a of the cap is coplanar with the first surface 350a or the rear surface of the die and the second surface 3390b is a sacrificial layer on the active or second surface 350b of the die ( Is coplanar with 377). Alternatively, the first surface of the cap need not be coplanar with the first surface of the die. For example, the first surface 390a of the cap is disposed in a plane different from the back surface 350a of the die, depending on the thickness of the adhesive layer 375 disposed in the die region on the surface 385b of the carrier. External heat sink or heat spreader (city May also be attached to the rear face 385a of the carrier to further improve heat dissipation.

Referring to FIG. 3D, the sacrificial layer 377 is removed. In one embodiment, the sacrificial layer is removed by dissolving the layer with chemicals. For example, chemicals are preferably used to remove the sacrificial layer that do not cause any damage to the second or active surface of the die. Other techniques can also be used to remove the sacrificial layer. Removal of the sacrificial layer exposes the active or second surface of the die and die contact pads 355. The cleaning step may optionally be performed to clean the second surface of the contact pad and die. For example, a solvent based on the cleaning step can be applied. Other suitable cleaning techniques are also useful.

In one embodiment, the second surface 390b of the cap is not coplanar with the active surface 350b of the die. For example, the active surface of the die and the second surface of the cap form step 387. In one embodiment, the active surface of the die is recessed below the surface of the cap. The height of the step may for example be approximately the thickness of the sacrificial layer. Other step heights may also be useful.

Providing a step between the active surface of the die and the cap surface mitigates the mechanical stress caused by the difference between the mold compound in the subsequently formed package and the thermal coefficient of the die.

The process continuously forms a package substrate. The process continuously forms, for example, a built-up or integrated wiring substrate. The package substrate includes, for example, a multi-layered substrate. In one embodiment, a first insulating substrate layer 313 is provided on the active surface of the die and the second surface of the cap. For example, the first substrate 313a of the first substrate layer contacts the second surface of the cap and fills the recess above the die.

In one embodiment, the first substrate layer may be a dielectric layer. The dielectric layer is disposed on the active surface of the die, for example. Other types of first substrate layers may also be used. The dielectric material may be deposited via appropriate techniques such as wafer processing techniques, spin coating, printing, and the like. Other techniques for depositing the first substrate layer may also be useful.

Via 315 is formed in the first substrate layer. The via extends from the second surface 313b through the first surface 313a to expose the contact pads of the die. In one embodiment, the vias are formed by laser drilling. Other techniques such as mechanical drilling or RIE are also useful. The vias may have a tapered or straight profile, depending on the type and process requirements of the via formation method used. In one embodiment, the vias are formed in a straight profile. It is also useful to provide a tapered profile (not shown). In particular, tapering of the sidewalls facilitates filling of the vias. For example, tapered sidewalls facilitate uniform material coverage of the sidewalls and the base of the via, which reduces the formation of voids.

Referring to FIG. 3F, the process continues to form traces 340 and conductive via contacts 330 of the package substrate. In one embodiment, a conductive layer is formed on the first substrate layer to cover the second surface of the first substrate layer to fill the vias. The conductive layer can for example be copper or a copper alloy. Other types of conductive materials may also be useful. For example, other types of conductive materials may include aluminum, gold, nickel or combinations or alloys thereof. The conductive layer can be formed by plating. For example, electrochemical or electroless plating may be applied to form the conductive layer. Other suitable methods of forming the conductive layer can also be used. In certain embodiments, a seed layer may be used prior to forming the conductive layer.

The patterning of the conductive layer can be formed by the patterned masked layer prior to the plating process. Alternatively, the conductive layer may be patterned to form conductive traces 340 coupled to substrate via contacts 330 in vias coupled to die pads of the same die. Conductive traces and vias form the interconnect. Patterning of the conductive layer can be accomplished by any suitable etching technique. For example, a patterned etch mask, such as a photoresist, is provided over the conductive layer. Etching may be performed using an etch mask to remove portions of the conductive layer that are not protected by the etch mask. Etching, for example isotropic etching, such as wet etching. Anisotropic etching can be used, such as reactive ion etching (RIE). Other techniques for patterning the conductive layer can also be used.

After patterning the conductive layer, the mask is removed. The mask may be removed by ashing, for example. Other techniques for removing the mask can also be used.

As shown in FIG. 3A, a second insulating substrate layer 317 having a first surface 317a and a second surface 317b is deposited on the first substrate layer, covering and filling the space between the conductive traces. . The second substrate layer provides insulation between the conductive traces. The first surface 317a of the second substrate layer is in contact with the first substrate layer. The second substrate layer functions as a contact mask. In one embodiment, the second substrate is formed of a polymer. The second substrate layer can be formed by spin-coating, for example. Other types of dielectric materials and deposition techniques may be useful for forming the second substrate layer.

The second substrate layer is patterned to form contact openings 319 to expose portions of the conductive traces. The contact openings correspond to the positions of the package contacts of the semiconductor package. For example, contact openings may be disposed in the grid pattern to form a BGA type package. Other contact opening patterns may also be used.

In one embodiment, the package or conductive pad 368 is formed on the exposed portion of the conductive trace 340, as shown in FIG. 3H. In one embodiment, the package pad comprises a conductive material. In one embodiment, package pads are selectively formed in openings in the dielectric layer by coating or plating techniques. Other types of conductive materials or techniques can be used to form the contact pads. The conductive pad is for example on the same plane as the conductive trace. In another embodiment, the conductive pad can include a protruding conductive pad. The conductive pad may be further covered with a surface protective material such as OSP or metal coating or plating.

The process continues by forming a package contact 370 in the opening of the package mask, as shown in FIG. 3H. For example, a package contact is formed on the package pad 368 in the opening of the package mask. The package contact may include, for example, a ball or spherical structure disposed within the grid pattern to form a BGA type package. The package contact is formed of a conductive material. Package contacts may be formed by soldering in one embodiment. Various types of solder can be used to form package contacts. For example, the solder can be lead-based or non-lead-based soldering.

In certain embodiments, other types of package contacts are formed in the openings. For example, the package contacts may include contacts that do not protrude from the bottom surface of the second substrate layer. It may also be useful to provide a package contact that does not protrude from the bottom surface of the second substrate layer, such as a solder land. Package contacts may be formed using materials or other techniques other than soldering.

In another embodiment, package contacts may include copper pillers or gold stud bumps (not shown). The use of copper fillers is excellent when they do not collide after reflow. Thus, the copper filler can enable the production of semiconductor packages with a much-titled pitch and a more uniform standoff height. On the other hand, gold stud bumps can sometimes be used in conjunction with effervescent conductive adhesives and thermal compression welding methods to achieve a title pitch. This is excellent when an IC chip originally designed as a peripheral bond pad for the purpose of wire bonding can be used as flip chips. Other suitable types of package contacts can also be used.

The process subsequently singulates the structure to form individual semiconductor packages. As shown in FIG. 1, a semiconductor package is formed.

4A-4C show another embodiment of a process for forming a semiconductor package 400. The process is similar as described in Figures 3A-3H. As such, common elements may not be described above or may not be described in detail. Referring to FIG. 4A, a wafer 401 having a die stack arrangement is provided. In one embodiment, the wafer is processed to include a plurality of die stacks 410.

The die stack contains n dies, where n is at least two. The bottom die may for example be referred to as first (eg n = 1) and the top die is n. It may also be useful to refer to the die of the die stack using other conventions. The die stack may be formed, for example, by any suitable type of die stacking methods. As such, the die stack includes first and second dies 450 ₁ and 450 ₂ . The second die 450 ₂ is attached onto the first die 450 ₁ , and the first die is attached to the die region of the wiring substrate. The die used for the die stack may be TSV or non-TSV. In one embodiment, both the top and bottom die can be TSV dies. In another embodiment, the bottom die may comprise a TSV die and the top die may comprise a non-TSV die. Non-TSV dies may include, for example, bonded wires, direct connections, flip chip dies, and the like. For die stacks having two or more dies, the bottom die (bottom and middle die except the top die) may be a normal TSV die while the top die may be a non-TSV die. Other configurations or types of die in the die stack may also be useful.

The TSV die includes first and second major surfaces 450a and 450b. The first surface includes a first die contact 433 and the second major surface includes a second die contact 435. The die contact is, for example, a die contact pad having an upper surface that is coplanar with the first and second major surfaces of the TSV die. It may also be useful to provide a surface of the contact pad that is not coplanar with the surface of the die. Other configurations of die contacts or die contact pads may also be useful. The first and second die contacts are interconnected by through via contacts 430. Other configurations of TSV dies may also be useful. Via contacts and contact pads are formed, for example, of conductive material. The conductive material may include copper for example. Other types of conductive materials can also be used for via contacts and contact pads.

As shown in FIG. 4A, the first die contact 433 is coincident with the second die of the die stack. In one embodiment, the die attach film or underfill 417 protects and stacks the bonding contact 440 coupling the first die contact 433 of the first die and the conductive die pad 355 of the second die. It may be provided in a cavity formed between the dies to facilitate this. For cases where two or more dies are used to form the die stack, the bottom and middle dies may be TSV dies. Other types of dies may also be used for the bottom and middle dies. n ^th The second die contact of the + 1 die is connected to the first die contact of the n ^th die below.

In one embodiment, sacrificial layer 377 is formed over die stack or second major surface 450b of first die 450 ₁ of wafer 401.

The process continues by dicing the wafer being processed into a die stack and a sacrificial layer over the second surface of the wafer. Dicing the wafer separates the die stack into individual die stacks 410 _1-3 . Although three die stacks are shown in FIG. 4B, it is understood that other numbers of die stacks may also be provided over the second surface 450b. In another embodiment, the sacrificial layer 377 may be provided after dicing the wafer into individual die stacks.

Referring to FIG. 4B, the process is in a similar stage as described in FIG. 3B. For example, a carrier 385 having an adhesive 375 on the first surface 385b of the carrier is provided with a die stack 410 _1-3 that is attached to a die region on the carrier. In one embodiment, the back surface or first surface 350a of the second die of the die stack contacts the die area with the adhesive 375 of the carrier 385. The die stack is attached to the die area using any suitable technique depending on the type of equipment and the adhesive used. In one embodiment, the carrier functions as a permanent carrier used for processing the chip package. In one embodiment, the carrier should have sufficient rigidity to function as a permanent support for holding the die stack during assembly. Alternatively or additionally, the carrier can also function as a thermal conductor, for example to dissipate heat from the die stack of the semiconductor package. By way of non-limiting example, the carrier may be a wafer or a conductive plate. For example, the wafer may comprise a silicon wafer and the conductive plate may comprise a metal plate. Various other types of materials can be used to form the carrier.

In one embodiment, adhesive 375 is provided on the first surface of the carrier to facilitate die stack attachment. Other bonding techniques may also be used to permanently bond the die stack to the carrier. The adhesive is provided at least in the die area on the carrier, for example to permanently hold the chip assembly thereon. In one embodiment, the adhesive is provided to the die area of the care. In another embodiment, the adhesive is provided on the entire first surface of the carrier.

In another embodiment, adhesive 375 may be provided over the first surface of the wafer. The adhesive can be applied, for example, before or after dicing the wafer into individual die stacks. For example, the adhesive may be applied to the back surface or first surface 350a of the second die of the die stack.

The process subsequently forms a cap 390 as shown in FIG. 4C. In one embodiment, the cap is formed of an encapsulation material, similar to that described in FIG. 3C. In one embodiment, the cap covers the side of the die stack as shown in FIG. 4C.

After forming the cap, the process proceeds continuously as similarly described in Figure 3d. For example, the process continues to form a semiconductor package as described in FIG. 3D and proceeds until the semiconductor package as described and shown in FIG. 2 is produced.

The process as described with respect to FIGS. 3A-3H and 4A-4C yields good results. For example, the sacrificial layer is used to protect the second major surface or active surface of the die or die stack from contamination during molding. In particular, the sacrificial layer is a temporary coating that is removed after molding to create a recess on the second surface of the die or die stack to relieve mechanical stress resulting from thermal mismatch between the mold compound and the die or die stack. Function The process also allows various molding techniques such as printing, transfer and compression molding to be used to form the cap.

It is understood that although only one conductive via and trace level may be formed and coupled to the die pad of the same die in the package substrate, additional conductive vias and trace levels may be included. For example, the first substrate layer may include a plurality of first sub layers. Therefore, the process can build up (compose) a plurality of wiring structures in a package substrate as compared to existing wafer based fan out processes that are limited to single metal layer fan out structures. Moreover, because the cap functions as a mechanical support for the die to form a package substrate on the die and the structure made is in the form of a panel or strip, the substrate process can be used to form a redistribution structure on the active surface of the die. Likewise, a conventional wafer redistribution layer formation process is not necessary. This avoids the need for investment in new wafer based process equipment.

In addition, the carrier as described serves as a permanent carrier or permanent support for holding the die or die stack during assembly. Likewise, the permanent carrier provides additional support for the die or die stack during assembly and during the formation of a redistribution structure on the die's active surface. Moreover, the carrier remains as part of the packaged structure. Likewise, the process for forming a semiconductor package is simple because the carrier and the step of removing the adhesive from the carrier are eliminated. In addition, depending on the material used for the carrier, the permanent carrier also functions as a thermal conductor to dissipate heat from the die or die stack of the semiconductor package. Permanent carriers therefore make it possible to produce semiconductor packages with reinforced heat elements.

In addition, at least the permanent adhesive used to bond the carrier and die avoids the same problem of resin leakage and prevents the die from shifting during the molding process of forming the cap. In addition, the processor for forming the semiconductor package is moreover because additional processing steps are not required to remove the extra encapsulation material for exposing the first or second surface of the die for further processing. It's simple.

The invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the above-described embodiments should be considered to be illustrative in all respects without limiting the invention described herein.

Claims (20)

As a method for forming a semiconductor package,
Providing at least one die having a first surface and a second surface, the second surface of the die comprising a plurality of conductive pads;
Providing a permanent carrier and attaching the at least one die to the support carrier, the first surface of the at least one die facing the permanent carrier; And
Forming a cap having a first surface and a second surface to encapsulate the one or more die, wherein the first surface of the cap is in contact with a permanent carrier and the second surface of the cap is the second of the die. Comprising a step, disposed in a plane different from the surface,
Method for forming a semiconductor package.
The method of claim 1,
Providing an adhesive on the first surface of the carrier,
Method for forming a semiconductor package.
3. The method of claim 2,
Providing the adhesive to a die area on the first surface of the carrier for permanently holding at least the one or more dies to the carriage,
Method for forming a semiconductor package.
The method of claim 1,
Providing an adhesive on the first surface of the die,
Method for forming a semiconductor package.
The method of claim 1,
The adhesive comprises a film, paste, liquid or thermally conductive adhesive,
Method for forming a semiconductor package.
The method of claim 1,
The permanent carrier comprises a wafer or a conductive plate,
Method for forming a semiconductor package.
The method of claim 1,
Attaching the one or more dies to the permanent carrier is performed prior to forming the cap;
Method for forming a semiconductor package.
The method of claim 1,
Forming a sacrificial layer on a second surface of the at least one die,
Method for forming a semiconductor package.
The method of claim 8,
Removing the sacrificial layer after forming the cap;
Method for forming a semiconductor package.
The method of claim 1,
The cap is formed by a molding technique comprising transfer molding or compression molding,
Method for forming a semiconductor package.
The method of claim 1,
Forming a built-up package substrate having interconnects on a second surface of the at least one die, the interconnects being coupled to conductive pads of the same die;
Method for forming a semiconductor package.
11. The method of claim 10,
Forming the built-up package substrate may include:
Providing a first patterned substrate layer having vias on a second surface of the at least one die; And
Forming the interconnect;
Forming the interconnect includes providing a conductive layer over the surface of the substrate layer to form substrate via contacts and conductive traces in the via, the conductive traces and contacts coupled to conductive pads of the same die. ,
A method of forming a semiconductor package.
As a method of forming a semiconductor package,
Providing at least one die stack having a first surface and a second surface, the second surface of the die stack comprising a plurality of conductive pads;
Providing a permanent carrier and attaching the at least one die stack to the permanent carrier, the first surface of the at least one die stack facing the permanent carrier,
Forming a cap having a first surface and a second surface to encapsulate the one or more die stacks, the first surface of the cap contacting the permanent carrier and the second surface of the cap being the first surface of the die stack; Comprising a step, disposed in a plane different from the two surfaces,
Method of forming a semiconductor package.
The method of claim 13,
Providing an adhesive on the first surface of the carrier,
Method for forming a semiconductor package.
15. The method of claim 14,
Providing the adhesive to a die area on the first surface of the carrier for permanently holding at least the one or more dies to the carriage,
Method for forming a semiconductor package.
The method of claim 13,
Providing an adhesive on the first surface of the die,
Method for forming a semiconductor package.
The method of claim 13,
The adhesive comprises a film, paste, liquid or thermally conductive adhesive,
Method for forming a semiconductor package.
The method of claim 13,
The permanent carrier comprises a wafer or a conductive plate,
Method for forming a semiconductor package.
The method of claim 13,
Attaching the one or more dies to the permanent carrier is performed prior to forming the cap;
Method for forming a semiconductor package.
The method of claim 13,
Forming a sacrificial layer on a second surface of the at least one die,
Method for forming a semiconductor package.

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