TWI569380B - Semiconductor packages and methods of packaging semiconductor devices - Google Patents

Description

Semiconductor package and method of packaging a semiconductor device

The present invention relates to semiconductor devices and, more particularly, to methods of semiconductor packaging and packaging semiconductor devices.

The present invention is a continuation-in-part application of U.S. Patent Application Serial No. 13/295,097, filed on Nov. 14, 2011, which is filed on November 15, 2010, entitled "Embedded Die The priority of U.S. Provisional Application No. 61/413,577, the entire disclosure of which is incorporated herein by reference.

Industrial fanout solutions involve high capital investment costs for new wafer redistribution layer (RDL) and bump facilities. In addition, new equipment for compression molding systems and trim sets is needed to enable wafer handling in pick-and-place systems for fan-out solutions.

In order to minimize or avoid the costs mentioned above, there is a need for improved fan-out semiconductor packaging processes that can take advantage of existing equipment tools and processes associated with current wafer level fan-out solutions. In addition, there is a need to create a fan-out semiconductor package that has a very thin package outline, a high I/O count for wafer level wafer scale packaging, with a multi-level redistribution layer and (possibly) system in the package application. In addition, there is a need to produce semiconductor packages with enhanced heat dissipation capabilities.

Embodiments are generally related to semiconductor packages. In an embodiment, presenting A method for forming a semiconductor package. The method includes providing at least one die having a first surface and a second surface. The second surface of the die includes a plurality of conductive pads. The method also includes providing a permanent carrier and attaching the at least one die to the permanent carrier. The first surface of the at least one die faces the permanent carrier. A cover having a first surface and a second surface is formed to encapsulate at least one die. The first surface of the cover contacts the permanent carrier and the second surface of the cover is disposed at a plane different from the second surface of the die.

In another embodiment, a method for forming a semiconductor package is disclosed. The method includes providing at least one die stack having a first surface and a second surface. The second surface of the die stack includes a plurality of conductive pads. A permanent carrier is provided and the at least one die stack is attached to the permanent carrier. The first surface of the at least one die stack faces the permanent carrier. A cover having a first surface and a second surface is formed to encapsulate the at least one die stack. The first surface of the cover contacts the permanent carrier and the second surface of the cover is disposed at a different plane than the second surface of the die stack.

These and other advantages and features of the invention will be apparent from the description and accompanying drawings. In addition, it should be understood that the features of the various embodiments described herein are not mutually exclusive and may be present in various combinations and arrangements.

In the drawings, the same reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, In the following description, various embodiments of the invention are described with reference to the following drawings.

Embodiments relate to semiconductor packages and methods for forming semiconductor packages. The packages are used to package one or more semiconductor dies or wafers. For more than one die condition, the dies may be configured in a planar configuration, a vertical configuration, or a combination thereof. The die, for example, may include a memory device, a logic device, a communication device, an optoelectronic device, a digital signal processor (DSP), a microcontroller, a system single chip (SOC), and other types of devices, or a combination thereof. Such packages can be incorporated into electronic products or devices, such as telephones, computers, and mobile products and mobile smart products. It can also be useful to incorporate the package into other types of products.

Figure 1 shows a simplified cross-sectional view of one embodiment of a semiconductor package 100 having a portion A' in more detail. The package includes a combined or integrated wiring substrate 110. The wiring substrate includes a first major surface 111 and a second major surface 112. The first major surface, for example, may be referred to as a top surface, and the second major surface, for example, may be referred to as a bottom surface. Other naming of the surface can also be useful. In an embodiment, the first major surface of the wiring substrate includes a first region 111a and a second region 111b. The first region is, for example, a die or wafer region on which the die 150 is mounted, and the second region is, for example, a non-grain region. In an embodiment, the non-grain regions surround the grain regions. The grain region, for example, may be disposed in a central portion of the mounting die 150, and the non-grain region 111b is external to the die attach region. The grain regions, for example, may be concentrically disposed within the periphery of the wiring substrate. Other configurations of die regions and non-grain regions may also be useful.

The grains can be semiconductor dies or wafers. The die can be, for example, any type of integrated circuit (IC), such as a memory device such as dynamic random access memory (DRAM), static random access memory (SRAM), and various types. Non-volatile memory, including programmable read-only memory (PROM) and flash memory), optoelectronic devices, logic devices, communication devices, digital signal processors (DSPs), microcontrollers, system single-chips, and Other types of devices.

The die includes a first surface 150a and a second major surface 150b. The first surface is, for example, the inactive or back side of the die, and the second surface is the active surface of the die. Other naming of the surface of the die can also be useful. The surface of the die contacts the die area of the wiring substrate. The active surface, for example, includes an opening in the final passivation layer (not shown) to expose the conductive die pad 155. The surface of the conductive die pad is, for example, substantially coplanar with the second major surface 150b of the die. It may also be useful to provide a surface of the conductive pad that is not coplanar with the second major surface of the die. The die pad provides a connection to the circuitry of the die. The die pad is formed, for example, of a conductive material such as copper, aluminum, gold, nickel or alloys thereof. Other types of conductive materials can also be used for the die pad. The pattern of die pads may be one or more columns disposed at the center or opposite sides of the active surface. Other pad patterns, such as grid or matrix configurations, may also be useful.

In an embodiment, the wiring substrate comprises a multilayer substrate. In an embodiment, the multilayer substrate includes a first insulating substrate layer 113 and a second insulating substrate layer 117. The first layer includes a first surface 113a and a second surface 113b. The first surface may be referred to as a top surface and the second surface may be referred to as a bottom surface. Other naming of the surface of the first layer may also be useful. The first surface contacts the die. In one embodiment, the first layer includes perforated contacts 130 that extend from the first surface of the first layer to the second surface. The via contacts are formed of a conductive material. For example, the via contacts can be formed of copper, aluminum, gold, nickel, or alloys thereof. Other types of conductive materials may also be useful. The via contacts are isolated from each other by the first insulating substrate layer.

The conductive traces 140 are disposed on the second surface of the first insulating substrate layer. The conductive traces are formed from a conductive material such as copper, aluminum, gold, nickel or alloys thereof. Other types of conductive materials may also be useful. The conductive traces are coupled to substrate via contacts forming interconnects that are coupled to die pads of the same die. The conductive traces can include conductive pads 168.

The first substrate layer can be a dielectric layer. A dielectric layer, for example, is disposed on the second surface of the die. Other types of first substrate layers may also be useful. In other embodiments, the substrate layer can be patterned to provide vias in which the substrate via contacts are disposed. The formation of vias in the first substrate layer can be achieved by any suitable technique including, but not limited to, laser and mechanical drilling.

The second insulating substrate layer includes a first surface 117a and a second surface 117b. The first surface may be referred to as a top surface and the second surface may be referred to as a bottom surface. Other nomenclature of the surface of the second insulating substrate layer may also be useful. The first surface of the second insulating layer is disposed on the second surface of the first substrate layer and the conductive trace; the second surface serves as the bottom surface of the package. The second substrate layer isolates the conductive traces from each other. The second substrate layer may be formed of a solder resist or other dielectric material. Other types of second substrate layers may also be useful.

The opening is disposed in the second substrate layer in which the package contact 170 is disposed. The opening, for example, exposes the conductive pads on the conductive traces. The pattern of openings can be designed to provide the desired package contact pattern. For example, the contact openings can be configured in a grid pattern to form a BGA type package. Other contact opening patterns can also be useful. The conductive pads are, for example, coplanar with the conductive traces. In other embodiments, The electrical pad can include a protruding conductive pad. The conductive pads may be further covered with a surface protective material such as an OSP or metal coating or plating.

The outer package contacts 170 are disposed on the second substrate layer in the openings. The package contacts are, for example, spherical structures or balls. The package contacts protrude from the bottom surface of the second substrate layer. It may also be useful to provide package contacts (such as pads) that do not protrude from the bottom surface of the second substrate layer. The package contacts are formed from a conductive material. In an embodiment, the package contacts may be formed from solder. Various types of solder can be used to form the package contacts. For example, the solder can be a lead based or non-lead based solder. Other types of conductive materials can also be used to form package contacts.

In other embodiments, the package contacts may include other types of package contacts, such as copper posts or gold stud bumps (not shown). The use of a copper column is advantageous because it does not break after reflow. Thus, the copper posts enable the semiconductor package to produce a much tighter pitch and a more uniform pad height. On the other hand, gold stud bumps can sometimes be used in combination with anisotropic conductive adhesives and thermocompression bonding methods to achieve tight spacing. This is advantageous because it allows the IC wafer originally designed for the peripheral bond pads intended for wire bonding to be used as flip chip. Other suitable types of package contacts may also be useful.

The package contacts provide external access to the die via conductive traces, substrate via contacts, and die pads. The package can be electrically coupled to an external device (not shown) such as a circuit board by a package contact.

In an embodiment, the combined wiring substrate is an integrated package substrate. As described, the package substrate directly contacts the die in the die region, wherein the conductive trace and the via contact are coupled to the die pad of the same die. In an embodiment, the integrated package substrate includes a via hole directly coupled to the die pad of the same die. point. The wiring substrate acts as a fan-out redistribution structure for the dies, thereby enabling a fan-out external package connection for redistribution.

As described, the first substrate layer is a single layer. In other embodiments, the first substrate layer 113 can include a plurality of first sub-layers. For example, the first substrate layer may include a first first sub-layer and a second first sub-layer. It may also be useful to provide a first substrate layer having other numbers of first sub-layers. The first first sub-layer and the second first sub-layer, for example, may comprise the same material. It may also be useful to provide a first sub-layer having a different material than the second sub-layer. The first sub-layer is similar to the first substrate layer. For example, the first sub-layer includes a first surface and a second surface and substrate via contacts extending through the conductive traces on the surfaces and the second surface. The first surface of the sub-layer contacts the die or is adjacent to the second surface of the first sub-layer. This produces a first substrate layer or layered stack with multiple conductive layers. Providing a first substrate layer having a plurality of combined conductive layers facilitates packaging of higher density dies having die contacts and package contacts.

In one embodiment, the cover 190 is formed on the second region 111b of the first major surface 111 of the package substrate. The cover is used to protect the crystal grains from the environment. For example, the cover protects the die from moisture. The cover, for example, is formed from an encapsulating material. The encapsulating material, for example, can be a molded epoxy material. Other types of encapsulating materials can also be useful.

The cover includes a first major surface 190a and a second major surface 190b. The first surface can be, for example, a top surface and the second surface can be a bottom surface. Other naming of the surface of the cover can also be useful. In an embodiment, the cover surrounds at least the die. For example, the bottom surface 190b is disposed on the package substrate on the non-grain area of the package substrate. The cover protects the die by surrounding the die.

In an embodiment, the non-grain regions are disposed in a different plane than the grain regions. For example, as shown by the portion A', the die regions and the non-grain regions form a step 187 in the package substrate. In one embodiment, the die zone is disposed or recessed into the encapsulating material relative to the first major surface 190a of the shroud. For example, the die region 111a has a greater distance from the bottom portion 117b of the package substrate than the non-die region 111b. The non-grain regions are, for example, above the die region or the conductive die pad relative to the first major surface 190a of the shroud. Referring to Figure 1a, the second surface of the die is disposed in a plane different from the second surface of the cover. Providing the bottom surface of the shroud at a plane other than the die advantageously mitigates mechanical stress on the die due to thermal mismatch of the encapsulating material.

In one embodiment, the cover does not cover the back or first surface of the die, as shown in FIG. For example, the top surface 190a of the cover is approximately coplanar with the back side 150a of the die. Alternatively, the top surface of the cover need not be coplanar with the back side of the die. For example, as will be described later, the first surface 190a of the cover is above the back side 150a of the die, depending on the thickness of the adhesive layer disposed on the back side of the die.

In one embodiment, the carrier 185 is permanently disposed on the top surface of the cover 190a and the die 150a or on top of the first surface. For example, the carrier remains as part of the encapsulated die. The carrier includes a first major surface and a second major surface. For example, the first major surface 185a is the top surface and the second major surface 185b is the bottom surface of the carrier. Other naming of the surface of the carrier may also be useful. In one embodiment, the second surface of the carrier contacts at least the first surface of the cover and the first surface of the carrier is exposed. For example, the second surface of the carrier covers substantially the entire first surface of the die and the cover.

In one embodiment, the adhesive 175 is disposed on the second surface of the carrier. For example, the adhesive bonds at least the carrier to the die. In one embodiment, the adhesive is disposed between at least the second surface of the carrier and the first surface of the die. In other embodiments, the adhesive may be disposed between the second surface of the carrier and the cover and the first surface of the die. For example, the adhesive includes a film, a paste, a liquid or a thermally conductive adhesive. Other suitable types of adhesives that promote bonding at least between the carrier and the die may also be used. The adhesive may comprise any suitable thickness as long as it can at least permanently bond the die to the carrier during processing.

As shown in Figure 1, the carrier covers substantially the entire first surface of the die and the cover. In an embodiment, as will be described in detail later, the carrier should be stiff enough to act as a permanent carrier or permanent support to hold the die or die stack during assembly. Alternatively or in addition, for example, the carrier can also act as a thermal conductor to dissipate heat from the die or die stack of the semiconductor package. As a non-limiting example, the carrier can include a wafer or a conductive plate. For example, the wafer can include a germanium wafer, and the conductive plate can include a metal plate. Other suitable types of materials may also be used to form the carrier. The semiconductor package may also include additional heat sinks or heat spreaders to enhance heat dissipation. For example, a heat spreader (not shown) can be attached to the carrier to further improve heat dissipation.

FIG. 2 shows another embodiment of a semiconductor package 200. The semiconductor package is similar to the semiconductor package described in FIG. Thus, common elements may not be described or described in detail.

The semiconductor package 200 includes a die stack 210 mounted on a die region 111a of the wiring substrate 110. The die stack includes n number of grains, wherein n 2. The bottom grain, for example, may be referred to as the first (eg, n=1) and the top grain is equal to n. It is also useful to use other specifications to name the die of the die stack. The die stack can be formed, for example, by any suitable type of die stacking method. As shown, the die stack includes a first die 250 ₁ and a second die 250 ₂ . The second die 250 _{2 is} attached to the first die 250 ₁ , and the first die is attached to the die region 111 a of the wiring substrate 110 . The grains used for the die stacking may be TSV or non-TSV grains. In an embodiment, both the top and bottom dies may be TSV dies. In yet another embodiment, the bottom die can include TSV die and the top die can include non-TSV die. Non-TSV dies, for example, may include wire bonds, direct connections, flip chip, and the like. For a die stack having more than two grains, the lower grains (bottom grains and intermediate grains except the top grains) are typically TSV grains, while the top grains are non-TSV grains. Other configurations or types of die of the die stack can also be useful.

The TSV die includes a first major surface 250a and a second major surface 250b. The first surface includes a first die contact 233 and the second major surface includes a second die contact 235. The die contacts are, for example, die contact pads having a top surface that is coplanar with the first major surface 250a and the second major surface 250b of the die. It may also be useful to provide a surface that is not in contact with the surface of the die. Other configurations of die contacts or die contact pads may also be useful. The first die contact and the second die contact are interconnected by a via contact 230. Other configurations of TSV die can also be useful. The via contacts and contact pads are formed, for example, of a conductive material. The electrically conductive material, for example, can include copper. Other types of conductive materials can also be used for via contacts and contact pads.

As shown, the second die contact 235 of the bottom die is mounted to the die region 111a of the wiring substrate. The first die contact 233 mates with the top die of the die stack. In an embodiment, a die attach film or primer 217 may be disposed in the recess formed between the crystal grains to facilitate stacking, and protect the conductive die pad 155 and the first die coupled to the second die. The junction of the first die contact 233 is a junction 240. A redistribution layer can also be set. Similar to FIG. 1, the die regions and non-grain regions of the semiconductor package 200 form a step 187 in the package substrate. For the case where two or more dies are used to form a grain stack, the bottom and intermediate grains may include TSV grains. It may also be useful to provide non-TSV grains for the bottom and intermediate grains. The second die contact of the upper n+1th die is connected to the first die contact of the nth die below.

A cover 190 is provided to encapsulate the die stack 210. In an embodiment, the cover surrounds at least the die stack. For example, the cover surrounds and protects each side of the first die 250 ₁ and the second die 250 ₂ of the die stack. Similar to FIG. 1, the die area is disposed or recessed into the encapsulating material relative to the first major surface 190a of the cover 190. In one embodiment, the first surface 190a of the shroud is approximately coplanar with the first surface 150a of the second die of the die stack. For example, the cover does not cover the back or first surface of the second die of the die stack. Alternatively, the first surface of the cover need not be coplanar with the first surface of the second die of the die stack. For example, as will be discussed later, the first surface of the shroud is higher than the back side of the second die of the die stack, depending on the thickness of the adhesive layer disposed on the back side of the second die. The bottom surface of the cover is disposed on the non-grain area of the wiring substrate.

In an embodiment, the carrier 185, similar to the carrier of Figure 1, is permanently Placed on the first surface of the second die of the cover and the die stack. The second surface 185b of the carrier contacts at least the first surface of the cover 190a and the first surface 185a of the carrier is exposed. For example, the second surface of the carrier covers substantially the entire first surface of the second die and the cover. An adhesive 175 similar to the adhesive of Figure 1 is disposed on the second surface of the carrier. In one embodiment, the adhesive is disposed between at least the second surface 185b of the carrier and the first surface 150a of the second die. In other embodiments, the adhesive may be disposed between the second surface of the carrier and the cover and the first surface of the die. For example, the adhesive at least permanently engages the carrier and the die stack.

3a-3h show an embodiment of a method for forming a semiconductor package 300. Figure 3a shows a wafer 301 having a first surface 301a and a second surface 301b. The wafer acts as a substrate for forming the die 350. The first surface is, for example, an inactive surface 350a and the second surface is an active surface 350b. Other naming of the surface can also be useful. The wafer, for example, can be a germanium wafer. Other types of semiconductor wafers can also be useful. In an embodiment, the wafer is processed to include a plurality of dies or wafers. For example, a plurality of dies are processed in parallel on a wafer. Illustratively, the wafer includes three dies that are processed in parallel. It may also be useful to provide other numbers of dies or wafers for the wafer.

The die 350 includes circuit components formed on a wafer or substrate. The circuit components include, for example, transistors, resistors, capacitors, and interconnects to form an IC. The final passivation layer can be formed on the die. The final passivation layer includes an opening to expose the die pad 355. The surface of the wafer or substrate that includes the opening to the die pad may be referred to as the active surface of the wafer.

In an embodiment, the sacrificial layer 377 is formed on the active surface of the wafer 301. on. The sacrificial layer is the temporary layer that will be removed later. The sacrificial layer (for example) is an adhesive material. Other types of sacrificial layers can also be useful. The sacrificial layer can be formed on the substrate using various techniques. For example, the sacrificial layer can be provided by spin coating or lamination. Other techniques for forming a sacrificial layer can also be useful. This technique, for example, may depend on the type of sacrificial layer. In an embodiment, the sacrificial layer may be semi-cured to less tacky during the encapsulation process. In other embodiments, the sacrificial layer remains tacky during use to improve adhesion to the support carrier.

The process continues with the wafer that is processed along with the die and sacrificial layers on the active surface of the wafer. The split wafer divides the die into individual dies having a sacrificial layer on the active surface. In another embodiment, the sacrificial layer 377 can be formed on the active surface of the die after dividing the wafer into individual dies.

Referring to Figure 3b, a carrier 385 is provided. In one embodiment, for example, the carrier is a permanent carrier or permanent support for processing the wafer package. In an embodiment, the carrier should be stiff enough to act as a support to permanently hold the die and tolerate further processing steps. For example, the carrier should be stiff enough to reduce or prevent warpage of the wafer assembly during the assembly process. Alternatively or in addition, for example, the carrier can also act as a thermal conductor to dissipate heat from the die of the semiconductor package. As a non-limiting example, the carrier can be a wafer or a conductive plate. For example, the wafer can include a germanium wafer, and the conductive plate can include a metal plate. Various other types of materials can also be used to form the carrier.

The carrier includes a first surface 385b on which the die is processed to form a package. The carrier can be configured in stripe style to process a column of dies. In other embodiments, the carrier is configured to process a plurality of columns of grains. For example, the carrier can have a panel style to form a two dimensional array of packages. Provides wafer style configuration The carrier may also be useful to form a plurality of packages. In some embodiments, the carrier can be configured to form a package, for example, a single style. The type of style selected may depend on, for example, process requirements, available equipment, or cost considerations.

Illustratively, the carrier is configured in a strip pattern having three package areas or regions 380a through 380c for forming three packages. It may also be useful to provide a carrier having a different number of package areas or styles. The package region includes a die region and a non-grain region. The size of the package area is approximately equal to the size of the package. The die 350 coated with the sacrificial layer 377 on the active surface 350b is attached to the die region. For example, three grains 350 ₁ to 350 _{3 are} attached to the grain regions on the permanent carrier.

In one embodiment, an adhesive 375 is disposed on the first surface 385b of the carrier to promote die attach. Other bonding techniques can also be used to attach the die to the carrier. For example, the adhesive is disposed on at least the grain regions on the carrier to permanently hold the wafer assembly to the die regions. In one embodiment, the adhesive is disposed only in the grain region. In other embodiments, the adhesive is disposed substantially over the entire first surface 385b of the carrier.

In other embodiments, the adhesive 375 can be disposed on an inactive surface of the wafer. For example, the adhesive can be applied before or after the wafer is diced into individual dies.

The adhesive can be any type of adhesive that provides permanent bonding of the wafer assembly to the surface of the wafer assembly of the carrier. Adhesive 375 (for example) may comprise the same material as sacrificial layer 377. In other embodiments, the adhesive 375 can comprise a material other than the sacrificial layer. The adhesive may comprise any suitable thickness as long as it can at least permanently bond the die to the carrier during processing. Adhesive can be present different forms. For example, the adhesive can be a film, a paste, a liquid or a thermally conductive adhesive. Adhesives can be provided on the carrier using a variety of techniques or on the inactive surface of the wafer or die. The technique employed may depend on the type or form of the adhesive. For example, the tape adhesive may be provided on the carrier by lamination, the paste adhesive may be provided on the carrier by printing, and the liquid adhesive may be provided on the carrier by spin coating. It may also be useful to use other techniques to attach the adhesive to the carrier and to the active surface of the wafer or die.

In one embodiment, the inactive surface 350a or the back side of the die is attached to the die region of the carrier. The dies are attached to the die area using any suitable technique depending on the equipment and the type of adhesive used.

Referring to Figure 3c, a cover 390 is formed to encapsulate the die. In one embodiment, the cover is disposed in a non-grain region of the permanent carrier. For example, the encapsulating material is dispensed to fill the space between the grains. In an embodiment, the encapsulating material is a molding compound, such as a molded epoxy material. Other types of encapsulating materials may also be useful.

In an embodiment, the cover is formed by a transfer molding technique. In one embodiment, the cover is formed by a film assisted transfer molding technique. For example, the film 393 is placed against the contour of a mold (not shown). In one embodiment, when the carrier and the die are placed against the mold, the film contacts the sacrificial layer on the active surface of the die, leaving the space therebetween in the non-grain region. An encapsulating material, such as a molding compound, is dispensed into the mold assembly to fill the space in the non-grain region to form a jacket. The sacrificial layer protects the active surface of the die from the encapsulation material. After molding, the molded panels of the die are separated from the mold. The sacrificial layer also facilitates the release of the molded panel from the molding tool. For shape Other techniques for forming a cover can also be useful. For example, the cover can also be formed by printing or compression molding.

The mold is removed such that a plurality of dies are attached to each other by the cover 390 and the carrier 385. The carrier provides additional mechanical support to the wafer for further processing. In one embodiment, the surface of the cover is coplanar with the surface of the die. For example, the first surface 390a of the cover is coplanar with the back side of the die or the first surface 350a, and the second surface 390b is coplanar with the active surface of the die or the sacrificial layer 377 on the second surface 350b. Alternatively, the first surface of the cover need not be coplanar with the first surface of the die. For example, depending on the thickness of the adhesive layer 375 disposed on the die region on the surface 385b of the carrier, the first surface 390a of the cover is disposed in a different plane than the back surface 350a of the die. An external heat sink or heat spreader (not shown) may also be attached to the back side 385a of the carrier to further improve heat dissipation.

Referring to Figure 3d, the sacrificial layer 377 is removed. In an embodiment, the sacrificial layer is removed by dissolving the layer with a chemical. For example, a chemical that does not cause any damage to the second surface or the active surface of the die is preferably used to remove the sacrificial layer. Other techniques can also be used to remove the sacrificial layer. The removal of the sacrificial layer exposes the active surface or second surface of the die and die contact pads 355. A cleaning step can be performed as appropriate to clean the second surface of the die and contact pads. For example, a solvent based cleaning step can be applied. Other suitable cleaning techniques can also be useful.

In one embodiment, the second surface 390b of the cover is not coplanar with the active surface 350b of the die. For example, the active surface of the die forms a step 387 with the second surface of the shroud. In an embodiment, the active surface of the die is recessed in Under the surface of the cover. The height of the steps, for example, may be about the thickness of the sacrificial layer. Other step heights can also be useful.

The step reduction between the active surface of the die and the surface of the jacket reduces the mechanical stress due to the difference between the thermal coefficients of the grains and the molding compound in the subsequently formed package.

The process continues to form a package substrate. The process continues, for example, to form a combined or integrated wiring substrate. The package substrate (for example) includes a multilayer substrate. In one embodiment, the first insulating substrate layer 313 is disposed on the second surface of the cover and the active surface of the die. For example, the first surface 313a of the first substrate layer contacts the second surface of the cover and fills the recess on the die.

In an embodiment, the first substrate layer can be a dielectric layer. A dielectric layer, for example, is disposed on the active surface of the die. Other types of first substrate layers may also be useful. The dielectric material can be deposited via suitable techniques such as wafer processing techniques, spin coating, printing, and the like. Other techniques for depositing the first substrate layer can also be useful.

A via 315 is formed in the first substrate layer. The via extends from the second surface 313b through the first surface 313a to expose the die contact pads of the die. In one embodiment, the vias are formed by laser drilling. Other techniques such as mechanical drilling or RIE can also be used. The through holes may have a tapered or straight profile depending on the process requirements and types of through hole forming methods used. In an embodiment, the through holes are formed to have a straight profile. It is also useful to provide a tapered profile (not shown). In particular, the tapering of the sidewalls promotes filling of the vias. For example, the tapered sidewalls promote uniform material coverage of the sidewalls and via bases, which reduces the formation of voids.

Referring to FIG. 3f, the process continues to form conductive via contacts 330 and traces 340 of the package substrate. In an embodiment, the conductive layer is formed on the first substrate layer, covering the second surface thereof and filling the via holes. The conductive layer, for example, can be copper or a copper alloy. Other types of conductive materials can also be used. For example, other types of electrically conductive materials can include aluminum, gold, nickel, or combinations or alloys thereof. The conductive layer can be formed by electroplating. For example, electrochemical or electroless plating can be used to form the conductive layer. Other suitable methods of forming a conductive layer can also be used. In some embodiments, the seed layer can be used prior to forming the conductive layer.

Patterning of the conductive layer can be formed prior to the electroplating process by means of a patterned mask layer. Alternatively, the conductive layer can be patterned to form conductive traces 340 coupled to the substrate via contacts 330 in the vias, the vias being coupled to the die pads of the same die. The conductive traces and via contacts form interconnects. Patterning of the conductive layer can be achieved by any suitable etching technique. For example, a patterned etch mask, such as a photoresist, is provided over the conductive layer. Etching can be performed using an etch mask to remove portions of the conductive layer that are not protected by the etch mask. The etch can be, for example, an isotropic etch, such as a wet etch. An anisotropic etch can be used, such as reactive ion etching (RIE). Other techniques for patterning the conductive layer can also be useful.

After the conductive layer is patterned, the mask is removed. The mask can be removed, for example, by ashing. Other techniques for removing the mask can also be used.

As shown in FIG. 3g, a second insulating substrate layer 317 having a first surface 317a and a second surface 317b is deposited over the first substrate layer to cover and fill the spaces between the conductive traces. The second substrate layer provides insulation between the conductive traces. The first surface 317a of the second substrate layer contacts the first substrate layer. Second substrate layer Acts as a contact mask. In an embodiment, the second substrate is formed of a polymer. The second substrate layer can be formed, for example, by spin coating. Other types of dielectric materials and deposition techniques can also be used to form the second substrate layer.

The second substrate layer is patterned to form contact openings 319 to expose portions of the conductive traces. The contact opening corresponds to the location of the package contacts of the semiconductor package. For example, the contact openings can be configured in a grid pattern to form a BGA type package. Other contact opening patterns can also be useful.

In an embodiment, a package or conductive pad 368 is formed over the exposed portion of conductive trace 340, as shown in Figure 3h. In an embodiment, the package pad comprises a conductive material. In one embodiment, the package pad is selectively formed in the opening of the dielectric layer by coating or plating techniques. Other types of electrically conductive materials or techniques can be used to form the contact pads. The conductive pads are, for example, coplanar with the conductive traces. In other embodiments, the conductive pads can include protruding conductive pads. The conductive pads may be further covered with a surface protective material such as an OSP or metal coating or plating.

The process continues with forming package contacts 370 in the opening of the package mask, as shown in Figure 3h. For example, the package contacts are formed on the package pads 368 in the openings of the package mask. The package contacts, for example, may include spherical structures or balls configured in a grid pattern to form a BGA type package. The package contacts are formed from a conductive material. In an embodiment, the package contacts may be formed from solder. Various types of solder can be used to form the package contacts. For example, the solder can be a lead based or non-lead based solder.

In some embodiments, other types of package contacts are formed in the opening. For example, the package contact may include not protruding from the bottom surface of the second substrate layer. contact. It may also be useful to provide package contacts (such as pads) that do not protrude from the bottom surface of the second substrate layer. The package contacts can be formed from materials other than solder or using other techniques.

In other embodiments, the package contacts can include copper posts or gold stud bumps (not shown). The use of a copper column is advantageous because it does not break after reflow. Thus, the copper posts enable the creation of semiconductor packages with much tighter pitches and more uniform pad heights. On the other hand, gold stud bumps can sometimes be used in combination with anisotropic conductive adhesives and thermocompression bonding methods to achieve tight spacing. This is advantageous because it allows the IC wafer originally designed for the peripheral bond pads intended for wire bonding to be used as flip chip. Other suitable types of package contacts can also be used.

The process continues to singulate the structure to form individual semiconductor packages. Thus, a semiconductor package such as the semiconductor package shown in FIG. 1 is formed.

4a-4c illustrate another embodiment of a process for forming a semiconductor package 400. This process is similar to the process described in Figures 3a through 3h. Thus, common elements may not be described or described in detail. Referring to Figure 4a, a wafer 401 having a die stacked configuration is provided. In an embodiment, the wafer is processed to include a plurality of die stacks 410.

The die stack includes n number of grains, where n 2. The bottom grain, for example, may be referred to as the first (eg, n=1) and the top grain is equal to n. It is also useful to use other specifications to name the die of the die stack. The die stack can be formed, for example, by any suitable type of die stacking method. As shown, the die stack includes a first die 450 ₁ and a second die 450 ₂ . The second die 450 _{2 is} attached to the first die 450 ₁ , and the first die is attached to the die region of the wiring substrate. The grains used for the die stacking may be TSV or non-TSV grains. In an embodiment, both the top and bottom dies may be TSV dies. In yet another embodiment, the bottom die can include TSV die and the top die can include non-TSV die. Non-TSV dies, for example, may include wire bonds, direct connections, flip chip, and the like. For a die stack having more than two grains, the lower grains (bottom grains and intermediate grains except the top grains) are typically TSV grains, while the top grains are non-TSV grains. Other configurations or types of die of the die stack can also be useful.

The TSV die includes a first major surface 450a and a second major surface 450b. The first surface includes a first die contact 433 and the second major surface includes a second die contact 435. The die contact, for example, is a die contact pad having a top surface that is coplanar with the first major surface and the second major surface of the TSV die. It may also be useful to provide a surface that is not in contact with the surface of the die. Other configurations of die contacts or die contact pads may also be useful. The first die contact and the second die contact are interconnected by a via contact 430. Other configurations of TSV die can also be useful. The via contacts and contact pads are formed, for example, of a conductive material. The electrically conductive material, for example, can include copper. Other types of conductive materials can also be used for via contacts and contact pads.

As shown in Figure 4a, the first die contact 433 mates with the second die of the die stack. In an embodiment, a die attach film or primer 417 may be disposed in the recess formed between the dies to facilitate stacking and to protect the conductive die pad 355 and the first die coupled to the second die. The junction of the first die contact 433 is 440. For the case where two or more dies are used to form a grain stack, the bottom and intermediate grains may be TSV grains. Other types of crystal grains can also Used for bottom and intermediate grains. The second die contact of the upper n+1th die is connected to the first die contact of the nth die below.

In one embodiment, the sacrificial layer 377 is formed on the wafer or die stacked on the second major surface 450b 450 ₁ 401 of the first die.

The process continues with wafers that are processed along with the die stack and sacrificial layers on the second surface of the wafer. The split wafer divides the die stack into individual die stacks 410 ₁ through 410 ₃ . Although three die stacks are shown in Figure 4b, it should be understood that other numbers of die stacks may also have a sacrificial layer on the second surface 450b. In another embodiment, the sacrificial layer 377 can be disposed after the wafer is divided into individual die stacks.

Referring to Figure 4b, the process is at a stage similar to that described in Figure 3b. For example, the carrier 385 having the adhesive 375 on the first surface 385b of the carrier has a die stack 410 ₁ to 410 ₃ attached to the die regions on the carrier. In one embodiment, the back side or first surface 350a of the second die of the die stack is attached to and contacts the die area of the adhesive 375 having the carrier 385. The die stack is attached to the die area using any suitable technique depending on the equipment used and the type of adhesive. In an embodiment, the carrier acts as a permanent carrier or permanent support for processing the wafer package. In an embodiment, the carrier should be stiff enough to act as a permanent support for holding the die stack during assembly. Alternatively or in addition, for example, the carrier can also act as a thermal conductor to dissipate heat from the die stack of the semiconductor package. As a non-limiting example, the carrier can include a wafer or a conductive plate. For example, the wafer can include a germanium wafer, and the conductive plate can include a metal plate. Other suitable types of materials may also be used to form the carrier.

In one embodiment, an adhesive 375 is disposed on the first surface of the carrier to facilitate adhesion of the die stack. Other bonding techniques can also be used to permanently bond the die stack to the carrier. For example, the adhesive is disposed at least in the die region on the carrier to permanently hold the wafer assembly to the die regions. In one embodiment, the adhesive is disposed on the grain regions of the carrier. In other embodiments, the adhesive is disposed on the entire first surface of the carrier.

In other embodiments, the adhesive 375 can be disposed on the first surface of the wafer. For example, the adhesive can be applied before or after the wafer is diced into individual die stacks. For example, an adhesive can be applied to the back side or first surface 350a of the second die of the die stack.

As shown in Figure 4c, the process continues until the cover 390 is formed. In an embodiment, the cover is formed from an encapsulating material similar to the material described in Figure 3c. In one embodiment, the cover covers each side of the die stack as shown in Figure 4c.

After the formation of the cover, the process continues, similar to that described in Figure 3d and continues. For example, the process continues until a semiconductor package is formed, as described in Figure 3d, and continues until a semiconductor package as described and illustrated in Figure 2 is produced.

As described with respect to Figures 3a through 3h and Figures 4a through 4c, the process produces several advantages. For example, a sacrificial layer is used to protect the second major surface or active surface of the die or die stack from contamination during molding. In addition, the sacrificial layer acts as a temporary coating that is removed after molding such that the recess is created on the second surface of the die or die stack to relieve heat between the die compound and the die or die stack Mechanical stress caused by mismatch. Also, the process allows various molding techniques (such as printing, transfer, and compression molding) to be used for the shape Form a cover.

Although only one conductive via and trace level is formed and coupled to the die pad of the same die in the package substrate, it will be understood that additional conductive vias and trace levels may be included. For example, the first substrate layer can include a plurality of first sub-layers. Thus, the process enables a plurality of wiring structures to be established in the package substrate as compared to a fan-out process based on an existing wafer that is limited to a single metal layer fan-out structure. Furthermore, since the cover acts as a mechanical support for the die to form a package substrate thereon, and the resulting structure is in the form of a panel or strip, the substrate process can be used to form a redistribution structure on the active surface of the die. Thus, conventional wafer redistribution layer formation processes are not required. This avoids the need for capital investment in new wafer-based processing equipment.

In addition, the carrier acts as a permanent carrier or permanent support to hold the die or die stack during assembly. Thus, the permanent carrier provides additional support for the die or die stack during assembly and during the formation of the redistribution structure on the active surface of the die. In addition, the carrier remains as part of the packaged structure. Thus, the process of forming the semiconductor package is simplified by eliminating the steps of removing the carrier and removing the adhesive from the carrier. Furthermore, depending on the materials used for the carrier, the permanent carrier can also act as a thermal conductor to dissipate heat from the die or die stack of the semiconductor package. Thus, the permanent carrier enables the creation of a semiconductor package with enhanced heat dissipation.

In addition, the permanent adhesive used to bond at least the carrier to the die avoids problems such as resin leakage and also prevents the die from shifting during the molding process used to form the cover. In addition, the process for forming a semiconductor package is further simplified because no additional processing steps are required to remove excess encapsulation. The material is exposed to the first or second surface of the die for further processing.

The present invention may be embodied in other specific forms without departing from the spirit and scope of the invention. Accordingly, the above embodiments should be considered in all aspects of the invention as illustrated and not limited.

100‧‧‧Semiconductor package

110‧‧‧ wiring substrate

111‧‧‧ first major surface

111a‧‧‧First Zone/Grain Zone

111b‧‧‧Second/Non-grain area

112‧‧‧Second major surface

113‧‧‧First insulating substrate layer

113a‧‧‧ first surface

113b‧‧‧second surface

117‧‧‧Second insulating substrate layer

117a‧‧‧ first surface

117b‧‧‧Second surface/bottom

130‧‧‧ Piercing joints

140‧‧‧conductive traces

150‧‧‧ grain

150a‧‧‧First surface/back

150b‧‧‧second main surface

155‧‧‧Electrical die pad

168‧‧‧Electrical mat

170‧‧‧Package joints

175‧‧‧Adhesive

185‧‧‧ Carrier

185a‧‧‧ first surface

185b‧‧‧ second surface

187‧‧‧ steps

190‧‧ ‧ cover

190a‧‧‧First main surface/top surface

190b‧‧‧Second major surface/bottom

200‧‧‧Semiconductor package

210‧‧‧Grade stacking

217‧‧‧ die attach film / primer

230‧‧‧ Piercing joints

233‧‧‧First die contacts

235‧‧‧Second die contacts

240‧‧‧ joint joint

250 ₁ ‧‧‧First grain

250 ₂ ‧‧‧Second grain

250a‧‧‧ first major surface

250b‧‧‧second main surface

300‧‧‧Semiconductor package

301‧‧‧ wafer

301a‧‧‧ first surface

301b‧‧‧ second surface

313‧‧‧First insulating substrate layer

313a‧‧‧ first surface

313b‧‧‧ second surface

315‧‧‧through hole

317‧‧‧Second insulating substrate layer

317a‧‧‧ first surface

317b‧‧‧ second surface

319‧‧‧Contact opening

330‧‧‧conductive via contacts

340‧‧‧conductive traces

350‧‧‧ grain

350a‧‧‧Inactive surface

350b‧‧‧Action surface

350 ₁ ‧‧‧Grain

350 ₂ ‧‧‧Grain

350 ₃ ‧‧‧Grain

355‧‧ ‧ die pad

368‧‧‧Packing mat / conductive pad

370‧‧‧Package joints

375‧‧‧Adhesive

377‧‧‧ sacrificial layer

380a‧‧‧Packing area

380b‧‧‧Packing area

380c‧‧‧Packing area

385‧‧‧ Carrier

385a‧‧‧back

385b‧‧‧ first surface

387‧‧‧ steps

390‧‧‧ Cover

390a‧‧‧First surface/top surface

390b‧‧‧second surface

393‧‧‧film

400‧‧‧Semiconductor package

401‧‧‧ wafer

410 ₁ ‧‧‧Grade stacking

410 ₂ ‧‧‧Grade stacking

410 ₃ ‧‧‧Grade stacking

417‧‧‧ die attach film / primer

430‧‧‧ Piercing joints

433‧‧‧First die contacts

435‧‧‧Second die contacts

440‧‧‧ joint joint

450 ₁ ‧‧‧First grain

450 ₂ ‧‧‧Second grain

450a‧‧‧ first major surface

450b‧‧‧second main surface

A'‧‧‧ part

1 and 2 show various embodiments of a semiconductor package; and FIGS. 3a through 3h and 4a through 4c illustrate various embodiments of a method for forming a semiconductor package.

100‧‧‧Semiconductor package

110‧‧‧ wiring substrate

111‧‧‧ first major surface

111a‧‧‧First Zone/Grain Zone

111b‧‧‧Second/Non-grain area

112‧‧‧Second major surface

113‧‧‧First insulating substrate layer

113a‧‧‧ first surface

113b‧‧‧second surface

117‧‧‧Second insulating substrate layer

117a‧‧‧ first surface

117b‧‧‧Second surface/bottom

130‧‧‧ Piercing joints

140‧‧‧conductive traces

150‧‧‧ grain

150a‧‧‧First surface/back

150b‧‧‧second main surface

155‧‧‧Electrical die pad

168‧‧‧Electrical mat

170‧‧‧Package joints

175‧‧‧Adhesive

185‧‧‧ Carrier

185a‧‧‧ first surface

185b‧‧‧ second surface

187‧‧‧ steps

190‧‧ ‧ cover

190a‧‧‧First main surface/top surface

190b‧‧‧Second major surface/bottom

A'‧‧‧ part

Claims (22)

A method for forming a semiconductor package, comprising: providing at least one die having an active surface and an inactive surface, wherein the active surface of the die comprises a plurality of conductive pads; providing a first planar surface And a planar permanent carrier of a second planar surface; attaching the at least one die to the second planar surface of the planar permanent carrier, wherein the non-active surface of the at least one die faces the planar permanent carrier, the plane being permanent The carrier includes a material that is sufficiently rigid to support the at least one die during assembly; and a cover having a first surface and a second surface to encapsulate the at least one die, wherein the cover is not in contact with the cover The at least one die surrounds the at least one die, the second planar surface of the planar permanent carrier covers the inactive surface of the at least one die and the first surface of the cover, and the cover The second surface is disposed at a plane different from the active surface of the die. The method of claim 1, comprising providing an adhesive on the second planar surface of the planar permanent carrier. The method of claim 2, wherein the adhesive is disposed on at least one of the die regions on the second planar surface of the planar permanent carrier to permanently hold the at least one die to the planar permanent carrier. The method of claim 1, comprising providing an adhesive on the non-active surface of the die. The method of claim 2 or 4, wherein the adhesive comprises a film, a paste Liquid, thermal or thermal adhesive. The method of claim 1, wherein the planar permanent carrier comprises a wafer. The method of claim 1, wherein attaching the at least one die to the planar permanent carrier is performed prior to forming the cover. The method of claim 1, comprising forming a sacrificial layer that directly contacts the active surface of the at least one die. The method of claim 8, comprising removing the sacrificial layer after forming the cover. The method of claim 1, wherein the cover is formed by one of molding techniques including transfer molding or compression molding. The method of claim 1, comprising forming a combined package substrate, the package substrate comprising at least one first patterned substrate layer having a first surface and a second surface, wherein the first patterned substrate layer The first surface includes a die region and a non-grain region defined by the first surface of the same first patterned substrate layer, wherein the die region is disposed in The non-grain region has a different plane, and wherein the active surface of the at least one die directly contacts the first surface of the first patterned substrate layer in the die region. The method of claim 11, wherein the first patterned substrate layer comprises: a via hole located therein, an interconnect structure having substrate via contacts disposed in the vias, and having a first patterned substrate disposed thereon a conductive trace on the second surface of the layer, and the plurality of conductive pads of the die, the plurality of conductive pads are directly coupled The substrate is pierced to the contacts and in contact with the substrate via contacts. A method for forming a semiconductor package, comprising: providing a wafer having a plurality of die stacks, the plurality of die stacks having an active surface and an inactive surface, wherein the active surface of the die stack comprises a plurality of conductive pads; singulating the wafer into individual die stacks; providing a planar permanent carrier having a first planar surface and a second planar surface; attaching the die stack to the planar permanent carrier a second planar surface, wherein the non-active surface of the die stack faces the planar permanent carrier, the planar permanent carrier comprising a material that is sufficiently hard to support the die stack during assembly; and formed to have a first surface and a a cover of the second surface to encapsulate the die stacks, wherein the cover is stacked around the die without contacting the active surface of the die stack, the second planar surface of the planar permanent carrier Covering the inactive surface of the die stack and the first surface of the cover, and the second surface of the cover is disposed differently from the active surface of the die stack A plane. The method of claim 13 which includes disposing an adhesive on the second planar surface of the planar permanent carrier. The method of claim 14, wherein the adhesive is disposed on at least a die region on the second planar surface of the planar permanent carrier to permanently hold the die stack to the planar permanent carrier. The method of claim 13, comprising: disposing an adhesive on the die Stacked on the non-active surface. The method of claim 14 or 16, wherein the adhesive comprises a film, a paste, a liquid or a thermally conductive adhesive. The method of claim 13, wherein the planar permanent carrier comprises a wafer. The method of claim 13, wherein attaching the die stack to the planar permanent carrier is performed prior to forming the cover. The method of claim 13, comprising forming a sacrificial layer that directly contacts the active surface of the die stack. The method of claim 13, comprising forming a combined package substrate, the package substrate comprising at least one first patterned substrate layer having a first surface and a second surface, wherein the first patterned substrate layer The first surface includes a die region and a non-grain region defined by the first surface of the same first patterned substrate layer, wherein the die region is disposed in The non-grain region has a different plane, and wherein the active surface of the die stack directly contacts the first surface of the first patterned substrate layer in the die region. The method of claim 21, wherein the first patterned substrate layer comprises: a perforation therein, an interconnect structure having substrate via contacts disposed in the vias, and having a first patterned substrate disposed thereon Conductive traces on the second surface of the layer, and the plurality of conductive pads of the die stack, the plurality of conductive pads are directly coupled to the substrate via contacts and in contact with the substrate via contacts .