KR20190013578A - Semiconductor packages and methods of forming same - Google Patents

Abstract

In one embodiment, a package comprises: a first die having a first active side and a first back surface; a second die bonded to the first die with a second active side and a second back surface; and a conductive bonding material. The first active side includes a first bonding pad and a first insulation layer. The second active side includes a second bonding pad and a second insulation layer. The second active side of the second die faces a first active side of the first die, and the second insulation layer bonds to the first insulation layer by dielectric-dielectric bonding. The conductive bonding material is bonded to the first bonding pad and the second bonding pad. The conductive bonding material has a reflow temperature lower than a reflow temperature of the first and the second bonding pads.

Description

Technical Field [0001] The present invention relates to a semiconductor package and a method of forming the same.

This application claims the benefit of U.S. Provisional Patent Application No. 62 / 537,736, filed July 27, 2017, entitled "Semiconductor Package and Method Forming It ", which is incorporated herein by reference.

The semiconductor industry is experiencing rapid growth with continuous improvement of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in the integration density results from a recurring decrease in the minimum linewidth size that allows more components to be integrated within a given area. As the demand for shrinking electronic devices grows, there is a need for a smaller and more creative semiconductor die packaging technology. An example of such a packaging system is a charge-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a bottom semiconductor package to provide a high degree of integration and component density. PoP technology typically allows for the fabrication of semiconductor devices with reduced functionality on a printed circuit board (PCB) with enhanced functionality.

Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. According to standard practice in the industry, various features are not written in proportion. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Figures 1-3, 4a-4o, 5-14 illustrate intermediate cross-sectional views during the process for forming a package structure according to some embodiments.
FIGS. 15-21 illustrate intermediate cross-sectional views during the process for forming a package structure in accordance with some embodiments.
Figures 22-28 illustrate intermediate cross-sectional views during the process for forming a package structure in accordance with some embodiments.
29-34 illustrate intermediate cross-sectional views during the process for forming a package structure in accordance with some embodiments.
35-38 illustrate intermediate cross-sectional views during the process for forming a package structure in accordance with some embodiments.

The following description provides a number of different embodiments or examples for the implementation of various other features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on the second feature may include an embodiment in which the first and second features are formed in direct contact, and the first and second features may not be in direct contact So that additional features may be formed between the first and second features. In addition, the present disclosure may repeat the reference numerals and / or characters in various instances. Such repetitions are for simplicity and clarity and do not in themselves indicate the relationship between the various embodiments and / or configurations discussed.

Also, spatial relation terms such as "below" (e.g., beneath, below, lower), "above" (e.g., above, upper), etc. may be used herein to refer to other element (s) May be used for ease of description which describes the relationship of one element or feature to another. Spatial relationship terms are intended to encompass other orientations of the element in use or in operation, in addition to the orientation represented in the figures. The device can be oriented differently (90 degrees rotation or other orientation), and the spatial relationship descriptor used here can be similarly interpreted accordingly.

The embodiments discussed herein will be discussed in the context of a package structure (e.g., a package-on-package (PoP) structure) that includes a die bonded using a hybrid bonding technique. The dies can be face-to-face (F2F) or face-to-back (F2B) bonded. For example, in the F2F bonding configuration, the active side (front side) of the dies are bonded together, while in the F2B bonding configuration the active side of one die is bonded to the back side of the other die. In addition, the hybrid bonding between the die includes inter-dielectric bonding and metal bonding. For example, by including solder bonding (e.g., instead of copper-to-copper bonding), the bonding temperature of the hybrid bonding can be greatly reduced.

In addition, the teachings of the present disclosure may be applied to any package structure including one or more semiconductor dies. Other embodiments contemplate other applications, such as other package types or other configurations, which will be apparent to those of ordinary skill in the art having the benefit of this disclosure. It is to be understood that the embodiments discussed herein are not necessarily illustrative of all components or features that may be present in the structure. For example, a number of components may be omitted in the figures if the discussion of one of the components is sufficient to state various aspects of the embodiment. In addition, while the method embodiments discussed herein may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Figures 1-3, 4a-4o, 5-14 illustrate intermediate cross-sectional views during the process for forming a package structure according to some embodiments.

Figure 1 illustrates an integrated circuit die 100 at an intermediate stage during processing. The integrated circuit die 100 may be a logic die (e.g., a central processing unit, a mobile application processor, an ASIC, a GPU, an FPGA, a microcontroller, etc.), a memory die such as a dynamic random access memory , Memory die (e.g., HBM, HMC, etc.), high speed data transceiver die, I / O interface die, IPD die (e.g., M-RAM die, R-RAM die, NAND die, static random access memory (E.g., integrated passive devices), power management dies (e.g., power management integrated circuit (PMIC) die), high frequency (RF) die, sensor die, micro- (DSP) die), a front-end die (e.g., an analogue user side (AFE) die), a monolithic 3D xerographic chiplet lamination die, or the like, or a combination thereof.

Prior to the intermediate steps illustrated in FIG. 1, the integrated circuit die 100 may be processed according to a fabrication process applicable to form an integrated circuit on the integrated circuit die 100. For example, the integrated circuit die 100 includes a semiconductor substrate 102 such as an active layer of a doped or undoped silicon or semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials such as germanium; A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphorus, indium phosphorus, indium arsenide, and / or indium antimony; An alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, and the like may be formed in and / or on top of the semiconductor substrate 102, such as, for example, wirings formed by wiring patterns in one or more dielectric layers on a semiconductor substrate 102 They can be interconnected by a structure to form an integrated circuit. The interconnect structure is formed in some embodiments using a damascene and / or dual damascene process.

The integrated circuit die 100 further includes pads 104, such as copper pads or aluminum pads or combinations thereof where external connections are formed. In some embodiments, these pads 104 may be used in a hybrid bonding configuration to bond the integrated circuit die 100 to another die or structure. The pad 104 is on top of what can be referred to as the active surface of the integrated circuit die 100. The insulating layer is also on the active surface of the integrated circuit die 100. In some embodiments, the insulating layer is formed of a polymer that can be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In another embodiment, the insulating layer comprises a nitride such as silicon nitride; Oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG); A combination of these, and the like. The insulating layer may be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like, or a combination thereof.

In some embodiments, the pad 104 may be referred to as a die connector 104 and may be a conductive pillar (e.g., including a metal such as copper). The pad 104 may be formed by, for example, metal deposition, plating, a combination thereof, or the like. The active surface of the integrated circuit die 100 (including the pad 104 and the insulating layer) may be planarized by a planarization process such as chemical mechanical polishing (CMP) to ensure a planar surface for subsequent bonding.

FIG. 1 also illustrates a conductive filler 106 formed on a portion of a pad 104. As illustrated, the conductive filler 106 may be tapered from top to bottom due to the high aspect ratio of the filler and relatively small dimensions. The conductive filler 106 will extend through the subsequently formed encapsulant 390 (see FIG. 6) and may be referred to as through vias 106 hereafter. As an example of forming the through vias 106, a seed layer is formed on the active surface of the integrated circuit die, such as wiring and pad 104 as shown. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer of a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating, lamination, or the like, and may be exposed to light for patterning. The photoresist pattern corresponds to the through vias. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metals such as copper, nickel, titanium, tungsten, aluminum, combinations thereof, and the like. Various portions of the seed layer on which no conductive material is formed and the photoresist are removed. The photoresist can be removed, for example, by an acceptable ashing or stripping process using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by using an acceptable etching process, such as, for example, wet or dry etching. The remaining portion of the seed layer and the conductive material form through vias 106.

In some embodiments, the pad 104 with the conductive filler 106 formed thereon is formed in a different configuration than the pad 104 without the conductive filler 106 (e.g., the pad 104 with the conductive filler formed thereon, The recesses may not be formed as illustrated by the recessed pad 312 of FIG. 4a). In some embodiments, the pads 104 are all formed in the same configuration.

Figure 2 illustrates an integrated circuit die 200 at an intermediate stage of processing. The integrated circuit die 200 may be any type of semiconductor die such as a logic die (e.g., a central processing unit, an ASIC, an FPGA, a microcontroller, etc.), a memory die (e.g., DRAM die, wide I / O die, M- (E.g., PMIC die), a power management die (e.g., a PMIC die), a memory module (e.g., (E.g., an RF die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), a monolithic 3D xerographic chiplet lamination die, Lt; / RTI > In some embodiments, the integrated circuit die 100 is a logical die and the integrated circuit die 200 is a memory die.

2, the integrated circuit die 200 may be processed according to a fabrication process applicable to form an integrated circuit on the integrated circuit die 200. For example, the integrated circuit die 200 includes a semiconductor substrate 202, such as an active layer of a doped or undoped silicon or semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 may include other semiconductor materials such as germanium; A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphorus, indium phosphorus, indium arsenide, and / or indium antimony; An alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, and the like may be formed in and / or on top of the semiconductor substrate 202, for example, a wiring structure formed by wiring patterns in one or more dielectric layers on the semiconductor substrate 202 So that an integrated circuit can be formed. The interconnect structure is formed in some embodiments using a damascene and / or dual damascene process.

The integrated circuit die 200 further includes a through via 204 and a pad 206. Through vias 204 may extend through semiconductor substrate 202 at this point in the process or partially extend through semiconductor substrate 202 at this point in the process as illustrated in FIG. In this particular embodiment, the semiconductor substrate 202 may be thinned to allow the through vias 204 to extend through the semiconductor substrate 202 (e.g., see FIG. 11). The through vias 204 may be formed, for example, by etching the openings in the substrate 202 and then depositing a conductive material in the openings. These openings for through vias 204 can all be formed simultaneously or in separate processes in the same process. The openings in the substrate 202 may be formed using suitable photolithographic masks and etching processes. For example, a photoresist may be formed and patterned on the substrate 202, and one or more etch processes (e.g., a wet etch process) may be performed to remove the portion of the substrate 202 on which the via vias 204 are desired to be formed Or dry etching process) is utilized. The openings may be formed from the active surface of the integrated circuit die 200 (i.e., the lower side of the integrated circuit die 200 of FIG. 2) by forming and patterning a mask on the active surface of the integrated circuit die 200 have.

The opening may be filled with a liner, such as, for example, a diffusion barrier layer, an adhesive layer, and the like, and combinations thereof. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The liner may be formed using chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD). However, other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD) may be applied.

The conductive material of through vias 204 may include one or more conductive materials, copper, copper alloy, silver, gold, tungsten, aluminum, nickel, other conductive metals, combinations thereof, and the like. The conductive material may be formed, for example, by depositing a seed layer (not shown) and depositing a conductive material on the seed layer using electroplating, electroless plating, etc. to fill and overcharge the openings for the via vias 204 have. Once the openings for the via vias 204 are filled, the excess liner and excess conductive material outside the openings for the via vias 204 may be removed through a polishing process, such as chemical mechanical polishing (CMP) Any suitable removal process can be used. As will be appreciated by one of ordinary skill in the art, the above-described process for forming the through vias 204 is only one way of forming the through vias 204, and other methods are fully intended to be included within the scope of the embodiments. In some embodiments, the through vias 204 are formed from the back side of the integrated circuit die 200.

It should be noted that although two through vias 204 are illustrated in the integrated circuit die 200, there may be more or fewer through vias 204 in each integrated circuit die 200.

The pad 206 may be a copper pad or an aluminum pad, or a combination thereof, in which an external connection portion is formed. In some embodiments, these pads 206 may be used in a hybrid bonding configuration to bond the integrated circuit die 200 to another die or structure. The pad 206 is on top of what can be referred to as the active surface of the integrated circuit die 200. The pad 206 may be formed on the through via 204 to be electrically coupled to the through via. One or more insulating layers 208 are also on the active surface of the integrated circuit die 200. The insulating layer 208 may be an inorganic layer or an organic layer. In some embodiments, the insulating layer 208 is formed of a polymer that can be a photosensitive material such as PBO, polyimide, BCB, and the like. In another embodiment, the insulating layer 208 may comprise a nitride such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, BPSG; . The insulating layer 2008 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The active surface of the integrated circuit die 200 (including the pad 206 and the insulating layer 208) can be planarized by a planarization process such as CMP to ensure a planar surface for subsequent bonding.

In some embodiments, the pad 206 may be referred to as die connector 206 and may be a conductive pillar or via (e.g., including a metal such as copper, aluminum, or combinations thereof). The pad 206 may be formed, for example, by plating or the like. In some embodiments, either or both of the pad 104 and the pad 206 comprise a braze material to be used in joining the integrated circuit die 100, 200. This structure will be described in more detail in Figures 4a-4o.

FIG. 3 illustrates an integrated circuit die 200 that is bonded to an integrated circuit die 100 through hybrid bonding. To achieve hybrid bonding, the integrated circuit die 100, 200 is first pre-bonded by an insulating layer on its active face (e.g., 208) by lightly pressing the respective integrated circuit die 100, 200 together. Although one integrated circuit die 100 and one integrated circuit die 200 are illustrated, the hybrid bonding may be performed at a wafer level (e.g., a chip on a wafer or a wafer on a wafer) and an integrated circuit die 100 and a plurality of integrated circuit dies 200 that are the same as the illustrated integrated circuit die 200 are pre-bonded and arranged in rows and columns on the wafer.

After all of the integrated circuit dies 100 and 200 have been pre-bonded, the reflow of the braze material (i.e., the braze material between the pads 104 and 206) and the reflow of the solder material and at least one of the pads 104 and 206 A reflow process is performed to cause interdiffusion. The reflow temperature can be lowered to less than about 200 ° C to avoid damage to the insulating layer and the bonding die. For example, the reflow temperature may range from about 150 ° C to about 200 ° C. The annealing time can be from about 2 hours to about 3 hours. According to some embodiments, the bonding interface is locally heated to reduce the thermal-mechanical stresses and bonding time at the bonding connection due to the mismatch of the coefficient of thermal expansion (CTE) between the top circuit die, the bottom circuit die, and the bonding tool Thermal compression bonding (TCB) can be applied.

Through hybrid bonding, the pads 104 and 206 are bonded to each other via solder bonding to form the bonding connection 300. The insulating layer of the integrated circuit die 100 is also bonded to the insulating layer 208 by bonding therebetween. For example, one atom of the insulating layer (e.g., an oxygen atom) forms a chemical bond or a covalent bond (e.g., O-H bond) with the other atom of the insulating layer (e.g., hydrogen atom). The resulting bond between the insulating layers is a dielectric-to-dielectric bond, which in various embodiments may be an inorganic-polymer bond, a polymer-polymer bond, or an inorganic-inorganic bond. In addition, since the surface insulation layers of the two integrated circuit dies 100 and / or 200 are different (e.g., one is a polymer layer and the other is an inorganic layer), two types of inorganic-polymer , Polymer-polymer and inorganic-inorganic bonds may be present.

4a. 4b, 4c, 4d, 4e, 4f, 4g, 4h, 4i, 4j, 4k, 4l, 4m, 4n, and 4o illustrate detailed configurations of the bonding connection unit 300 different from those of FIG. In each illustrated configuration, the integrated circuit die 100, 200 may include, for example, a top die (i.e., a die on the bonding interface 350) of Figs. 4a-4o or a bottom die (E.g., a die underneath 350).

4A illustrates a bonding connection configuration 300A by a bonding pad with dielectric bonding and recesses formed. 4A, the first die comprises a semiconductor substrate 302, dielectric layers 304, 308 and 310 on the semiconductor substrate 302, a wiring layer in the dielectric layer 304 and a wiring layer 306 in the dielectric layer 310 And a bonding pad 312 provided with a recess provided thereon. 4A, the second die includes a semiconductor substrate 320, dielectric layers 322, 326 and 328 on the semiconductor substrate 320, a wiring layer 324 in the dielectric layer 322, A bonding pad 330 on the substrate 324, and a layer 332, 334. The interface 350 represents the bonded interface between the dielectric layers 310 and 328.

In this embodiment, the dielectric layers 304, 308, 310, 322, 326, 328 may include nitride, such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, BPSG; And so on. The dielectric layers 308 and 326 may be utilized as an etch stop layer when forming the bonding pads 312 and 330 on each die and may be formed with a different material composition than the peripheral dielectric layer. The surfaces of the dielectric layers 310 and 328 (including the respective conductive portions 330 and 312) at the bonding interface 350 can be planarized by a planarization process such as CMP to ensure a plane for bonding.

The wiring layers 306 and 324 and the bonding pads 330 may be formed of a conductive material, and the conductive material may include a metal such as copper, titanium, tungsten aluminum, and the like. The conductive material may be formed by plating, sputtering, or the like, such as electroplating or electroless plating. These structures may be formed by a damascene process and may include a diffusion barrier layer or adhesive layer, etc., a seed layer and a conductive material. The diffusion barrier layer and / or the adhesive layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, and the like. The diffusion barrier layer and / or the adhesive layer may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering or MOCVD may be used. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like.

The recessed bond pad 312 may comprise a plurality of layers formed in the recess of the dielectric layer 310. The layers may include a seed layer 312A, a diffusion barrier layer 312B, and a conductive material layer 312C. In addition, a diffusion barrier layer and / or an adhesive layer may be present between the seed layer 312A and the dielectric layer 310. [

The diffusion barrier layer and / or the adhesive layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, and the like. The diffusion barrier layer and / or the adhesive layer may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering or MOCVD may be used.

In some embodiments, the seed layer 312A is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers of different materials. In some embodiments, the seed layer 312A comprises a titanium layer and a copper layer over the titanium layer. The seed layer 312A may be formed using, for example, PVD or the like.

In some embodiments, the diffusion barrier layer 312B includes a nickel layer. The diffusion barrier layer 312B may be formed using PVD or the like. The diffusion barrier layer 312B provides diffusion protection so that the braze material 334 does not diffuse into the wiring layer 306. [ Other materials may be used instead of diffusion barriers if they provide adequate degree of diffusion protection.

The conductive material layer 312C may comprise one or more conductive materials, copper, copper alloy, silver, gold, tungsten, aluminum, nickel, other conductive metals, and the like. The conductive material layer 312C can be formed, for example, by forming a conductive material by electroplating, electroless plating or the like. The layers 312A, 312B and 312C of the bonding pad 312 do not fill the recesses in the dielectric layer 310 such that the bonding pads 312 form a recess in the dielectric layer 310. [ This recessed bonding pad 312 may allow for a thinner package by reducing the spacing of the bonded package. After formation of the conductive material layer 312C, excess portions of the out-of-recess layers 312A, 312B, and 312C (e.g., along the top surface of the dielectric layer 310 before the die is bonded) Can be removed through the process. In this embodiment, the combined thickness of layers 312A, 312B, and 312C is less than the thickness of the dielectric layer.

The bump layers 332 and 334 include a diffusion barrier layer 332 and a braze layer 334. A diffusion barrier layer 332 may be formed on the bonding pad 330. In some embodiments, the diffusion barrier layer 332 comprises a nickel layer. The diffusion barrier layer 332 may be formed using, for example, PVD or the like. The diffusion barrier layer 332 provides diffusion protection so that the braze material 334 does not diffuse into the pad / via 330. Other materials may be used instead of diffusion barriers if they provide adequate degree of diffusion protection.

A solder layer 334 may be formed on the diffusion barrier layer 332. The braze layer 334 may be formed of a braze material comprising copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. The solder layer 334 may be formed by evaporation, electroplating, printing, solder transfer, ball placement, or the like. The solder layer 334 is bonded to the recessed bond pads through a solder reflow process (as described above) or a thermal compression bonding process. The solder layer 334 has a lower reflow temperature than both the conductive material layer 312C of the bonding pad 312 and the pad /

4A-4O include voids or gaps 336 surrounding the braze layer 334 and between the bonding pads 312 and the dielectric layers 322/328. This void / gap 336 may be in an uncharged state and can be observed in the final product.

FIG. 4B illustrates another configuration 300B of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4A except that in this embodiment the bonding interface 350 comprises a polymer layer 340, 342 instead of a dielectric layer, and thus includes polymer bonding. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, each die comprises a polymer layer as a bonding layer. A polymer layer 340 is formed on the first die, and a polymer layer 342 is formed on the second die. The polymer layers 340 and 342 may be photosensitive materials such as PBO, polyimide, BCB, and the like. The polymer layers 340 and 342 may be formed by spin coating, lamination, or the like, or a combination thereof.

FIG. 4C illustrates another configuration 300C of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4B except that in this embodiment the bonding pads 312 are not recessed into the insulating layer. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, the bonding pads 312 are substantially planar across the wiring layer 306 without recess formation. The polymer layer 340 extends over the upper surface of the bonding pad 312 so that the bump layers 332 and 334 have a space between the bonding pad 312 and the pad / via 324, 2 die < / RTI >

4D illustrates another configuration 300D of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4A except that the dielectric layers 310 and 328 are separate from each other in this embodiment, so that the bonding interface 350 is solder bonding rather than dielectric bonding. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, the dielectric layers 310, 328 of the die are spaced apart from each other after the bonding process. This embodiment is not necessarily ideal because the standoff height may be higher and the bonding strength may be reduced compared to other embodiments.

FIG. 4E illustrates another configuration 300E of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4A except that in this embodiment the wiring layer 306 is provided to be electrically coupled over the through vias 204 / through vias 466 (see FIG. 15 for 466) similar. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, the through vias 204 / through vias 466 are formed through one of the integrated circuit die 100 and / or 200.

FIG. 4F illustrates another configuration 300F of the bonding connection 300 of FIG. This embodiment differs from the embodiment of FIG. 4E except that in this embodiment, the wiring layer 306 is omitted and the through vias 204 / through vias 466 are directly coupled to the recessed pads 312 similar. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, the width of the via vias 204/466 adjacent to the recessed pad 312 is less than the width of the recessed pad 312.

FIG. 4G illustrates another configuration 300G of the bonding connection 300 of FIG. The present embodiment is similar to the embodiment described above except that in this embodiment the width of the via vias 204/466 adjacent to the recessed pad 312 is greater than the width of the recessed pad 312 4f. ≪ / RTI > The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

Figure 4h illustrates another configuration 300H of the bonding connection 300 of Figure 3. This embodiment differs from the first embodiment in that the width of the through vias 204 / through vias 466 adjacent to the recessed pad 312 is the same as the width of the recessed pad 312 in this embodiment. Is similar to the embodiment of Figure 4f. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

Figure 4i illustrates another configuration 300I of the bonding connection 300 of Figure 3. This embodiment is similar to the embodiment of FIG. 4F except that there are two or more through vias 204 / through vias 466 adjacent to the recessed pad 312 in this embodiment. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

Figure 4J illustrates another configuration 300J of the bonding connection 300 of Figure 3. This embodiment is similar to the embodiment of FIG. 4E except that there are two or more through vias 204 / through vias 466 adjacent to the recessed pad 312 in this embodiment. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

4K illustrates another configuration 300K of the bonding connection 300 of FIG. This embodiment differs from the first embodiment in that the width of the through vias 204 / through vias 466 adjacent to the recessed pad 312 is the same as the width of the recessed pad 312 in this embodiment. 4J. ≪ / RTI > The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

FIG. 4L illustrates another configuration 300L of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4F except that in this embodiment the recessed pad 312 is omitted and the solder material 334 is directly coupled to the through via / via 466 . The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In this embodiment, the through vias 204 and the through vias 466 are formed such that a portion of the solder paste 334 extends below the top surface of the through vias 204/466 and / Seth can be formed. In some embodiments, the width of the void 336 is greater than the width of the through vias 204/466 adjacent the braze material 334.

FIG. 4M illustrates another configuration 300M of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4I except that the width of the void 336 in this embodiment is less than the width of the through vias 204/466 adjacent to the braze material 334. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

Figure 4n illustrates another configuration 300N of the bonding connection 300 of Figure 3. This embodiment is similar to the embodiment of FIG. 41 except that in this embodiment the width of the void 336 is equal to the width of the through vias 204/466 adjacent to the braze material 334. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

4O illustrates another configuration 300O of the bonding connection 300 of FIG. This embodiment is similar to the embodiment of FIG. 4J except that in this embodiment, the recessed pad 312 is omitted and the solder material 334 is directly bonded to the wiring layer 306. The detailed configuration of this embodiment similar to the above-described embodiment will not be repeated here.

In each of the constructions of Figures 4a, 4b, 4c, 4e ~ 4o, the hybrid bonding is performed by applying an insulating layer (e. G., 310, 328, 340, and / or 342) to the active surface of the die by tightly pressing the integrated circuit die together. Bonding the first and second substrates to each other. After the pre-bonding, a reflow process is performed to cause reflow of the solder layer 334.

In Fig. 5, an encapsulant 390 is formed on the various components of Fig. The encapsulant 390 can be a molding component, epoxy, oxide, etc. and can be applied by compression molding, transfer molding, lamination, fluidized CVD, and the like. In some embodiments, the encapsulant may be, for example, an oxide layer such as silicon oxide, tetraethylorthosilicate (TEOS) silicon oxide, and the like. In some embodiments, the encapsulant may be, for example, a nitride layer such as silicon nitride. In some embodiments, the encapsulant may be a complex such as organic and inorganic encapsulants. The encapsulant 390 may be formed on the wafer including the integrated circuit die 100 such that the conductive filler 106 and the integrated circuit die 200 are embedded or covered. The encapsulant 390 may then be cured. The semiconductor substrate 102 of the integrated circuit die 100 may have a thickness (T1) of about 775 [mu] m.

In Fig. 5, the semiconductor substrate 102 may be thinned to a thickness T2 smaller than the thickness T1. Such a thinning process may include an abrasive process such as mechanical polishing, CMP, etch process, or a combination thereof. In some embodiments, the thickness T2 ranges from about 50 microns to about 150 microns.

After the thinning process, the package including the integrated circuit die 100, 200 is singulated by, for example, sawing or dicing cut, so that each package 392 is integrated with at least one integrated circuit die 100 and one integrated A plurality of packages including the circuit die 200 can be formed. In some embodiments, the fragmentation occurs in scribe lines between package areas.

Figure 7 illustrates a carrier substrate 400, a release layer 402 formed on a carrier substrate 400, and a dielectric layer 404 formed on the release layer 402. The carrier substrate 400 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 400 may be a wafer, and thus multiple packages may be formed on the carrier substrate 400 at the same time. Release layer 402 may be formed of a polymeric material that may be removed with the carrier substrate 400 from a coating structure to be formed in a subsequent step. In some embodiments, the release layer 402 is an epoxy based thermal-relief material that, like a photo-thermal conversion (LTHC) release coating, dissipates its adhesion during heating. In another embodiment, the release layer 402 may be a UV adhesive that loses its adhesion upon exposure to UV light. The release layer 402 may be a liquid film that is dispensed and cured as a liquid, or laminated to the carrier substrate 400, or a similar configuration. The top surface of the release layer 402 can be planarized and can have a high level of coplanarity.

A dielectric layer 404 is formed on the release layer 402. The bottom surface of the dielectric layer 404 may be in contact with the top surface of the release layer 402. In some embodiments, the dielectric layer 404 is formed of a polymer such as PBO, polyimides, BCB, and the like. In another embodiment, the dielectric layer 404 may comprise a nitride such as silicon nitride; Silicon oxides, oxides such as PSG, BSG, and BPSG. The dielectric layer 404 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, or other methods, or combinations thereof. In some embodiments, one or more wiring patterns are formed on or in the dielectric layer 404 to form a wiring structure. This re-wiring structure can be referred to as a rear side re-wiring structure.

Also, in Fig. 7, an electrical connection portion 406 is formed. The electrical connection 406 may extend through the subsequently formed encapsulant 408 (see FIG. 9) and then be referred to as through vias 406. As an example of forming via vias 406, a seed layer is formed over a substructure, e.g., dielectric layer 404. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer of a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating, lamination, or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to through vias 406. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Various portions of the seed layer on which no conductive material is formed and the photoresist are removed. The photoresist can be removed, for example, by an acceptable ashing or stripping process using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by using an acceptable etching process, such as, for example, wet or dry etching. The remaining portion of the seed layer and the conductive material form through vias 406.

In Fig. 8, a package 392 is attached to the release layer 402. Fig. It should be appreciated that although one package 392 is illustrated as being attached, more or fewer packages 392 may be attached to each package area. Although not shown, the package 392 may be attached by an adhesive layer (not shown). The adhesive may be any suitable adhesive, epoxy, die attach film (DAF), and the like.

In Fig. 9, an encapsulant 408 is formed on various components. The encapsulant 408 may be a molding component, epoxy, or the like and may be applied by compression molding, lamination, transfer molding, and the like. The encapsulant 408 may be formed on the carrier substrate 400 such that the electrical connections 406 and the package 392 are embedded or covered. The encapsulant 408 may then be cured. The encapsulant 408, 390 may be formed of the same material or another material.

10, the encapsulant 408 may be subjected to a polishing process to expose the electrical connections 406, the conductive filler 106, and the through vias 204. The surfaces of the electrical connections 406, the conductive filler 106, the through vias 204, the semiconductor substrate 202 and the encapsulant 408 are the same after the polishing process. In some embodiments, polishing may be omitted if, for example, electrical contact 406, conductive filler 106 and through vias 204 are already exposed. Electrical connection 406 and conductive filler 106 may then be referred to as through vias 406 and 106, respectively.

In Fig. 11, the front side wiring structure body 410 is formed. The front side wiring structure 410 includes at least one dielectric layer 414 and at least one wiring pattern 412.

The formation of the front side wiring structure 410 can be started by depositing the dielectric layer 414 on the sealing material 408, the through vias 406, the through vias 204 and the through vias 106. [ In some embodiments, the through vias 106,204 may have conductive pads formed thereon to help the top wiring pattern 412 formed and to be electrically coupled with the respective via vias 106,204 23, in the case of the pad 494). In some embodiments, the dielectric layer 414 is formed of a polymer that can be a photosensitive material such as PBO, polyimide, BCB, etc. that can be patterned using a lithographic mask. In another embodiment, dielectric layer 414 may include a nitride such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, BPSG; . The dielectric layer 414 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof.

Next, the dielectric layer 414 is patterned. The patterning forms openings that expose portions of the through vias 406, 106, 204. Patterning may be performed, for example, by exposing the dielectric layer 414 to light when the dielectric layer 414 is a photosensitive material, for example, by ablation using laser ablation or by etching, for example, using anisotropic etching Can be done by an acceptable process. If the dielectric layer 414 is a photosensitive material, the dielectric layer 414 may be developed after exposure.

Next, a wiring pattern 412 having a via is formed on the dielectric layer 414. A seed layer (not shown) is formed in the opening through the dielectric layer 414 and the dielectric layer 414 as an example of forming the wiring pattern 4120. In some embodiments, the seed layer is a metal layer, In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may comprise, for example, PVD or the like. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist may be formed by patterning the wiring pattern Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed within the openings of the photoresist and over exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating, etc. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. Thereafter, a seed material having no conductive material formed thereon The photoresist may be removed by an acceptable ashing or stripping process using, for example, an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer may be removed, for example, Such as wet or dry etching. The remaining portion of the seed layer and the conductive material form vias and wiring patterns 412. Vias may be formed in the openings through the dielectric layer 414, Vias 406, 106, and 204, respectively.

This process can be repeated on more dielectric layers 414 and more wiring patterns and vias 412 to continue the formation of the rewiring structure 410. The materials and processes used to form these layers of the rewiring structure 410 may be similar to those described above, so the description thereof is not repeated herein. In some embodiments, the rewiring structure 410 is formed by a damascene process. In some embodiments, some of the layers of the rewiring structure 410 are formed by a dual damascene process and the remaining layers are formed by the foregoing process, such as, for example, a semi-additive process (SAP) .

The front layer re-wiring structure 410 is shown as an example. More or fewer dielectric layers and wiring patterns can be formed on the front side wiring structure 410. [ When fewer dielectric layers and wiring patterns are formed, the above-described steps and processes may be omitted. Once more dielectric layers and wiring patterns are formed, the steps and processes described above can be repeated. One of ordinary skill in the art will readily understand what steps and processes may be omitted or repeated.

12, a pad (not shown) is formed on the outer side of the front side wiring structure 410 and a conductive connection portion 416 is formed on the pad. The pad is used to couple to the conductive connection 416 and may be referred to as under bump wiring (UBM). The pads may be formed in the topmost wiring pattern 412 through openings in the top dielectric layer 414 of the wiring structure 410. As an example of forming the pad, a seed layer (not shown) is formed over the dielectric layer 414. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer of a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pad. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Thereafter, various portions of the seed layer on which no conductive material is formed and the photoresist are removed. The photoresist can be removed, for example, by an acceptable ashing or stripping process using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by using an acceptable etching process, such as, for example, wet or dry etching. The rest of the seed layer and the conductive material form a pad. In the above embodiment, if the pads are formed differently, more photoresist and patterning steps may be utilized.

In addition, in Fig. 12, a conductive connection 416 is formed on the pad / UBM. The conductive connection 416 may be a bump formed from a ball grid array (BGA) connector, a solder ball, a metal filler, a controlled collapse chip connection (C4) bump, a micro bump, electroless nickel-electroless palladium- And so on. The conductive connection 416 may comprise a conductive material such as a braze material, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connection 416 is initially formed by forming a layer of braze material through commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, and the like. Once a layer of braze material is formed on the structure, reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 416 is a metal pillar (e.g., a copper filler) formed by sputtering, printing, electroplating, electroless plating, CVD, The metal filler may be free of braze material and may have a substantially vertical sidewall. In some embodiments, a metal cap layer (not shown) is formed on top of the metal pillar connector 416. The metal cap layer may comprise nickel, tin, tin-zinc, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold or the like or combinations thereof and may be formed by a plating process.

In Fig. 13, a carrier substrate separation is performed to detach (detach) the carrier substrate 400 from the dielectric layer 404. Thus, a first package 420 is formed in each package area of the carrier. According to some embodiments, the separation includes projecting light such as laser light or UV light onto the release layer 402 such that the release layer 402 is decomposed by heat of the light to remove the carrier substrate 400 . An opening is formed through the dielectric layer 404 to expose a portion of the wiring pattern through the via 406. The opening may be formed using, for example, laser drilling, etching, or the like.

14 illustrates a cross-sectional view of a package structure according to some embodiments. The package structure may be referred to as a paper-on-paper (PoP) structure. In FIG. 14, a second package 450 is attached to the first package 420. The second package 450 includes one or more lamination dies 440 (440A, 440B) coupled to the substrate 430 and the substrate 430. One laminate die 440 (440A, 440B) is illustrated, but in other embodiments, a plurality of laminate dies 440 (each including one or more lamination dies) are coupled side by side to the same surface of the substrate 430 . The substrate 430 may be formed of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphorus, silicon germanium carbide, gallium arsenide, gallium indium, combinations thereof, and the like may be used. In addition, the substrate 430 may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Substrate 430 is based on an insulating core such as a glass fiber reinforced resin core in one alternative embodiment. One exemplary core material is a glass fiber resin such as FR4. Alternative examples of core materials include bismaleimide-triazine (BT) resins, or alternatively other printed circuit board (PCB) materials or films. A build-up film such as an Ajinomoto Build-up Film (ABF) or other laminate may be used for the substrate 430. [

Substrate 430 may include active and passive components (not shown). As will be appreciated by one of ordinary skill in the art, various components, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to generate the structural and functional requirements of the design of the second package 450. The elements may be formed using any suitable method.

The substrate 430 may include a wiring layer (not shown) and through vias 432. The wiring layer can be formed on active and passive elements and is designed to connect various elements to form a functional circuit. The wiring layer may be formed by alternating dielectric layers (e. G., Low-k dielectric material) and conductive material layers (e. G., Copper) and layers of conductive material may be interconnected via vias, Drills, dual damascene, etc.). In some embodiments, the substrate 430 is substantially free of active and passive components.

The substrate 430 may include a substrate 430 that is opposite the first side to be coupled to the conductive contact 438 and a bonding pad 434 provided on the first side of the substrate 430 to be coupled to the lamination die 440. [ And a bonding pad 436 provided on the second side of the substrate. In some embodiments, bonding pads 434 and 436 are formed by forming recesses (not shown) in a dielectric layer (not shown) on first and second sides of substrate 430. The recesses may be formed such that the bonding pads 434 and 436 may be embedded into the dielectric layer. In another embodiment, the recesses are omitted if bonding pads 434 and 436 can be formed on the dielectric layer. In some embodiments, the bonding pads 434 and 436 include a thin seed layer (not shown) formed of copper, titanium, nickel, gold, palladium, or the like, or a combination thereof. The conductive material of the bonding pads 434 and 436 may be deposited on the thin seed layer. The conductive material may be formed by an electrochemical plating process, electroless plating process, CVD, ALD, PVF, etc., or a combination thereof. In one embodiment, the conductive material of the bonding pads 434 and 436 is copper, tungsten, aluminum, silver, gold, or the like, or a combination thereof.

In one embodiment, the bonding pads 434 and 436 are UBMs comprising a layer of three conductive materials such as a titanium layer, a copper layer, and a nickel layer. However, one of ordinary skill in the art will appreciate that the composition of the chromium / chrome-copper alloy / copper / gold, titanium / titanium / tungsten / copper composition, or copper / nickel / gold composition suitable for formation of the bonding pads 434, Those skilled in the art will recognize that there are many suitable configurations of the same materials and layers. Any suitable material or layer of material that may be used for the bonding pads 434 and 436 is intended to be fully within the scope of the present application. In some embodiments, the through vias 432 penetrate the substrate 430 to couple at least one bonding pad 434 to at least one bonding pad 436.

In the illustrated embodiment, the laminate die 440 is bonded to the substrate 430 by a wire bonding portion 442, but other connections such as conductive bumps may be used. In one embodiment, the lamination die 440 is a stacked memory die. For example, the lamination die 440 may be a memory die such as a low power (LP) double data rate (DDR) memory module such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules.

The lamination die 440 and the wire bonding portion 442 can be sealed by the molding material 444. [ The molding material 444 can be molded on the lamination die 440 and the wire bonding portion 442, for example, using compression molding. In some embodiments, the molding material 444 is a molding compound, a polymer, an epoxy, a silicon oxide filling material, or the like, or a combination thereof. A curing step may be performed to cure the molding material 444, wherein the curing may be thermal curing, UV curing, or the like, or a combination thereof.

In some embodiments, the lamination die 440 and the wire bonding portion 442 are embedded in the molding material 444, and after the molding material 444 has been cured, a planarization step, such as polishing, Thereby providing a substantially planar surface for the second package 450.

After the second package 450 is formed, the second package 450 is electrically connected to the first package 450 by a conductive connection 438, a bonding pad 436, and a through via 406 (or backside re- 420). ≪ / RTI > In some embodiments, the stacking die 440 includes a wire bonding portion 442, bonding pads 434 and 436, through vias 432, conductive connections 438, through vias 406, Lt; RTI ID = 0.0 > 392 < / RTI >

The conductive connection 438 and the conductive connection 416 need not be identical, as the conductive connection 438 may be similar to the conductive connection 416 described above, although the description thereof is not repeated here. The conductive connection 438 may be disposed on the side of the substrate 430 opposite the stacking die 440. In some embodiments, a solder resist (not otherwise indicated) may be formed on the side of the substrate opposite to the lamination die 440. The conductive connection 438 may be disposed in an opening in the solder resist to be electrically and mechanically coupled to a conductive feature (e.g., bonding pad 436) within the substrate 430. The solder resist can be used to protect areas of the substrate from external damage.

In some embodiments, prior to bonding the conductive connection 438, the conductive bonding portion 438 is coated with a flux (not shown), such as a no-clean flux. The conductive connection 438 may be immersed in the flux or the flux may be jetted to the conductive connection 438. [ In another embodiment, the flux may be applied to the surface of the through vias 406 (or the back side reordering structure, if present).

In some embodiments, the conductive connection 438 may be formed by depositing a selective epoxy flux (not shown) formed on top of at least a portion of the epoxy portion of the epoxy flux left after the second package 450 is attached to the first package 420, (Not shown).

An underfill (not shown) may be formed between the first package 420 and the second package 450 and around the conductive connection 438. The under-ping can reduce the stress and protect the connection due to the reflow of the conductive connection 438. [ The underfill may be formed by a capillary flow process after the second package 450 is attached or by an appropriate deposition method before the second package 450 is attached. In embodiments where an epoxy flux is formed, the epoxy flux may act as an underfill.

The bonding between the second package 450 and the first package 420 may be solder bonding. In one embodiment, the second package 450 is bonded to the first package 420 by a reflow process. During this reflow process, the conductive receptacle 438 contacts the bonding pads 436 and the through vias 406 (or rear side reordering structures, if present) to connect the second package 450 to the first package 420, Lt; RTI ID = 0.0 > and < / RTI > After the bonding process, the interface between the conductive via 438 and the conductive interconnect 438 and the bonding pad 4436 (not shown) is formed at the interface between the through via 406 (or the backside reordering structure, if present) A compound (IMC, not shown) may be formed. In one embodiment, the underfill material can be applied after the bonding process to cover the bonding conductive connections to provide additional protection against adverse environmental conditions such as, for example, moisture, particles and chemical corrosion.

For example, a fragmentation process is performed by cutting along a scribe line region between package regions. The resulting fragmented first and second packages 420, 450 are from one of the package regions. In some embodiments, the fragmenting process is performed after the second package 450 is attached to the first package 420. In another embodiment (not shown), the fragmenting process is performed, for example, after the carrier substrate 400 is detached before the second package 450 is attached to the first package 420. [

Additional processing may be performed on the package structure of FIG. For example, the package structure of Fig. 15 may be mounted to the package substrate using the conductive connection 416. Fig.

Figures 15-21 illustrate a cross-sectional view of another package structure in accordance with some embodiments. The embodiment of Figures 15-21 is similar to the embodiment of Figures 1-12 except that this embodiment includes through vias 466 in the integrated circuit die 100 and the integrated circuit die 200 does not include through vias. Which is similar to the embodiment. In addition, the integrated circuit die 100, 200 are oppositely oriented in the package structure, e.g., when the integrated circuit die 100 is attached to the carrier substrate 400 (see FIG. 18) 200). The details of this embodiment similar to the above embodiment are not repeated herein.

In FIG. 15, the integrated circuit die 100 is illustrated as including through vias 466. The details of the integrated circuit die 100 of this embodiment, which is similar to the integrated circuit die 100 of the above-described embodiment, are not repeated herein.

In this embodiment, through vias 466 extend from the pads 104 on the integrated circuit die 100 into the semiconductor substrate 102 of the integrated circuit die 100. The formation of the through vias 466 may be similar to the through vias 204 of the integrated circuit die 200 of the above-described embodiment, so the description thereof is not repeated here.

It should be appreciated that although two through vias 466 are illustrated in the integrated circuit die 100, there may be more or less through vias 466 in each integrated circuit die 100.

Fig. 16 illustrates further processing for the structure of Fig. The process between these two figures is similar to the process illustrated and described with reference to Figures 2 and 3, and Figure 3 is the same intermediate step as Figure 6, so the description is not repeated here.

In FIG. 16, the integrated circuit die 100, 200 are bonded together by a bonding connection 300. The bonding connection 300 may be any of the bonding connection configurations 300A-300O of FIGS. 4A-4O.

Figure 17 illustrates further processing for the structure of Figure 16; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 3-5, and Fig. 5 is the same intermediate step as Fig. 17 so that the description is not repeated here. The bonded integrated circuit die 100, 200 is encapsulated with an encapsulant 464 to form a package 470.

Figure 18 illustrates attaching the package 470 on a carrier substrate 400 similar to that described above in Figures 7 and 8, so the description is not repeated here. In FIG. 18, a package 470 is attached to a carrier substrate, and the integrated circuit die 200 is closer to the carrier substrate than the integrated circuit die 100.

Figure 19 illustrates further processing for the structure of Figure 16; The processing between these two figures is similar to the processing illustrated and described with reference to Figs. 9 and 10, and Fig. 10 is the same intermediate step as Fig. 19, so the description is not repeated here. The package 470 is encapsulated with an encapsulant 472 and its upper surface is planarized.

In Fig. 19, the encapsulant 472 may be subjected to a polishing process that exposes the electrical connections 406 and through vias 466. The surfaces of the electrical connections 406, the through vias 466, the semiconductor substrate 102, and the encapsulant 472 are the same after the polishing process.

Figure 20 illustrates further processing for the structure of Figure 19; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 10 and 11, and Fig. 11 is the same intermediate step as Fig. In Fig. 20, a wiring structure 410 is formed so as to be electrically coupled to the through vias 406 and the through vias 466. As shown in Fig.

Figure 21 illustrates further processing for the structure of Figure 20; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 12-14, and Fig. 14 is the same intermediate step as Fig. In Fig. 21, the second package 450 is bonded to the package structure 476 of Fig.

Additional processing may be performed on the package structure of FIG. For example, the package structure of FIG. 21 may be mounted to the package substrate using the conductive connection 416.

22-28 illustrate a cross-sectional view of another package structure in accordance with some embodiments. The embodiment of Figs. 22-28 is similar to the embodiment illustrated in Figs. 15-21 except that this embodiment has an integrated circuit die 100, 200 that is front-back mated instead of front-front. The integrated circuit die 100 includes a die connector 488 and an insulating layer 490 on the pad 104 on the active side of the integrated circuit die 100. These die connectors 488 and insulating layer 490 can protect the pad 104 during subsequent planarization processes. The details of this embodiment similar to the above embodiment are not repeated herein.

The die connector 488 may be formed of a material and a similar process similar to the pad 104 described above, so the description thereof is not repeated herein. In this embodiment, the die connector may be a copper filler, and the pad 104 may be an aluminum contact pad. Since the insulating layer 490 may be similar to the above-described insulating layer, the description thereof is not repeated here.

23, the active side of the integrated circuit die 100 is attached to the carrier substrate 498. Since the carrier substrate 498 is similar to the carrier substrate 400 described above, its description is not repeated here. The backside of integrated circuit die 100 is thinned to expose through vias 466. This thinning may be similar to the thinning process described above in FIG. 6, so the description is not repeated here. After the thinning process, insulating layers 492 and 496 and pads 494 are formed on the backside of the integrated circuit die 100. Insulation layers 492 and 496 and pads 494 may be utilized to bond the integrated circuit die 100 to the integrated circuit die 200. The pads 494 are electrically coupled to the exposed through vias 466. The pad 494 may be formed of a material and a process similar to the pad 104 described above, so the description thereof is not repeated here. The insulating layers 492 and 496 may be formed by a material and a process similar to the insulating layer 208 described above, so the description thereof is not repeated here.

In FIG. 24, integrated circuit die 100 is bonded to integrated circuit die 200. The bonding has been described above in FIGS. 2 and 3, so the description is not repeated here. In FIG. 24, integrated circuit die 100, 200 are bonded together by bonding connection 300. The bonding connection 300 may be any of the bonding connection configurations 300A-300O of FIGS. 4A-4O.

Figure 25 illustrates further processing for the structure of Figure 24; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 3-5, and Fig. 5 is the same intermediate step as Fig. The bonded integrated circuit die 100, 200 is encapsulated with an encapsulant 499 to form a package 500.

Fig. 26 illustrates attachment of the package 500 onto a carrier substrate 400 similar to that described above in Figs. 7 and 8, and the description thereof is not repeated here. In FIG. 26, a package 500 is attached to a carrier substrate, and the integrated circuit die 200 is closer to the carrier substrate than the integrated circuit die 100.

Figure 26 illustrates further processing for the structure of Figure 25; The process between these two figures is similar to the process illustrated and described with respect to Figs. 9 and 10, and Fig. 10 is the same intermediate step as Fig. The package 500 is encapsulated with the encapsulant 502 and its upper surface is planarized.

In Fig. 26, the encapsulant 502 may be subjected to a polishing process that exposes the electrical connections 406 and the die connector 488. The surfaces of the electrical connections 406, the die connectors 488, the insulating layer 490 and the encapsulant 502 are the same after the polishing process.

Figure 27 illustrates further processing for the structure of Figure 26; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 10 and 11, and Fig. 11 is the same intermediate step as Fig. In Fig. 27, a wiring structure 410 is formed so as to be electrically coupled to the through-via 406 and the die connector 488. In Fig.

Figure 28 illustrates further processing for the structure of Figure 27; The processing between these two figures is similar to the processing illustrated and described with reference to Figs. 12-14, and Fig. 14 is the same intermediate step as Fig. In Fig. 28, the second package 450 is bonded to the package structure 500 of Fig.

Additional processing may be performed on the package structure of FIG. For example, the package structure of FIG. 28 may be mounted to the package substrate using the conductive connection 416.

29-34 illustrate a cross-sectional view of another package structure in accordance with some embodiments. The embodiment of Figures 29-34 shows that the integrated circuit die 100 in this embodiment does not include the die connector 488 and the insulating layer 490 on the pad 104 on the active side of the integrated circuit die 100 Is similar to the embodiment illustrated in Figs. This removal of die connector 488 and insulating layer 490 requires additional carrier substrate bonding / disconnection to protect pad 9104). The details of this embodiment similar to the above embodiment are not repeated herein.

FIG. 29 illustrates integrated circuit die 100 bonded to integrated circuit die 200 as described above in FIG. 24, and the description thereof is not repeated here. The bonding has been described above in FIGS. 2 and 3, so the description is not repeated here. In FIG. 29, integrated circuit die 100, 200 are bonded together by bonding connection 300. The bonding connection 300 may be any of the bonding connection configurations 300A-300O of FIGS. 4A-4O.

Figure 30 illustrates further processing for the structure of Figure 29; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 3-8, and Fig. 8 is the same intermediate step as Fig. 30, so the description is not repeated here. The bonded integrated circuit die 100, 200 is encapsulated with an encapsulant 522 to form a package 524.

Figure 30 illustrates attaching the package 524 on a carrier substrate 400 similar to that described above in Figures 7 and 8, so the description is not repeated here. In Figure 30, a package 524 is attached to a carrier substrate, and the integrated circuit die 100 is closer to the carrier substrate 400 than the integrated circuit die 200.

Figure 31 illustrates an additional process for the structure of Figure 30; The processing between these two figures is similar to the processing illustrated and described with reference to Figs. 9 and 10, and Fig. 10 is the same intermediate step as Fig. The package 524 is encapsulated with an encapsulant 526 and its upper surface is planarized.

In Fig. 31, the encapsulant 526 may be subjected to a polishing process that exposes the electrical connections 406. The surfaces of the electrical connection 406 and the encapsulant 526 are the same after the polishing process.

Figure 32 illustrates further processing for the structure of Figure 31; In Fig. 32, the carrier substrate 400 is detached and the structure is inverted and bonded to another carrier substrate 530. Since the separation process has been described above, the description thereof is not repeated here. 32, the package 524 is attached to a carrier substrate and the integrated circuit die 200 is closer to the carrier substrate 530 than the integrated circuit die 100. 32, the exposed surfaces of the encapsulant 526, the electrical contact 406 and the pad 104 and the semiconductor substrate 102 are at the same height without polishing.

Figure 33 illustrates further processing for the structure of Figure 32; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 10 and 11, and Fig. 11 is the same intermediate step as Fig. 33, a wiring structure 410 and a conductive connection portion 416 are formed so as to be electrically coupled to the through-via 406 and the pad 104. [

Figure 34 illustrates further processing for the structure of Figure 33; The processing between these two figures is similar to the processing illustrated and described with reference to Figs. 12-14, and Fig. 14 is the same intermediate step as Fig. 34, the second package 450 is bonded to the package structure 540 of FIG.

Additional processing may be performed on the package structure of FIG. For example, the package structure of FIG. 34 may be mounted to the package substrate using the conductive connection 416.

35-38 illustrate a cross-sectional view of another package structure in accordance with some embodiments. The embodiment of Figures 35-38 is similar to the embodiment illustrated in Figures 1-14, except that in this embodiment there is a gap between the dielectric layers of the integrated circuit die after the integrated circuit dies are bonded. The details of this embodiment similar to the above embodiment are not repeated herein.

35 illustrates the integrated circuit die 100 bonded to the integrated circuit die 200 as described above in FIGS. 2 and 3, the description thereof is not repeated here. In Figure 35, the integrated circuit die 100, 200 are bonded together by a bonding connection 300. The bonding connection portion 300 of this embodiment is the bonding connection portion configuration 300D of FIG. 4D. This embodiment includes a standoff gap between the dielectric layers of the integrated circuit die 100, 200.

Figure 36 illustrates further processing for the structure of Figure 35; In FIG. 36, a sealing layer 546 is formed over various components to seal the bonding interface between the integrated circuit die 100, 200. Sealing of the bonding interface can contribute to the reliability of the present embodiment as compared with the case where the bonding interface is not sealed in this structure. The sealing layer 546 may be formed of a material and a process similar to the above-described insulating layer 208, so the description thereof is not repeated here. According to one embodiment, the sealing layer may be formed of a polymeric material such as, for example, parylene, polyimide, BCB and PBO. The forming method may be by spraying, jet spraying, coating or the like.

Figure 37 illustrates further processing for the structure of Figure 36; The processing between these two figures is similar to the processing illustrated and described with respect to Fig. 5, and Fig. 5 is the same intermediate step as Fig. 37, so the description is not repeated here. The bonded integrated circuit die 100, 200 is encapsulated with an encapsulant 548 to form a package.

Figure 38 illustrates further processing for the structure of Figure 37; The processing between these two figures is similar to the processing illustrated and described with respect to Figs. 5-14, and Fig. 14 is the same intermediate step as Fig. 38, the second package 450 is bonded to the package structure 562 including the bonded integrated circuit die of FIG.

Additional processing may be performed on the package structure of FIG. For example, the package structure of FIG. 38 may be mounted to the package substrate using the conductive connection 416.

By forming a PoP structure including a die that is bonded together using a hybrid bonding technique that uses a brazing material instead of conventional copper-copper bonding of hybrid bonding, the bonding temperature of the hybrid bonding can be significantly lowered. In addition, the bonding pads of the structure may be recessed to reduce the height of the package structure. The die may be bonded together with the front-front (F2F) or front-back (F2B) bonding. For example, in the F2F bonding configuration, the active side (front side) of the die is bonded together, while in the F2B bonding configuration, the active side of one die is bonded to the back side of the other die.

In one embodiment, the package includes a first die having a first active surface and a first backside, a second die having a second active surface and a second backside and being bonded to the first die, and a conductive bonding material, Wherein the first active surface comprises a first bonding pad and a first insulating layer, the second active surface comprises a second bonding pad and a second insulating layer, and the second active surface of the second die comprises Facing the first active surface of the first die, wherein the second insulating layer is bonded to the first insulating layer via dielectric-dielectric bonding, and the conductive bonding material is bonded to the first bonding pad and the second bonding pad And the conductive bonding material has a reflow temperature lower than a reflow temperature of the first and second bonding pads.

Embodiments may include one or more of the following features. The first insulating layer is bonded to the second insulating layer by a separate bond including an O-H bond. The first bonding pad is recessed into the first insulating layer. The first insulating layer and the second insulating layer are both formed of a polymer. The first insulating layer and the second insulating layer may be formed of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG) . Voids are present between the periphery of the conductive bonding material and the first and second bonding pads. The first package structure comprising a conductive pad on the first active surface of the first die, a first through via electrically coupled to the conductive pad, a second through via provided on the first die, A first encapsulation material that laterally extends the first through-hole via the first encapsulation material, the first encapsulation material extending through the first encapsulation material, and the second encapsulation material, And a first wiring structure electrically connected to the first through vias. Wherein the first package structure is a second encapsulation member that encapsulates the second through vias adjacent to the first die and the first die, the first encapsulation member, and the second through vias, through the second encapsulation member Further comprising a second encapsulant to which the second through vias extend, wherein the first wiring structure is electrically coupled to the second through vias. The package further includes a second package structure bonded to the second through via by a first conductive connection.

In one embodiment, the method includes forming a first package by bonding a first side of a first die to a second side of a second die using a conductive bonding material and first and second insulating layers Wherein the first side includes a first bonding pad and the first insulating layer and the second side comprises a second bonding pad and the second insulating layer, Facing the first side of the first die, the low-dielectric layer being bonded to the first dielectric layer via dielectric-dielectric bonding, the conductive bonding material being bonded to the first and second bonding pads, And the conductive bonding material has a reflow temperature lower than a reflow temperature of the first and second bonding pads.

Embodiments may include one or more of the following features. Wherein forming the first package comprises forming a first conductive filler electrically coupled to the third bonding pad on a third bonding pad on the first side of the first die, Sealing the second die and the first conductive filler with an encapsulant. Wherein forming the first package comprises forming an electrical connection on the carrier substrate, attaching the bonded first and second die to the carrier substrate adjacent the electrical connection, wherein the first die is bonded to the carrier substrate Sealing the first and second die, the first encapsulant, and the electrical connection with a second encapsulant, the first die, the second die, the first encapsulation material, The first wiring structure and the second wiring structure are formed so that the first wiring structure is electrically connected to the first conductive pillar and the electrical connection portion, . ≪ / RTI > The method further includes removing the carrier substrate, bonding the second package proximate the first die to the electrical connection of the first package using a first conductive connection. Forming the first package includes forming a via in the first die, encapsulating the first die and the second die with a first encapsulation material, forming an electrical connection on the carrier substrate, Attaching the first bonded die and the second bonded die to the carrier substrate adjacent the electrical connection, wherein the second die is adjacent to the carrier substrate; attaching the bonded first and second die, Sealing the first encapsulant and the electrical connection with a second encapsulant; planarizing the encapsulant to expose the vias in the electrical connection and the first die; Forming a first wiring structure on the first die, the first encapsulation material, the second encapsulation material, and the electrical connection portion, So as to be electrically coupled to the term connecting portion, the first wiring and forming a structural body and the first wiring and forming a conductive connection portion to be electrically coupled to structure on more. The first insulating layer and the second insulating layer are both formed of a polymer. The first insulating layer and the second insulating layer may be formed of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG) .

In one embodiment, a method includes forming a first insulating layer on a first side of a first wafer, patterning the recess in the first insulating layer, depositing a conductive layer on the first insulating layer, Depositing a material having a thickness equal to the thickness of the first insulating layer, wherein the thickness of the conductive material is less than the thickness of the first insulating layer; removing portions of the conductive material outside the recess to form a first bonding pad, Removing the first bonding pad and the first insulating layer such that the first bonding pad and the first insulating layer are positioned on a first active surface of the first die in the first wafer; and a second active surface having a second bonding pad and a second insulating layer Forming a conductive bump on the second bonding pad such that the conductive bump has a reflow temperature lower than the reflow temperature of the first and second bonding pads, brother A step, wherein the conductive bump on the second bonding pad comprises the step of bonding the second insulating layer in the step of bonding in the first bonding pad and said second die on the first insulating layer.

Embodiments may include one or more of the following features. The method further includes forming a first conductive filler on the third bonding pad on the first active surface of the first die such that the first conductive filler is electrically coupled to the third bonding pad, Sealing the first conductive pillar with a first encapsulant; and segmenting the first wafer and the first encapsulant, wherein the first die, the second die, the first conductive pillar, and the first encapsulant To form a first package structure including the first package structure. The method includes forming an electrical connection on a carrier substrate, attaching the first package structure to the carrier substrate adjacent the electrical connection, wherein the first die is adjacent to the carrier substrate, The method comprising: encapsulating the structure and the electrical connection portion with a second encapsulant; and forming a first reed structure on the first package structure, the second encapsulation material, and the electrical connection portion, And forming the first wiring structure to be electrically coupled to the first conductive filler and the electrical connection portion.

1) A package according to the first aspect of the present disclosure includes a first package structure, the first package structure comprising: a first die having a first active side and a first back side; A second die bonded to the first die with a second active surface and a second backside; And a conductive bonding material, wherein the first active surface comprises a first bonding pad and a first insulating layer, the second active surface comprises a second bonding pad and a second insulating layer, and the second die Wherein the second active surface of the first die is opposite the first active surface of the first die and the second insulating layer is bonded to the first insulating layer via dielectric-dielectric bonding, Pad and the second bonding pad, and the conductive bonding material has a reflow temperature lower than the reflow temperature of the first and second bonding pads.

2) In the package according to the first aspect of the present disclosure, the first insulating layer is bonded to the second insulating layer by a separate bond including an O-H bond.

3) In the package according to the first aspect of the present disclosure, the first bonding pad is recessed into the first insulating layer.

4) In the package according to the first aspect of the present disclosure, the first insulating layer and the second insulating layer are both made of a polymer.

5) A package according to the first aspect of the present disclosure, wherein the first insulating layer and the second insulating layer are both made of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass ; BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof.

6) In the package according to the first aspect of the present disclosure, a void is present between the periphery of the conductive bonding material and the first and second bonding pads.

7) A package according to the first aspect of the present disclosure, wherein the first package structure comprises: a conductive pad on the first active surface of the first die; A first through vias electrically coupled to the conductive pad; A first encapsulation material on said first die and laterally sealing said second die and said first through vias, said first through vias extending through said first encapsulation material; ashes; And a first wiring structure provided on the second die, the first through vias, and the first encapsulation material and electrically coupled to the first through vias.

8) A package according to the first aspect of the present disclosure, wherein the first package structure comprises: a second through via adjacent to the first die; And a second encapsulant for encapsulating the first die, the first encapsulant, and the second through vias, wherein the second through vias extend through the second encapsulant, And the first wiring structure is electrically coupled to the second through via.

9) The package according to the first aspect of the present disclosure further comprises a second package structure bonded to the second through via by a first conductive connection.

10) The package according to the first aspect of the present disclosure, wherein the conductive bonding material is a soldering material, and the first and second bonding pads comprise copper or aluminum.

11) The method according to the second aspect of the present disclosure includes forming a first package, wherein forming the first package comprises forming a first side of the first die by a conductive bonding material, And bonding the second side of the second die to the second side of the second die using a second insulating layer, the first side including a first bonding pad and the first insulating layer, Wherein the second side of the second die faces the first side of the first die and the second insulating layer is bonded to the first insulating layer via dielectric- Wherein the conductive bonding material is bonded to the first and second bonding pads and the conductive bonding material has a reflow temperature lower than the reflow temperature of the first and second bonding pads.

12) The method according to the second aspect of the present disclosure, wherein the step of forming the first package comprises: forming a first package on the first side of the first die, 1 conductive filler; And sealing the first die, the second die, and the first conductive filler with a first encapsulant.

13) The method according to the second aspect of the present disclosure, wherein forming the first package comprises: forming an electrical connection on the carrier substrate; Attaching the bonded first and second die to the carrier substrate adjacent the electrical connection, the first die being adjacent to the carrier substrate; Sealing the bonded first and second die, the first encapsulant, and the electrical connection with a second encapsulant; And forming a first wiring structure on the first die, the second die, the first encapsulation material, the second encapsulation material, and the electrical connection portion, wherein the first wiring structure comprises the first conductive filler And forming the first wiring structure to be electrically coupled to the electrical connection portion.

14) A method according to the second aspect of the present disclosure, comprising: removing the carrier substrate; And bonding a second package proximate the first die to the electrical connection of the first package using a first conductive connection.

15) The method according to the second aspect of the present disclosure, wherein forming the first package comprises: forming a via in the first die; Sealing the first die and the second die with a first encapsulant; Forming an electrical connection on the carrier substrate; Attaching the encapsulant and the bonded first and second die to the carrier substrate adjacent the electrical connection, wherein the second die is adjacent to the carrier substrate; Sealing the bonded first and second die, the first encapsulant, and the electrical connection with a second encapsulant; Planarizing the encapsulant to expose the vias in the electrical connection and the first die; Wherein the first wiring structure is formed on the first die, the second die, the first encapsulation material, the second encapsulation material, and the electrical connection portion, Forming a first wiring structure to be electrically coupled to the electrical connection portion; And forming a conductive connecting portion on the first wiring structure to be electrically coupled to the first wiring structure.

16) In the method according to the second aspect of the present disclosure, both the first insulating layer and the second insulating layer are made of a polymer.

17) A method according to the second aspect of the present disclosure, wherein the first and second insulating layers are both silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG) , Phosphosilicate glass (BPSG), or combinations thereof.

18) A method according to the third aspect of the present disclosure includes: forming a first insulating layer on a first side of a first wafer; Patterning the recess in the first insulating layer; Depositing a conductive material on the recess and the first insulating layer at an equal angle so that the thickness of the conductive material is less than the thickness of the first insulating layer; Removing portions of the conductive material outside the recess to form a first bonding pad such that the first bonding pad and the first insulating layer are positioned on the first active surface of the first die in the first wafer , ≪ / RTI > Forming a second die comprising a second active surface having a second bonding pad and a second insulating layer; Forming a conductive bump on the second bonding pad such that the conductive bump has a reflow temperature lower than the reflow temperature of the first and second bonding pads; Bonding the conductive bump on the second bonding pad to the first bonding pad; And bonding the second insulating layer of the second die to the first insulating layer.

19) A method according to the third aspect of the present disclosure comprises: forming a first conductive filler on a third bonding pad on the first active surface of the first die to be electrically coupled to the third bonding pad; Sealing the first wafer, the second die, and the first conductive filler with a first encapsulant; And fragmenting the first wafer and the first encapsulant to form a first package structure comprising the first die, the second die, the first conductive pillar, and the first encapsulant .

20) A method according to the third aspect of the present disclosure comprises: forming an electrical connection on a carrier substrate; Attaching the first package structure to the carrier substrate adjacent the electrical connection, wherein the first die is adjacent to the carrier substrate; Sealing the first package structure and the electrical connection with a second encapsulant; And forming a first wiring structure on the first package structure, the second encapsulation material, and the electrical connection portion, wherein the first wiring structure is electrically coupled to the first conductive filler and the electrical connection portion, And forming the first wiring structure.

The foregoing description is a summary of features of the various embodiments to enable those skilled in the art to understand the various aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes or structures to accomplish the same purpose and / or to achieve the same advantages as the embodiments introduced herein. In addition, those skilled in the art should appreciate that equivalent configurations do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and changes can be made without departing from the spirit and scope of the present disclosure.

Claims (10)

As a package,
A first package structure,
The first package structure may include:
A first die having a first active side and a first back side;
A second die bonded to the first die with a second active surface and a second backside; And
Conductive bonding material
Lt; / RTI >
Wherein the first active surface comprises a first bonding pad and a first insulating layer,
The second active surface comprising a second bonding pad and a second dielectric layer, the second active surface of the second die facing a first active surface of the first die, - bonded to said first insulating layer via dielectric bonding,
Wherein the conductive bonding material is bonded to the first bonding pad and the second bonding pad and the conductive bonding material has a reflow temperature lower than the reflow temperature of the first and second bonding pads. The method according to claim 1,
Wherein the first insulating layer is bonded to the second insulating layer by a separate bond comprising an OH bond. The method according to claim 1,
Wherein the first bonding pad is recessed into the first insulating layer. The method according to claim 1,
The first insulating layer and the second insulating layer are both made of a polymer; or ii) both are made of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG) Boron-doped phosphosilicate glass (BPSG), or a combination thereof. The method according to claim 1,
Wherein a void is present between the periphery of the conductive bonding material and the first and second bonding pads. The method according to claim 1,
The first package structure may include:
A conductive pad on the first active surface of the first die;
A first through vias electrically coupled to the conductive pad;
A first encapsulation material on said first die and laterally sealing said second die and said first through vias, said first through vias extending through said first encapsulation material; ashes; And
And a second wiring structure provided on the second die, the first through vias, and the first encapsulation material and electrically coupled to the first through vias,
Further comprising: The method according to claim 6,
The first package structure may include:
A second through vias adjacent the first die; And
Wherein the second encapsulation material is a second encapsulant for encapsulating the first die, the first encapsulation material and the second through vias, wherein the second through-vias extend through the second encapsulation material,
Further comprising:
And the first wiring structure is electrically coupled to the second through via. 8. The method of claim 7,
Further comprising a second package structure bonded to the second via via by a first conductive connection. In the method,
And forming a first package,
Wherein forming the first package comprises:
Bonding the first side of the first die to the second side of the second die using a conductive bonding material and first and second insulating layers,
Wherein the first side comprises a first bonding pad and the first insulating layer, the second side comprises a second bonding pad and the second insulating layer, and the second side of the second die comprises the first Facing the first side of the die, the second insulating layer being bonded to the first insulating layer via dielectric-dielectric bonding, the conductive bonding material being bonded to the first and second bonding pads, Wherein the bonding material has a reflow temperature lower than the reflow temperature of the first and second bonding pads. In the method,
Forming a first insulating layer on a first side of a first wafer;
Patterning the recess in the first insulating layer;
Depositing a conductive material on the recess and the first insulating layer at an equal angle so that the thickness of the conductive material is less than the thickness of the first insulating layer;
Removing portions of the conductive material outside the recess to form a first bonding pad such that the first bonding pad and the first insulating layer are positioned on the first active surface of the first die in the first wafer , ≪ / RTI >
Forming a second die comprising a second active surface having a second bonding pad and a second insulating layer;
Forming a conductive bump on the second bonding pad such that the conductive bump has a reflow temperature lower than the reflow temperature of the first and second bonding pads;
Bonding the conductive bump on the second bonding pad to the first bonding pad; And
Bonding the second insulating layer of the second die to the first insulating layer
/ RTI >

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