CN112117195B

CN112117195B - Packaging method

Info

Publication number: CN112117195B
Application number: CN201911295619.9A
Authority: CN
Inventors: 王明军; 刘磊
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2023-06-02
Anticipated expiration: 2039-12-16
Also published as: CN112117195A

Abstract

A packaging method, comprising: providing a carrier and a semiconductor chip, wherein the carrier comprises a first surface and a second surface corresponding to the first surface, the semiconductor chip is provided with an electrode, and the semiconductor chip comprises a third surface exposed out of the electrode; forming a conductive blind hole in the carrier from the first surface of the carrier, wherein the top size of the conductive blind hole is smaller than the bottom size of the conductive blind hole; the first surface and the third surface are arranged oppositely, and the semiconductor chip is bonded on the carrier, so that the conductive blind holes correspond to electrodes of the semiconductor chip; and thinning the second surface of the carrier to change the conductive blind holes into conductive through holes. According to the embodiment of the invention, the forming efficiency of the conductive through hole is improved, so that the process cost for forming the conductive through hole is reduced, the packaging cost is reduced, the risk of etching stop in the process of forming the conductive through hole is avoided, the forming process of the conductive through hole is optimized, the forming efficiency of the conductive through hole is improved, and the packaging cost is reduced.

Description

Packaging method

Technical Field

The invention relates to the field of semiconductor packaging, in particular to a packaging method.

Background

With the development trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously reduced, and the requirements of people on the packaging technology of the integrated circuits are continuously improved. Existing packaging technologies include Ball Grid Array (BGA), chip size (Chip Scale Package, CSP), wafer level (Wafer Level Package, WLP), three-dimensional (3D), and System In Package (SiP), among others.

The system package may combine a plurality of active elements of different functions, passive elements, microelectromechanical systems (MEMS), optical elements, etc. into one unit, forming a system or subsystem that may provide multiple functions, allowing heterogeneous IC integration. Compared with a System on Chip (SoC), the System on Chip (SoC) has the advantages of relatively simple integration of System packaging, shorter design period and market period, lower cost and capability of realizing a more complex System.

Currently, in order to meet the goals of lower cost, reliability, rapider and higher density of integrated circuit packages, an advanced packaging method mainly adopts wafer level system packaging (Wafer Level Package System in Package, WLPSiP), and compared with the traditional system packaging, the wafer level system packaging completes a packaging integration process on a device wafer, has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a packaging method, which reduces packaging cost, improves packaging efficiency and improves packaging precision.

In order to solve the above problems, an embodiment of the present invention provides a packaging method, including: providing a carrier and a semiconductor chip, wherein the carrier comprises a first surface and a second surface corresponding to the first surface, the semiconductor chip is provided with an electrode, and the semiconductor chip comprises a third surface exposing the electrode; forming a conductive blind hole in the carrier from the first face of the carrier, wherein the top dimension of the conductive blind hole is smaller than the bottom dimension of the conductive blind hole; the first surface and the third surface are arranged oppositely, and the semiconductor chip is bonded on the carrier, so that the conductive blind holes correspond to electrodes of the semiconductor chip; thinning the second surface of the carrier to change the conductive blind holes into conductive through holes; a metal seed layer conformally covering the conductive via is formed.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the packaging method provided by the embodiment of the invention, the conductive blind hole is formed in the carrier from the first surface of the carrier, the top size of the conductive blind hole is smaller than the bottom size of the conductive blind hole, then the semiconductor chip is bonded on the carrier, and then the second surface of the carrier is thinned, so that the conductive blind hole is changed into the conductive through hole, and in the conductive through hole, the size of one end, which is close to the first surface of the device wafer, is smaller than the size of one end, which is far away from the device wafer, so that the forming efficiency of the conductive through hole is improved, the process cost for forming the conductive through hole is reduced, and the packaging cost is reduced. In addition, in the packaging method provided by the embodiment of the invention, an etching stop layer is not required to be formed, the risk of etching stop in the process of forming the conductive through hole is avoided, and the forming process of the conductive through hole is optimized, so that the forming efficiency of the conductive through hole is improved, and the packaging cost is reduced.

Drawings

FIGS. 1 to 9 are schematic structural views of steps in a packaging method;

Fig. 10 to 22 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method.

Detailed Description

At present, the existing packaging method has higher packaging cost, lower packaging efficiency and higher packaging precision. The cause of the above problems is now analyzed in conjunction with a packaging method.

Fig. 1 to 9 are schematic structural diagrams corresponding to each step of a packaging method.

Referring to fig. 1, a cover wafer 10 is provided, the cover wafer 10 including a first face 18 and a second face 19 corresponding to the first face 18.

Referring to fig. 2, a straight blind hole 11 is formed on a first surface of the cover wafer 10; after forming the straight blind holes 11, an etching resist layer 12 is formed, and the etching resist layer 12 conformally covers the top walls and the side walls of the straight blind holes 11 and the first face 18 of the cover wafer 10.

Referring to fig. 3, a device wafer 13 is provided, a front surface 20 of the device wafer 13 has a chip (not shown in the figure), a surface of the chip has a pad (not shown in the figure), and an oxide layer 14 is formed on the front surface 20 of the device wafer 13.

Referring to fig. 4, after the oxide layer 14 is formed, the first surface 18 of the cover wafer 10 is bonded to the front surface 20 of the device wafer 13 by the oxide layer 14.

Referring to fig. 5, after the first surface 18 of the cover wafer 10 is bonded to the front surface 20 of the device wafer 13, the second surface 19 of the cover wafer 10 is thinned, so that the through hole 11 becomes the through hole 15.

During the thinning process, the etching resist layer 12 at the bottom of the straight blind hole 11 is also removed.

Referring to fig. 6, after the through hole 11 is changed into the through hole 15, a shielding layer (not shown) covering the through hole 15 is formed; and etching the cover wafer 10 by taking the shielding layer as a mask and the anti-etching layer 12 as an etching stop layer, wherein a trapezoid through hole 16 is formed in the cover wafer 10, and the top size of the trapezoid through hole 16 is larger than the bottom size of the trapezoid through hole 16.

The trapezoidal via 16 is formed after bonding of the cap wafer 10 and the device wafer 13 is achieved so that the top dimension of the trapezoidal via 16 is larger than the bottom dimension of the trapezoidal via 16.

Referring to fig. 7 and 8 in combination, after forming the trapezoid through hole 16, the etching resist layer 12 and the oxide layer 14 at the bottom of the trapezoid through hole 16 are sequentially removed by using the shielding layer as a mask; after removing the etching resist layer 12 and the oxide layer 14 at the bottom of the trapezoid through hole 16, the shielding layer is removed.

The step of forming the trapezoidal via 16 generally includes: the cover wafer 10 is etched using the shielding layer as a mask, a via hole (not shown) is formed in the cover wafer, and after the via hole is formed, the top of the via hole is etched to form the trapezoid via hole 16.

Referring to fig. 9, a metal seed layer 17 is conformally coated over the trapezoid shaped via 16, through via 15, and the device wafer 13 where the trapezoid shaped via 16 and through via 15 are exposed.

In the packaging method, the straight blind hole 11 is formed before the bonding process, the trapezoid through hole 16 is formed after the bonding process, and correspondingly, the straight blind hole 11 and the trapezoid through hole 16 are not formed in the same positioning state, so that the relative position precision of the straight blind hole 11 and the trapezoid through hole 16 is not high, and the trapezoid through hole 16 is not easy to expose a bonding pad on the chip, thereby reducing the packaging precision. Moreover, since the straight blind hole 11 and the trapezoidal through hole 16 are formed in different steps, repeated positioning is required at the time of forming the trapezoidal through hole 16, thereby requiring an excessive process time.

In the packaging method, the etching resist layer 12 is used as an etching stop layer, and after the trapezoid through hole 16 is formed in the cover wafer 10, in the process of etching the etching resist layer 12 and the oxide layer 14 at the bottom of the trapezoid through hole 16, when the adopted etching process is wet etching, the wet etching process is isotropic etching process, and undercut (as shown in fig. 7E) is easily generated on the etching resist layer 12, so that the electrical signal abnormality is easily generated when the packaging structure completed by the packaging method works.

In the packaging method, after the cover wafer 10 and the device wafer 13 are bonded, the difficulty of forming the trapezoid through hole 16 with the top dimension larger than the bottom dimension in the cover wafer 10 is relatively high, and accordingly, the efficiency of the trapezoid through hole 16 forming process is low, resulting in relatively high cost of the packaging process.

In addition, the step of forming the trapezoid through hole 16 generally includes: a via (not shown) is formed in the cover wafer 10, and after the via is formed, the top of the via is etched to form the trapezoid via 16. Therefore, the formation efficiency of the trapezoid through-hole 16 is low.

In order to solve the technical problem, an embodiment of the present invention provides a packaging method, including: providing a carrier and a semiconductor chip, wherein the carrier comprises a first surface and a second surface corresponding to the first surface, the semiconductor chip is provided with an electrode, and the semiconductor chip comprises a third surface exposing the electrode; forming a conductive blind hole in the carrier from the first face of the carrier, wherein the top dimension of the conductive blind hole is smaller than the bottom dimension of the conductive blind hole; the first surface and the third surface are arranged oppositely, and the semiconductor chip is bonded on the carrier, so that the conductive blind holes correspond to electrodes of the semiconductor chip; thinning the second surface of the carrier to change the conductive blind holes into conductive through holes; a metal seed layer conformally covering the conductive via is formed.

In the packaging method provided by the embodiment of the invention, the conductive blind hole is formed in the carrier from the first surface of the carrier, the top size of the conductive blind hole is smaller than the bottom size of the conductive blind hole, then the semiconductor chip is bonded on the carrier, and then the second surface of the carrier is thinned, so that the conductive blind hole is changed into the conductive through hole, the top size of the conductive through hole is larger than the bottom size of the conductive through hole, the forming efficiency of the conductive through hole is improved, the process cost for forming the conductive through hole is reduced, and the packaging cost is reduced. In addition, in the packaging method provided by the embodiment of the invention, an etching stop layer is not required to be formed, the risk of etching stop in the process of forming the conductive through hole is avoided, and the forming process of the conductive through hole is optimized, so that the forming efficiency of the conductive through hole is improved, and the packaging cost is reduced.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 10 to 22 are schematic structural diagrams corresponding to each step in an embodiment of a packaging method of an image capturing device according to the present invention.

Referring to fig. 10, a carrier 200 is provided, the carrier 200 including a first face 201 and a second face 202 corresponding to the first face 201.

The carrier 200 is used for bonding with a semiconductor chip. The first face 201 of the carrier 200 is the face to be bonded, and the first face 201 is used to prepare for subsequent formation of the alignment mark blind holes and the conductive blind holes.

In this embodiment, the carrier 200 is made of silicon. In other embodiments, the carrier may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the carrier may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the carrier may be a material suitable for the process requirements or easy to integrate.

It should be noted that, the alignment mark blind hole and the conductive blind hole are formed on the first surface 201 later. The blind holes of the alignment mark are used as the alignment mark when the carrier 200 is bonded with the semiconductor chip, and the blind holes of the conductive mark are used for preparing for the subsequent formation of the conductive through holes.

It should be further noted that in this embodiment, the packaging method is used to implement wafer level packaging, so as to improve packaging efficiency, and therefore, the semiconductor chip is integrated on the device wafer, and correspondingly, the carrier 200 is a carrier wafer.

Referring to fig. 11, a semiconductor chip 102 is provided, the semiconductor chip 102 having an electrode 104, and the semiconductor chip 102 including a third face 101 exposing the electrode 104.

In this embodiment, the semiconductor chip 102 is integrated in the device wafer 100, and the front surface (not labeled) of the device wafer 100 exposes the electrodes 104 of the semiconductor chip 102.

The device wafer 100 is a wafer to be packaged for completing device fabrication.

In this embodiment, the semiconductor substrate of the device wafer 100 is a silicon substrate. In other embodiments, the semiconductor substrate of the device wafer may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate may also be made of other types of substrates such as silicon on insulator or germanium on insulator. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration.

It should be noted that, the device wafer 100 may be manufactured by using an integrated circuit manufacturing technology, for example, an N-Metal-Oxide-Semiconductor (NMOS) device, a P-Metal-Oxide-Semiconductor (PMOS) device, etc. are formed on a Semiconductor substrate by using a deposition process, an etching process, etc., and a dielectric layer, a Metal interconnection structure, an electrode electrically connected to the Metal interconnection, etc. are formed on the front surface of the device wafer 100.

For convenience of illustration, in this embodiment, two semiconductor chips 102 are integrated in the device wafer 100 as an example. The number of the semiconductor chips 102 is not limited to two.

In this embodiment, the semiconductor chip 102 is a radio frequency chip. Specifically, the chip 102 is a bulk acoustic wave filter radio frequency chip (BAW RF filter). The acoustic wave filter radio frequency chip can provide a high quality factor at a higher frequency level with lower insertion loss. The size of the bulk acoustic wave filter decreases with increasing frequency, and furthermore, the sensitivity of the bulk acoustic wave design to temperature variations is much lower, even at wide bandwidths. In other embodiments, the chip may also be a communication chip, an artificial intelligence chip, an LED chip, a computer chip, or the like.

In this embodiment, the electrode 104 is a pad, and the electrode 104 is used to electrically connect the semiconductor chip 102 with other circuits. In this embodiment, the electrode 104 is a Bond Pad (Bond Pad).

It should be noted that, in this embodiment, the front surface of the device wafer 100 has a positioning hole, and the positioning hole is aligned with an alignment mark blind hole formed in the carrier 200 before the semiconductor chip 102 is bonded to the carrier 200, so that the conductive blind hole formed in the carrier 200 can correspond to the electrode 104 of the semiconductor chip 102.

With continued reference to fig. 11, after the semiconductor chip 102 is provided, an oxide layer 103 is formed on the third face 101 of the semiconductor chip 102.

The oxide layer 103 serves as a bonding layer for bonding the semiconductor chip 102 to the carrier 200 in the subsequent process, thereby achieving physical connection between the semiconductor chip 102 and the carrier 200 to be bonded.

In this embodiment, the oxide layer 103 has an insulating property, and can insulate the third surface 101 of the semiconductor chip 102 from the carrier 200.

In this embodiment, the material of the oxide layer 103 is silicon oxide. By selecting silicon oxide, in the subsequent bonding process of the semiconductor chip 102 to the carrier 200, the oxide layer 103 and the first surface 201 of the carrier 200 can be bonded by a covalent bond of si—o, and the bonding strength of the silicon-oxygen bond is improved due to the larger bonding energy of the silicon-oxygen bond; in addition, the silicon oxide material has higher process compatibility, and the silicon oxide is also a material with common process and lower cost, so that the method of selecting the silicon oxide material is beneficial to reducing the process difficulty and the process cost and reducing the performance influence on the formed packaging structure. In other embodiments, the material of the oxide layer 103 may be hafnium oxide, aluminum oxide, or lanthanum oxide.

In this embodiment, the oxide layer 103 is formed by an atomic layer deposition (Atomic Layer Deposition, ALD) process. Through an atomic layer deposition process, the oxide layer 103 is formed on the surface of the device wafer 100 in the form of an atomic layer, so that uniformity of a deposition rate, uniformity of thickness of the oxide layer 103 and uniformity of structure in the oxide layer 103 are improved, and the oxide layer 103 has good coverage capability; in addition, the process temperature of the atomic layer deposition process is generally lower, so that the Thermal Budget (Wafer) is also reduced, and the probability of Wafer deformation and device performance deviation is reduced. In other embodiments, the process of forming the oxide layer may also be a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process, a metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, or a laser pulse deposition (Pulsed Laser Deposition, PLD) process, depending on the material of the oxide layer.

In the process of forming the oxide layer 103 on the third surface 101 of the semiconductor chip 102, the oxide layer 103 covers the front surface of the device wafer 100.

Referring to fig. 12, after the carrier 200 is provided, an alignment mark blind hole 204 is formed in the carrier 200 from a first face 201 of the carrier 200 before the semiconductor chip 102 is bonded to the carrier 200.

The blind alignment mark holes 204 are used to align with the alignment holes in the device wafer 100 during the subsequent bonding of the semiconductor chip 102 and the carrier 200, thereby achieving alignment of the carrier 200 and the semiconductor chip 102.

Specifically, the step of forming the blind alignment mark holes 204 includes: forming a first mask layer (not shown) on the first face 201 of the carrier 200, wherein the first mask layer has a first opening (not shown) that exposes a region of the carrier 200 where the alignment mark blind hole 204 is to be formed; and etching the carrier 200 from the first surface of the carrier 200 by taking the first mask layer as a mask, and forming an alignment mark blind hole 204 in the carrier 200.

In this embodiment, the first mask layer is used as a mask, and a dry etching process (for example, an anisotropic dry etching process) is used to etch the alignment mark blind hole 204 formed on the first surface 201 of the carrier 200. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the appearance of the alignment mark blind holes 204 to meet the process requirements, and is also favorable for improving the removal efficiency of the carrier 200 material. Moreover, a dry etching process is adopted, which is beneficial to precisely controlling the formation depth of the blind alignment mark holes 204. In addition, the dry etching process is simpler and has lower cost.

In this embodiment, the material of the first mask layer is a material that is easy to remove, and after the alignment mark blind holes 204 are formed, damage to the carrier 200 is reduced in the process of removing the first mask layer.

The material of the first mask layer is an organic material, for example: photoresist, BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer ) material, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide) material, or APF (Advanced Patterning Film ) material.

In this embodiment, the material of the first mask layer is photoresist. By selecting the photoresist, the first mask layer can be directly patterned by a photoetching process, which is beneficial to simplifying the steps of the packaging process.

Specifically, the step of forming the first mask layer includes: forming a first mask material layer (not shown) covering the first side 201 of the carrier 200; and patterning the first mask material layer, forming the first opening in the first mask material layer, and taking the rest of the first mask material layer as a first mask layer.

In this embodiment, the first mask material layer is formed by using a spin-coating process. The surface flatness of the first mask material layer is higher.

The packaging method further comprises the following steps: after forming the blind alignment mark holes 204, the first mask layer is removed. In this embodiment, an ashing process is used to remove the first mask layer.

Referring to fig. 13 to 18, a conductive blind hole 203 (as shown in fig. 18) is formed in the first face 201 of the carrier 200, and the top size of the conductive blind hole 203 is smaller than the bottom size of the conductive blind hole 203.

After the second surface 202 of the carrier 200 is thinned, the conductive blind holes become conductive through holes. The conductive blind via 203 is further adapted to correspond to the electrode 104 of the semiconductor chip 102, such that the conductive via exposes the electrode 104 of the semiconductor chip 102 after bonding the third side 101 of the semiconductor chip 102 to the first side 201 of the carrier 200.

In the packaging method provided by the embodiment of the invention, the conductive blind hole 203 is formed in the carrier 200 from the first surface 201 of the carrier 200, the top dimension of the conductive blind hole 203 is smaller than the bottom dimension of the conductive blind hole 203, then the semiconductor chip 102 is bonded on the carrier 200, and the second surface 202 of the carrier 200 is thinned, so that the conductive blind hole 203 becomes a conductive through hole, and in the conductive through hole, the dimension of one end close to the first surface 101 of the device wafer 100 is smaller than the dimension of one end far from the device wafer 100, thereby improving the formation efficiency of the conductive through hole, reducing the process cost of forming the conductive through hole and being beneficial to reducing the packaging cost. In addition, in the packaging method provided by the embodiment of the invention, an etching stop layer is not required to be formed, the risk of etching stop in the process of forming the conductive through hole is avoided, and the forming process of the conductive through hole is optimized, so that the forming efficiency of the conductive through hole is improved, and the packaging cost is reduced.

In this embodiment, before the carrier 200 is bonded to the semiconductor chip 102, the alignment mark blind hole 204 and the conductive blind hole 203 are formed on the first surface 201 of the carrier 200, so that the alignment mark blind hole 204 and the conductive blind hole 203 can be formed under the same positioning condition, which makes the relative position precision of the alignment mark blind hole 204 and the conductive blind hole 203 high, and after the alignment mark blind hole 204 is subsequently utilized to position and bond the semiconductor chip 102 to the carrier 200, the conductive blind hole 203 is more likely to correspond to the electrode 104, and after the carrier 200 is subsequently bonded to the semiconductor chip 102, the second surface 202 of the carrier 200 is subjected to thinning treatment, and the conductive blind hole 203 becomes a conductive through hole, so that the conductive through hole can be exposed out of the electrode, and because the alignment mark blind hole 204 and the conductive blind hole 203 are formed under the same positioning condition, repeated positioning is avoided, so that the alignment mark blind hole 204 and the conductive blind hole 203 have higher forming efficiency, which is beneficial to reduce packaging cost and process time.

In this embodiment, the top dimension of the conductive blind hole 203 is smaller than the bottom dimension of the conductive blind hole 203.

After the carrier 200 is bonded to the semiconductor chip 102, the second surface 202 of the carrier 200 is thinned, so that the conductive blind hole 203 becomes a conductive through hole, and therefore, in the conductive through hole, the size of one end, close to the first surface 101 of the device wafer 100, is smaller than the size of one end, far away from the device wafer 100, that is, the longitudinal section of the conductive through hole is in an inverted trapezoid shape, so that a seed layer with better quality can be formed on the device wafer 100 exposed by the conductive through hole, which is beneficial to improving the packaging performance.

The step of forming the conductive blind via 203 includes: as shown in fig. 13, a second mask layer 205 is formed on the first surface 201 of the carrier 200, the second mask layer 205 has a second opening 206, and the second opening 206 exposes a region of the carrier 200 where the conductive blind hole 203 is to be formed; as shown in fig. 14 to 18, the carrier 200 is etched from the first surface of the carrier 200 with the second mask layer 205 as a mask, and the conductive blind holes 203 are formed in the carrier 200.

In this embodiment, the formation process of the second mask layer 205 refers to the description of the first mask layer, and the specific process is not described herein.

It should be noted that, in the process of forming the second mask layer 205, the second mask layer 205 is further filled in the blind alignment mark holes 204 (as shown in fig. 12), so as to avoid damage to the blind alignment mark holes 204 caused by the process of forming the blind conductive holes 204.

In this embodiment, the carrier 200 is etched from the first surface 201 of the carrier 200 by a deep silicon etching process, and the conductive blind holes 203 are formed in the carrier 200, where the deep silicon etching process includes etching a plurality of groups of sequentially and circularly performed etching process, passivation process, and bottom cleaning process.

By controlling the time ratio of etching treatment, passivation treatment and bottom cleaning treatment in the deep silicon etching process, the included angle between the bus of the formed conductive blind hole 203 and the normal of the first surface 201 can be well controlled, and the deep silicon etching rate has the advantages of high etching rate, strong anisotropism, less pollution and the like.

As shown in fig. 14, fig. 14 is a schematic enlarged view of a region a in fig. 13, and in the deep silicon etching process, the steps of the etching process include: the carrier 200 is etched, forming a recess 207 in the carrier 200.

In this embodiment, an isotropic dry etching process is used for the etching process.

During the first etching process, an isotropic dry etching process is used to etch the material of the first surface 201 exposed by the second opening 206, so as to form a recess 207 in the first surface 201 of the carrier 200.

The etching gas adopted in the etching treatment is fluorine-containing gas, and the etching treatment is to decompose the etching gas in the isotropic dry etching process under the action of plasma to provide neutral fluorine groups and accelerated ions required by etching, so as to realize the etching of the first face 201 of the carrier 200.

In this embodiment, the process parameters of the etching process include: the etching gas comprises SF ₆ The chamber pressure is 10mTorr to 300mTorr, the etching time is 0.2 seconds to 4 seconds, and the flow rate of the etching gas is 300sccm to 2000sccm.

It should be noted that, during the etching process, the chamber pressure should not be too high or too low. If the chamber pressure is too low, the lower density of the plasma of the etching gas in the chamber tends to result in a lower etching carrier 200 rate, which is detrimental to the improvement of the groove 207 formation efficiency. If the chamber pressure is too high, the decomposition rate of the by-product generated by etching the carrier 200 is too slow, and correspondingly, the rate of the by-product exiting the chamber is too slow, and the chamber pressure is too high, which also easily causes the carrier 200 exposed by the second mask layer 205 to be etched by the etching gas at a relatively fast rate, which easily reduces the process controllability and the reaction rate uniformity of the etching process, resulting in poor process stability. In this embodiment, the chamber pressure is 10mTorr to 300mTorr.

It should be noted that the etching treatment time should not be too short or too long. If the etching process is too short, the depth of the formed recess 207 is too shallow, and accordingly, more etching processes are required to reach the depth required by the process, which results in too long process time for forming the conductive blind hole 203, and is not beneficial to improving the efficiency of the semiconductor structure. If the etching treatment is too long, the roughness of the side wall of the conductive blind hole is too large, which leads to existence of voids (void) in a redistribution layer (RDL) formed by filling conductive material in the conductive through hole after the subsequent thinning treatment, and if the etching treatment is too long, the process controllability of the etching treatment is easily reduced, which leads to poor process stability. In this embodiment, the etching time is 0.2 to 4 seconds during the etching process.

In the etching process, the flow rate of the etching gas should not be too large or too small. If the flow of the etching gas is too large, the pressure in the reaction chamber is easily caused to be too large, the etching gas etches the first face 201 of the carrier 200 exposed by the second opening 206 at a relatively high speed, which easily causes the roughness of the side wall of the formed conductive blind hole to be too large. If the flow rate of the etching gas is too small, the pressure in the reaction chamber is easily too small, and the etching rate of the etching gas to etch the first surface 201 of the carrier 200 is low, which is not beneficial to improving the formation efficiency of the groove 207. In this embodiment, the flow rate of the etching gas is 300sccm to 2000sccm during the etching process.

As shown in fig. 15, fig. 15 is a schematic structural diagram based on fig. 14, and the steps of the passivation process include: a passivation layer 208 is formed on the bottom and side walls of the recess 207.

And subsequently removing the passivation layer 208 at the bottom of the groove 207, wherein in the next etching process, the passivation layer 208 remained on the side wall of the groove 207 is used for protecting the side wall of the groove 207, so that only the bottom of the groove 207 exposed by the passivation layer 208 can be etched, and the etching process has anisotropic etching characteristics. And because the side walls of the grooves 207 are protected by the passivation layer 208, only the bottoms of the grooves 207 exposed by the passivation layer 208 are etched, which is beneficial to the projection of the grooves 207 formed by the previous etching treatment on the carrier 200 and the projection of the grooves 207 formed by the next etching treatment on the carrier 200, so that after the deep silicon etching process, the top dimension of the conductive blind holes 203 is smaller than the bottom dimension of the conductive blind holes 203.

In this embodiment, the passivation gas used in the passivation process is fluorocarbon-based gas, and the reaction gas used in the passivation process is decomposed under the action of high-density plasma to generate fluorocarbon polymer, and the fluorocarbon polymer is deposited on the side wall and bottom of the groove 207 to be used as the passivation layer 208.

The technological parameters of the passivation treatment comprise: the passivation gas used comprises C ₄ F ₈ The chamber pressure is 20mTorr to 300mTorr, the process time of the passivation treatment is 0.2 seconds to 4 seconds, and the flow rate of the passivation gas is 300sccm to 2000sccm.

The chamber pressure should not be too high or too low during the passivation process. If the chamber pressure is too high during the passivation process, the passivation layer 208 is too thick, and the process time required for removing the passivation layer 208 at the bottom of the groove 207 is too long during the subsequent bottom cleaning process, which is not beneficial to improving the formation efficiency of the conductive blind via 203, and if the chamber pressure is too high during the passivation process, the process controllability and the reaction rate uniformity of the passivation process are difficult to control. If the chamber pressure is too small during the passivation process, the formation rate of the passivation layer 208 is reduced, which is not beneficial to improving the formation rate of the conductive blind via 203, and the thickness uniformity of the passivation layer 208 in the recess 207 is easily caused to be poor, so that the passivation layer 208 in a partial area of the sidewall of the recess 207 is easily removed prematurely during the next etching process, resulting in damage to the sidewall of the recess 207, and accordingly poor formation quality of the finally formed conductive blind via 203. In this embodiment, the chamber pressure is between 10mTorr and 300mTorr during the passivation process.

During the passivation process, the flow rate of the passivation gas should not be too large or too small. If the flow of the passivation gas is too large, the passivation layer 208 is formed too thick, which results in too long process time for removing the passivation layer at the bottom of the groove 208, and if the flow of the passivation gas is too large, the process stability of the passivation treatment is also poor. If the flow rate of the passivation gas is too small, the passivation layer 208 is formed at too slow a rate, which is unfavorable for increasing the formation rate of the conductive via 203. In this embodiment, the flow rate of the passivation gas is 300sccm to 2000sccm.

In the passivation process, the process time of the passivation process is not too short or too long. If the process time of the passivation treatment is too short, the passivation layer 208 is easy to be formed too thin, and in the process of the bottom cleaning treatment, the passivation layer 208 at the bottom of the groove 207 is removed too quickly, so that the material of the carrier 200 at the bottom of the groove 207 is removed, and the formation quality of the conductive blind hole 203 is poor; and during the next etching process, the passivation layer 208 on the sidewall of the recess 207 cannot protect the sidewall of the recess 207, resulting in poor quality of the formation of the conductive blind via 203. If the passivation process is too long, the passivation layer 208 is too thick, which results in too long process time for removing the passivation layer at the bottom of the groove 208, which is not beneficial to improving the efficiency of forming the conductive via 203. In this embodiment, the process time of the passivation treatment is 0.2 to 4 seconds during the passivation treatment.

The passivation layer 208 is preferably neither too thick nor too thin during each of the passivation treatments. If the passivation layer 208 is too thick, the process time required for forming the passivation layer 208 is too long, and the process time required for removing the passivation layer 208 at the bottom of the groove 207 by using bottom cleaning treatment is too long, which is not beneficial to improving the formation efficiency of the semiconductor structure. If the passivation layer 208 is too thin, during the subsequent bottom cleaning process, the passivation layer 208 at the bottom of the groove 207 is removed too quickly, resulting in removal of the material of the carrier 200 at the bottom of the groove 207, resulting in poor formation quality of the conductive via 203; and during the next etching process, the passivation layer 208 on the sidewall of the groove 207 cannot protect the sidewall of the groove 207, resulting in poor formation quality of the conductive blind hole 203. In this embodiment, the passivation layer 208 has a thickness of 0.2 micrometers to 1.5 micrometers. For example 0.4 mm, 0.8 mm and 1.2 mm.

As shown in fig. 16, fig. 16 is a schematic view of the structure based on fig. 15, and the steps of the bottom cleaning process include: the passivation layer 208 at the bottom of the recess 207 is removed.

The passivation layer 208 at the bottom of the recess 207 is removed, so that the passivation layer 208 on the sidewall of the recess 207 protects the material of the carrier 200 on the sidewall of the recess 207 from being etched in the next etching process, which is favorable for the projection of the recess 207 formed in the previous etching process on the carrier 200, and the recess 207 formed in the next etching process is located in the projection of the carrier 200, so that after the deep silicon etching process, the top dimension of the conductive blind hole 203 is smaller than the bottom dimension of the conductive blind hole 203.

In this embodiment, the bottom cleaning process is performed by using an anisotropic dry etching process. The anisotropic dry etching process has good etching profile control, and can accurately remove the passivation layer 208 at the bottom of the groove 207, so that the shape of the passivation layer 208 remained on the side wall of the groove 207 meets the process requirement, and the removal efficiency of the passivation layer 208 at the bottom of the groove 207 is facilitated and improved.

The process parameters of the bottom cleaning treatment comprise: the etching gas comprises a gas containing F and O, the chamber pressure is 10mTorr to 300mTorr, the process time is 0.2 seconds to 4 seconds, and the etching gas flow is 100sccm to 2000sccm. In other embodiments, the bottom cleaning process is performed using physical sputter bombardment.

In this embodiment, the etching gas includes a gas containing F and O, where F and O can provide neutral fluorine groups and accelerated ions, and the neutral fluorine groups are brought to the bottom of the groove 207 by the accelerated ions and react with the passivation layer 208 at the bottom of the groove 207, so as to implement etching of the passivation layer 208 at the bottom of the groove 207.

It should be noted that the chamber pressure should not be too high or too low during the bottom purge process. If the chamber pressure is too high, the decomposition rate of the by-product generated by etching the carrier 200 is too slow, and accordingly, the rate of the by-product discharged out of the chamber is too slow, and the chamber pressure is too high, the passivation layer 208 at the bottom of the recess 207 is easily removed too fast, and the material of the carrier 200 at the bottom of the recess 207 is damaged, which may result in too high roughness of the sidewall of the formed conductive blind hole, resulting in existence of voids (void) in a redistribution layer (RDL) formed by filling the conductive material into the conductive blind hole after the subsequent thinning process, and if the chamber pressure is too high, the process controllability and uniformity of the reaction rate of the bottom cleaning process are reduced, and accordingly, the quality of the finally formed conductive blind hole 203 is poor. If the chamber pressure is too low, the plasma density of the etching gas in the chamber is low, which is detrimental to the removal rate of the passivation layer 208 at the bottom of the recess 207. In this embodiment, the chamber pressure is 10mTorr to 300mTorr.

It should be noted that, in the bottom cleaning process, the process time should not be too short or too long. If the process time is too short, the passivation layer 208 at the bottom of the groove 207 is easy to remain, which is not beneficial to forming the groove 207 in the next etching process, and the corresponding final formation quality of the conductive blind hole 203 is poor. If the process time is too long, after the passivation layer 208 at the bottom of the groove 207 is removed, the material of the carrier 200 after the bottom of the groove 207 is easily removed, which may cause too large roughness of the sidewall of the conductive blind hole, resulting in existence of voids (void) in the redistribution layer (RDL) formed by filling the conductive material into the conductive via hole after the subsequent thinning treatment, and if the etching treatment is too long, the process controllability of the etching treatment is also easily reduced, resulting in poor process stability. In this embodiment, the etching time is 0.2 to 4 seconds during the etching process.

The flow rate of the etching gas should not be too large or too small. If the flow of the etching gas is too large, the pressure in the reaction chamber is easily too large, the etching gas etches the passivation layer 208 at the bottom of the groove 207 at a relatively high speed, and accordingly, the carrier 200 at the bottom of the groove 207 is easily damaged in the bottom cleaning process, which is not beneficial to control the process and easily results in poor formation quality of the conductive blind holes 203. Too small a flow of the etching gas may result in too low a pressure in the reaction chamber, which may result in too slow a removal rate of the passivation layer 208 at the bottom of the recess 207. In this embodiment, the etching gas flow rate is 100sccm to 2000sccm.

As shown in fig. 17 and 18, fig. 17 is a schematic diagram showing a partial enlarged structure corresponding to the five-cycle process. Conductive blind holes 203 are formed in the first side 201 of the carrier 200 using a deep silicon etching process.

In this embodiment, after the conductive blind via 203 is formed by a deep silicon etching process, the passivation layer 208 at the bottom of the conductive blind via 203 is removed, and the passivation layer 208 on the sidewall of the conductive blind via 203 is remained. In other embodiments, the passivation process and the bottom cleaning process may not be performed after the last etching process is completed.

In this embodiment, a cyclic process comprising etching, passivation and bottom cleaning is performed a plurality of times, thereby forming conductive blind holes 203 in the carrier 200. In the deep silicon etching process, the reaction time of the etching process at the next time is longer than that of the etching process at the previous time, which is favorable for making the projection of the groove 207 formed by the etching process at the previous time on the carrier 200 and the projection of the groove 207 formed by the etching process at the next time on the carrier 200, so that the top dimension of the conductive blind hole 203 is smaller than the bottom dimension of the conductive blind hole 203 after the deep silicon etching process.

In the process of the etching treatment after the initial etching, the isotropic dry etching process etches the bottom of the recess 207 exposed by the passivation layer 208 on the sidewall of the recess 207 to form an initial recess (not shown in the figure); after forming the initial groove, the side wall of the initial groove and the bottom are etched by using an isotropic dry etching process, so that when the side wall of the groove 207 formed last time is not damaged, a new groove 207 is formed at the bottom of the groove 207 formed last time, and the projection of the groove 207 formed last time on the first face 201 can be covered by controlling the etching process time.

As shown in fig. 18, the packaging method further includes: after the conductive blind via 203 is formed, the second mask layer 205 is removed.

It should be noted that the conductive blind hole 203 is not too shallow. If the conductive blind hole 203 is too shallow, after the carrier 200 is bonded to the semiconductor chip 102, the rest of the carrier 200 is subjected to too high polishing pressure in the process of thinning the second surface 202 of the carrier 200, which is likely to cause cracking in the rest of the carrier 200 and damage to the semiconductor chip 102.

It should be further noted that, in the step of forming the conductive blind hole 203 in the carrier 200, an included angle between a bus bar of the conductive blind hole 203 and a normal line of the first surface 201 of the carrier 200 is not too large or too small. If the included angle is too large, the deep silicon etching process takes longer process time, the second surface of the carrier is thinned subsequently, the conductive blind holes become conductive through holes, and accordingly excessive materials filled in the conductive through holes subsequently are easy to cause waste. If the included angle is too small, then when a metal seed layer is formed to conformally cover the conductive via, it is easy to occur that the thickness of the metal seed layer on the sidewall of the conductive via is smaller than the thickness of the metal seed layer formed on the second surface 202 of the carrier 200, which is disadvantageous for forming a re-wiring (RDL) in the conductive via. In this embodiment, the included angle between the bus bar of the conductive blind hole 203 and the normal line of the first surface 201 of the carrier 200 is 2 ° to 3 °.

In this embodiment, the process of removing the second mask layer 205 refers to the process of removing the first mask layer, which is not described herein.

It should be noted that, in the embodiment of the present invention, the blind alignment mark holes 204 are formed first, and the blind conductive holes 203 are formed after the blind alignment mark holes 204 are formed.

In other embodiments, the carrier may be etched from the first surface of the carrier by using a deep silicon etching process in the same step, and an alignment mark blind hole and a conductive blind hole are formed in the carrier, where correspondingly, the top size of the formed alignment mark blind hole is smaller than the bottom size, and then the semiconductor chip and the carrier are positioned by using the alignment mark blind hole and the positioning hole.

The alignment mark blind holes and the conductive blind holes are formed simultaneously in the same step, so that the process steps are simplified, and the packaging efficiency is improved.

Correspondingly, the step of forming the alignment mark blind hole and the conductive blind hole comprises the following steps: forming a mask layer on the first surface of the carrier, wherein the mask layer is provided with a third opening, and the third opening exposes a region of the carrier, in which the alignment mark blind hole and the conductive blind hole are to be formed; and etching the carrier by taking the third opening as a mask, and forming an alignment mark blind hole and a conductive blind hole in the carrier.

In other embodiments, the conductive blind hole may be formed first, and then the alignment mark blind hole may be formed.

It should be further noted that, in the embodiment of the present invention, before the semiconductor chip 102 is bonded to the carrier 200, the conductive blind hole 203 is formed, and then the second surface 202 of the carrier 200 is thinned, and the conductive blind hole 203 is directly changed into a conductive through hole, so that there is no need to exist a position where etching is stopped in the process of forming the conductive through hole, that is, in the packaging method of the embodiment of the present invention, there is no need to form a film layer for playing a role of etching stop.

Referring to fig. 19, the first face 201 and the third face 101 are disposed opposite to each other, and the semiconductor chip 102 is bonded to the carrier 200 such that the conductive blind hole 203 corresponds to the electrode 104 of the semiconductor chip 102.

In this embodiment, the alignment mark blind hole 203 is used for positioning, and the semiconductor chip 102 is bonded to the carrier 200.

Specifically, the positions of the alignment mark blind holes 203 and the positioning holes are positioned by using a bonding alignment process (Bonding Alignment), so that the semiconductor chip 102 is aligned with the carrier 200, and the conductive blind holes 203 correspond to the electrodes 104, and correspondingly, the second surface 202 of the carrier 200 is thinned, so that the electrodes 104 are located right below the conductive through holes after the conductive blind holes 203 become the conductive through holes.

Specifically, the bonding alignment process includes: the positions of the blind alignment mark holes 203 and the positioning holes are found, and the device wafer 100 or the carrier 200 is moved, so that the blind alignment mark holes 203 and the positioning holes in the device wafer 100 are aligned.

The first surface 201 of the carrier 200 is bonded to the third surface 101 of the semiconductor chip 102, so that the conductive blind hole 203 is inverted on the third surface 101 of the semiconductor chip 102, so that a dimension of an end, far away from the third surface 101, of the conductive blind hole 203 is larger, and therefore, after the conductive blind hole 203 is subsequently thinned from the second surface 202 of the carrier 200 to become the conductive through hole 303, a dimension of an end, close to the first surface 101, of the conductive through hole is smaller than a dimension of an end, far away from the first surface 101, of the conductive through hole, so that a seed layer with better quality can be formed on the device wafer 100 exposed by the conductive through hole, which is beneficial to improving packaging performance.

Specifically, the first face 201 of the carrier 200 is bonded to the third face 101 of the semiconductor chip 102 via the oxide layer 103.

In this embodiment, the first face 201 of the carrier 200 is bonded to the third face 101 of the semiconductor chip 102 using a high temperature bonding process. After the first surface 201 of the carrier 200 is bonded to the third surface 101 of the semiconductor chip 102 by using a high-temperature bonding process, the influence of chemical solution on bonding efficiency in the subsequent process can be avoided, and the covalent bond formed by using the high-temperature bonding process has excellent high-temperature resistance and waterproof performance. In other embodiments, a fusion bonding process may also be employed.

Gao Wenjian the bonding process is a process that utilizes interfacial chemical forces to accomplish bonding. In the Gao Wenjian bonding process, si in the semiconductor chip 102 and O and Si in the oxide layer 103 diffuse mutually, and a Si-O covalent bond is formed between the oxide layer 103 and the semiconductor chip 102, so that the oxide layer 103 and the semiconductor chip 102 have higher bonding strength, thereby improving the reliability of the bonding process, further improving the bonding strength of the semiconductor chip 102 and the carrier 200, and correspondingly improving the packaging yield.

Referring to fig. 20, the second surface 202 of the carrier 200 is thinned, so that the conductive blind holes 203 become conductive through holes 303.

Compared with the situation that an alignment mark blind hole is formed before bonding a carrier and a device wafer, and a conductive through hole is formed in the carrier after bonding, in the embodiment of the invention, before bonding the carrier 200 and the semiconductor chip 102, the alignment mark blind hole 204 and the conductive blind hole 203 are formed on the first surface of the carrier 200 in the same positioning, so that the relative position precision of the alignment mark blind hole 204 and the conductive blind hole 203 is higher, after bonding the carrier 200 and the device wafer 100, the conductive blind hole 203 can correspond to the electrode 104, thereby being beneficial to improving the packaging precision, and because the alignment mark blind hole 204 and the conductive blind hole 203 are formed in the same positioning, repeated positioning is avoided, and the alignment mark blind hole 204 and the conductive blind hole 203 have higher forming efficiency, thereby being beneficial to reducing the packaging cost and the process time. After the carrier 200 is bonded to the semiconductor chip 102, the second surface 202 of the carrier 200 is thinned, the conductive blind hole 203 becomes a conductive through hole 303, and the electrode 104 is located directly below the conductive through hole 303, so that a metal seed layer formed in the conductive through hole 303 can cover the electrode 104, and an interconnection structure formed on the electrode 104 can be electrically connected with the electrode 104, which is beneficial to improving the packaging performance.

In this embodiment, the blind alignment mark holes 204 are also converted into the blind alignment mark holes 304 during the thinning process of the second surface 202 of the carrier 200. In other embodiments, for example, when the depth of the blind alignment mark holes is smaller than the depth of the conductive blind holes, and the thickness of the second surface of the carrier is smaller in the process of thinning the second surface of the carrier, the blind alignment mark holes are not enough to be converted into the blind alignment mark holes.

In this embodiment, a polishing process (polishing) is used to thin the second surface 202 of the carrier 200. The grinding process has the characteristics of low cost, high process efficiency, simple operation and the like. In other embodiments, the second side of the carrier is thinned using a chemical mechanical polishing process (chemical mechanical planarization, CMP).

The conductive via 303 should not be too deep or too shallow. If the conductive via 303 is too deep, the conductive blind hole 203 is correspondingly too deep, and the process difficulty of forming the conductive blind hole 203 is too high; in addition, if the conductive via 303 is too deep, the difficulty of covering the conductive via 303 and the exposed semiconductor chip 102 with the metal seed layer is too high, and after the metal seed layer is formed, voids are likely to exist in the redistribution layer formed by filling the conductive material into the conductive via 303. If the conductive through holes 303 are too shallow, that is, the material thinned from the second surface 202 is too much, the rest of the carrier 200 is subjected to polishing pressure in too long a time during the thinning process of the second surface 202 of the carrier 200, which is easy to cause cracks in the rest of the carrier 200 and damage to the semiconductor chips 102 in the device wafer 100. In this embodiment, the depth of the conductive via 303 is 40 micrometers to 100 micrometers.

It should be noted that, the packaging method further includes: after the second surface 202 of the carrier 200 is thinned, the conductive via 303 is cleaned, so as to remove the passivation layer 208 in the conductive via 303.

The passivation layer 208 in the conductive via 303 is removed in preparation for the subsequent formation of a metal seed layer in the conductive via 303, so that the quality of the formed metal seed layer is better.

In this embodiment, the passivation layer 208 in the conductive via 303 is removed using a gas including F and O.

It should be noted that, after the passivation layer 208 in the conductive via 303 is removed, deionized water is used to rinse the carrier 200 for cleaning.

In the process of performing the cleaning process on the carrier 200, the oxide layer 103 on the device wafer 100 can protect the semiconductor chip 102 from the cleaning process, so that the performance of the semiconductor chip 102 is not easily affected by the cleaning process.

The electrode 104 is located directly below the conductive via 303, and provides for the subsequent formation of a metal seed layer on the conductive via 303 and the electrode 104 exposed by the conductive via 303, so that the formed metal seed layer can contact the electrode 104.

As shown in fig. 21, it should be noted that the packaging method further includes: after the second surface 202 of the carrier 200 is thinned, the oxide layer 103 at the bottom of the conductive via 303 is removed before the metal seed layer is formed.

The oxide layer 103 at the bottom of the conductive via 303 is removed, exposing the electrode 104 of the semiconductor chip 102, so that a subsequently formed metal seed layer can contact the electrode 104.

The step of removing the oxide layer 103 at the bottom of the conductive via 303 includes: forming a third mask layer (not shown) covering the alignment mark holes 304 and the carrier 200, wherein the third mask layer exposes the bottoms of the conductive through holes 303; and etching the oxide layer 103 at the bottom of the conductive via 303 by using the third mask layer as a mask, and forming a third opening 106 (as shown in fig. 21) in the oxide layer 103.

In this embodiment, the third opening 106 exposes a portion of the electrode 104. In other embodiments, the third opening may also expose the entire electrode.

In this embodiment, the related description of the third mask layer refers to the first mask layer, and will not be repeated here.

In this embodiment, a dry etching process is used to remove the oxide layer 103 at the bottom of the conductive via 303. The dry etching process has anisotropic etching characteristics and good etching profile control, so that the projection of the third opening 106 on the device wafer 100 can be located in the projection of the bottom end of the conductive through hole 303 on the device wafer 100, so that undercut (undercut) is not easy to occur in the step of removing the oxide layer 103 at the bottom of the conductive through hole 303, and the reliability of the packaging structure is improved. In addition, a dry etching process is adopted, so that the position of etching stop can be controlled.

The packaging method further comprises the following steps: after forming a third opening 106 in the oxide layer 103, the third mask layer is removed.

Referring to fig. 22, a metal seed layer 105 is formed conformally covering the conductive via 303.

The metal seed layer 105 has a surface with high flatness and smoothness, which facilitates the subsequent preparation for forming a re-wiring (RDL) in the conductive via 303.

In the process of forming the metal seed layer 105 conformally covering the conductive via 303, the metal seed layer 105 also conformally covers the second surface 202 of the carrier 200.

In this embodiment, a physical vapor deposition process (Physical Vapor Deposition, PVD) is used to form the metal seed layer 105 on the conductive via 303 and the device wafer 100 exposed by the conductive via 303. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable composition and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow. In other embodiments, the metal seed layer may also be formed using an atomic layer deposition process or a metal organic chemical vapor deposition process.

The metal seed layer 105 includes a first metal seed layer 1051 and a second metal seed layer 1052 disposed on the first metal seed layer 1051.

The first metal seed layer 1051 has strong adhesion, and is not easy to fall off to prepare for a second metal seed layer formed later. In this embodiment, the material of the first metal seed layer 1051 is titanium.

The second metal seed layer 1052 has a relatively high conductivity in preparation for subsequent formation of a re-wiring structure in the conductive via 303 using an electrochemical plating process. In this embodiment, the material of the second metal seed layer 1052 is copper.

In the process of forming the metal seed layer 105, the metal seed layer 105 is further formed on the oxide layer 103 at the bottom of the alignment mark hole 304 and on the sidewall of the alignment mark hole 304.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of packaging, comprising:

Providing a carrier and a semiconductor chip, wherein the carrier comprises a first surface and a second surface corresponding to the first surface, the semiconductor chip is provided with an electrode, and the semiconductor chip comprises a third surface exposing the electrode;

forming a conductive blind hole and an alignment mark blind hole in the carrier from the first surface of the carrier, wherein the top size of the conductive blind hole is smaller than the bottom size of the conductive blind hole;

the first surface and the third surface are arranged oppositely, and the semiconductor chip is bonded on the carrier, so that the conductive blind holes correspond to electrodes of the semiconductor chip;

thinning the second surface of the carrier to change the conductive blind holes into conductive through holes and change the alignment mark blind holes into alignment mark holes;

a metal seed layer conformally covering the conductive via is formed.

2. The packaging method of claim 1, wherein the alignment mark blind via and conductive blind via are formed in the carrier in the same step.

3. The packaging method of claim 1, wherein the step of forming the blind alignment mark holes in the carrier from the first side of the carrier comprises: forming a first mask layer on the first surface of the carrier, wherein the first mask layer is provided with a first opening, and the first opening exposes a region of the carrier, in which a blind hole of an alignment mark is to be formed; etching the carrier from the first surface of the carrier by taking the first mask layer as a mask, and forming an alignment mark blind hole in the carrier;

The packaging method further comprises the following steps: and removing the first mask layer after forming the alignment mark blind holes.

4. A packaging method as claimed in claim 1 or 3, wherein the step of forming the blind alignment mark holes in the carrier from the first side of the carrier comprises: and etching the carrier from the first surface of the carrier by adopting a dry etching process, and forming an alignment mark blind hole in the carrier.

5. The packaging method of claim 1, wherein the step of forming the conductive blind via comprises: forming a second mask layer on the first surface of the carrier, wherein the second mask layer is provided with a second opening, and the second opening exposes a region of the carrier where the conductive blind hole is to be formed; etching the carrier from the first surface of the carrier by taking the second mask layer as a mask, and forming the conductive blind holes in the carrier;

the packaging method further comprises the following steps: and removing the second mask layer after the conductive blind holes are formed.

6. The packaging method of claim 1 or 5, wherein the step of forming conductive blind vias in the carrier from the first side of the carrier comprises: etching the carrier from the first surface of the carrier through a deep silicon etching process to form a conductive blind hole in the carrier, wherein the deep silicon etching process comprises etching a plurality of groups of etching treatment, passivation treatment and bottom cleaning treatment which are sequentially and circularly performed;

The etching treatment comprises the following steps: etching the carrier to form a groove in the carrier;

the passivation process comprises the following steps: forming passivation layers on the bottom wall and the side walls of the groove;

the bottom cleaning process includes the steps of: and removing the passivation layer at the bottom of the groove.

7. The packaging method of claim 6, wherein the etching process is performed using an isotropic dry etching process;

the technological parameters of the etching treatment comprise: the etching gas comprises SF6, the chamber pressure is 10mTorr to 300mTorr, the etching time is 0.2 seconds to 4 seconds, and the flow rate of the etching gas is 300sccm to 2000sccm.

8. The packaging method of claim 6, wherein the process parameters of the passivation process include: the passivation gas comprises C4F8, the chamber pressure is 10mTorr to 300mTorr, the process time of the passivation treatment is 0.2 seconds to 4 seconds, and the flow rate of the passivation gas is 300sccm to 2000sccm.

9. The packaging method of claim 6, wherein the passivation layer has a thickness of 0.2 microns to 1.5 microns during each of the passivation treatments.

10. The packaging method of claim 6, wherein the bottom cleaning process is performed using an anisotropic dry etching process, and wherein the process parameters of the bottom cleaning process include: the etching gas comprises a gas containing F and O, the chamber pressure is 10mTorr to 300mTorr, the process time is 0.2 seconds to 4 seconds, and the etching gas flow is 100sccm to 2000sccm.

11. The packaging method of claim 6, wherein in the step of forming conductive blind vias in the carrier, a reaction time of a previous etching process is less than a reaction time of a subsequent etching process.

12. The packaging method of claim 6, wherein after the conductive blind via is changed to a conductive via, the packaging method further comprises, prior to forming a metal seed layer conformally covering the conductive via: and cleaning the conductive through hole to remove the passivation layer in the conductive through hole.

13. The packaging method of claim 1, wherein the conductive vias have a depth of 40 microns to 100 microns.

14. The packaging method according to claim 1, wherein in the step of forming a conductive blind via in the carrier, an included angle between a bus bar of the conductive blind via and a normal line of the first surface of the carrier is 2 ° to 3 °.

15. The packaging method of claim 1, wherein the carrier material is silicon;

after providing the device wafer, before bonding the first surface of the carrier with the third surface of the semiconductor chip, the packaging method further includes: forming an oxide layer on a third surface of the semiconductor chip;

The step of bonding the semiconductor chip to the carrier includes: bonding the first face of the carrier with the third face of the semiconductor chip through an oxide layer;

the packaging method further comprises the following steps: and after the second surface of the carrier is thinned, removing the oxide layer at the bottom of the conductive through hole before forming the metal seed layer.

16. The packaging method of claim 1, wherein a physical vapor deposition process is used to form a metal seed layer conformally covering the conductive via.

17. The packaging method of claim 1, wherein the thinning process is performed on the second side of the carrier using a chemical mechanical polishing process or a grinding process.

18. The packaging method of claim 1, wherein the semiconductor chip is a radio frequency chip.

19. The packaging method of claim 1, wherein the semiconductor die is integrated in a device wafer and the carrier is a carrier wafer.