1305406 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板之製造方法，尤指一種無需形成電 鏟金屬導線電鍍金屬保護層之封裝基板製造方法。 【先前技術】 近年來’隨著電子產品輕小化轉私及電子產動目關技術的 • 快速提昇’半導體晶片封裝基板(或稱ic載板)製造業者正面臨著 許多製程上的關鍵及挑戰。 如熟習該項技藝者所知，封裝基板之製作過程中，除了於其上 形成細密料線贿(-般為__之外，且各導線線路上的 I/O接點通常另需再鑛上一層所謂的「軟金」，也就是錄/金㈣制 以提相裝基板與“之贴進行打錢過辦構成穩固的 -性連接’同時’此鎳/金層亦有防止圖案化銅質導線氧化之功能。 習知電賴/金表面處理之作祕在具職化銅質線路之基板 面上儿成防焊層之後始進行之。因此，在未被防騎遮蔽之區 需有從紐絲仏鱗魏延輕練之紐延伸導線 ，以作為電鍍時之導電路徑。如此，才能在基板上外 路、防焊科之各待鍍金區域上魏-層特定厚度的鎳/金層。 …、而上述1知作法之主要缺點在於電鍍延伸導線勢必佔據封 1305406 裝土板表面可彻的佈線空間，使得基板的佈線密度無法提升。 此外，在_使用時，因錄之魏導線會辟待紐區域之電 訊品質，而柄謂的天線效應崎舰誠生。而如果使用回餘 ^气（etehbaek)雖可切除電鍍延伸導線，但仍會遺留下電鍵 線尾端部份。gj此在基板上雖形麟電舰域祕/金層之結 ，，但又包含—堆賴導線尾端之統結構。當然，降低線_ 叹面積讀及在喊使㈣產生雜訊干擾之問驗舊存在，進而 影響電訊傳輸品質。 【發明内容】 習知技藝的缺點 據此，本發明之主要目的即在於提出一種改良之封裝基板之製 作方法’可不需於職基板上另佈設電麟/金導線，以改善前述 本發明之另—目的即在於提出—種職基板之製作方法，可以 在封裝基板之第-、第二表面待織輯上進行關種類之表面 處理材料。 根據本發$讀雜關，本發贿供—觀裝級之 法，包含有下列步驟： 提供-基材，在該基材的第—、第二表面上分顺有—第一銅 層以及一第二銅層； 進行線路圖案化製程，將該第一銅層定義形成一第一線路圖 1305406 '案’其中該第—線關案包含有至少—待電鍍區域，且該待電鍍 區域經由一電鍍導通孔與該第二銅層電性連結； 又 ' 於該基材的第―、第二表面上設置-級層，且該光阻層於該 基材的第-表面上形成有待電鍍區類σ，以暴露出該 區 域； 於該待電鑛區域内電鍍一金屬層； 剝除該光阻層； • 進行線路圖案化製程，將該第二銅層定義形成-第二線路圖 案’其中該第二線路圖案包含有至少一電性接觸區域，且該電性 接觸區域經由該電鍍導通孔與該第一線路圖案電連結； ▲於該紐的第-、第二表面上碱—絕緣保護層，麟絕緣保 護層於該基材㈣-、第二表面上分卿成#開口，以分別暴露 出該待電鍍區域及電性接觸區域；以及 於該電性接觸區域内形成一保護層。 鲁 根據柄^狀較佳實齡彳，本發$提供—種封裝基板之製 造方法’包含有下列步驟： 提供基材，在該基材的第一、第二表面上分別設有一第一銅 層以及一第二銅層； 進行線路圖案化製程，將該第二銅層定義形成一第二線路圖 案，其中該第二線路圖案包含有至少一電性接觸區域，且該電性 接觸區域經由—電料通孔與該第-銅層f性連結； 於該基材的第―、第二表面上形成一光阻層，且該光阻層於該 基板的第-表面上形成有電性接觸區細口，暴露出該電性接觸 1305406 區域； 於該電性接觸區域内形成一保護層； 剝除該光阻層； 進行線路圖案化製程，將該第一銅層在該基材的第一表面上定 義形成一第一線路圖案，其中該第一線路圖案包含有至少一待電 鍍區域，且該待電鍍區域經由該電鍍導通孔與該第二線路圖案電 連結； 於該基板的第-、第二表面第二表面上形成—絕緣保護層且 該絕緣保護層於該基板的第一、第二表面上形成有開口，暴露出 該待電鍍區域及電性接觸區域；以及 於該待電鍍區域内電鍍一金屬層。 為了使貝審查委員能更進一步瞭解本發明之特徵及技術内 容’請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與_說賴，並非縣財發明加職制者。 【實施方式】 5月參閱第1圖至第I5圖’其繪示的是根據本發明較佳實施例 之封裝基板製作方法剖面示意圖。 首先，如第1圖所示，提供—基材1G，其包含有—核心層12， 以及分別設於基材10的第一表面13及第二表面15之第一底銅層 14及第二底銅層16。其中，哕仿,、、、爲mθ 一 4捕〜層12可以是絕緣層或已完成 1305406 别段線路製程之電路板，但不限於此。 接著’如第2圖所示，進行一鑽通孔處理，以機械方式在基材 ίο中鑽出至少一貫穿核心層12與第一及第二底銅層i4，i6之通孔 18 ° 如第3圖所示，接著進行一通孔金屬化(咖通灿⑽製程， 同時於基材1G的表面上以及祕之通孔18的内麵上沈積一 化學晶種層⑽未示），接者進行電鍍触.第—及第二底銅層 14，16與通孔18表面形成一銅層2〇。而該通孔18則形成電性連接 上下底銅層之電鍍導通孔19。 如第4圖所示，接下來，針對前述之電鑛導通孔19進行一塞 孔製程’在電鱗航19 _滿_ 22等㈣。完成塞孔製程 之後’此時，基材1G的第—表面13及第二表面15皆為一平扭的 表面，以利後續進行圖案化線路製程。 第圖斤丁接著利用微景娜光及顯景多)及钕刻等圖宰化製1305406 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a package substrate, and more particularly to a method of manufacturing a package substrate without forming a metal protective layer for a metal wire of a shovel. [Prior Art] In recent years, the manufacturers of semiconductor chip package substrates (or ic carrier boards) are facing many key processes in manufacturing processes, such as the lighter and smaller electronic products and the electronic production technology. challenge. As is familiar to those skilled in the art, in the fabrication process of the package substrate, in addition to the formation of fine material briquettes thereon, the I/O contacts on the various conductor lines usually need to be remineralized. The so-called "soft gold" on the upper layer, that is, the record / gold (four) system to raise the phase-loading substrate and "the paste to carry out the money to form a stable - sexual connection" while the nickel / gold layer also has a pattern to prevent copper The function of the oxidation of the quality wire. The secret of the conventional electric/gold surface treatment is carried out after the solder mask on the substrate surface of the professional copper circuit. Therefore, it is required in the area not covered by the anti-riding The wire is extended from the wire of the New Zealand 仏 魏 wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei wei. ..., and the main disadvantage of the above known method is that the electroplated extension wire is bound to occupy a clear wiring space on the surface of the sealing plate 1305406, so that the wiring density of the substrate cannot be improved. In addition, when used, the wire is recorded Waiting for the telecommunications quality of the New Zealand area, and the antenna effect of the handle Sakisaki Sang Sang, and if you use the back gas (etehbaek), although the electroplated extension wire can be cut off, the tail end of the electric button wire will still be left behind. Gj is on the substrate, although it is a secret or gold layer. The knot, but it also contains the structure of the tail end of the wire. Of course, the reduction of the line sigh area reading and the occurrence of noise interference in the shouting (4), and thus affect the quality of telecommunications transmission. Disadvantages of the Invention According to the present invention, the main object of the present invention is to provide an improved method for fabricating a package substrate, which can be used to provide an additional electric/gold wire on the substrate to improve the foregoing invention. - The method for manufacturing the seed board can be used to perform the type of surface treatment material on the first and second surfaces of the package substrate. According to the present invention, the method of bribery-viewing level is The method comprises the steps of: providing a substrate, and having a first copper layer and a second copper layer on the first and second surfaces of the substrate; performing a circuit patterning process to define the first copper layer Forming a first line diagram 13 05406 '案', wherein the first-line pass includes at least - a region to be plated, and the region to be plated is electrically connected to the second copper layer via a plated via; and the first and the second of the substrate a second layer is disposed on the surface of the substrate, and the photoresist layer forms a region σ to be plated on the first surface of the substrate to expose the region; plating a metal layer in the region to be electroplated; stripping the a photoresist layer; • performing a line patterning process to define the second copper layer to form a second line pattern, wherein the second line pattern includes at least one electrical contact region, and the electrical contact region is turned on via the plating The hole is electrically connected to the first line pattern; ▲ an alkali-insulating protective layer on the first and second surfaces of the button, and a lining insulating protective layer on the substrate (four)-, the second surface Exposing the area to be plated and the electrical contact area respectively; and forming a protective layer in the electrical contact area. The method for manufacturing a package substrate according to the handle is preferably provided with the following steps: providing a substrate, and respectively providing a first copper on the first and second surfaces of the substrate a layer and a second copper layer; performing a line patterning process to define the second copper layer to form a second line pattern, wherein the second line pattern includes at least one electrical contact region, and the electrical contact region An electric material via hole is f-connected to the first copper layer; a photoresist layer is formed on the first and second surfaces of the substrate, and the photoresist layer is electrically formed on the first surface of the substrate a contact opening, exposing the electrical contact 1305406 region; forming a protective layer in the electrical contact region; stripping the photoresist layer; performing a line patterning process, the first copper layer on the substrate Forming a first line pattern on a surface, wherein the first line pattern includes at least one area to be plated, and the area to be plated is electrically connected to the second line pattern via the plated via; Second surface second table Forming an insulating protective layer on the surface, and the insulating protective layer is formed with an opening on the first and second surfaces of the substrate to expose the area to be plated and the electrical contact area; and plating a metal layer in the area to be plated . In order to make the members of the present invention more aware of the features and technical contents of the present invention, please refer to the following detailed description of the invention and the accompanying drawings. However, the drawings are for reference only and _ said, not the county financial invention plus the system. [Embodiment] Referring to Figures 1 to 5, May, a schematic cross-sectional view showing a method of fabricating a package substrate according to a preferred embodiment of the present invention is shown. First, as shown in FIG. 1, a substrate 1G is provided, which includes a core layer 12, and first and second copper layers 14 and 14 respectively disposed on the first surface 13 and the second surface 15 of the substrate 10. Bottom copper layer 16. Wherein, the imitation, the, and the mθ-4 trapping layer 12 may be an insulating layer or a circuit board that has completed the line process of 1305406, but is not limited thereto. Then, as shown in FIG. 2, a through hole processing is performed to mechanically drill at least one through hole 18 through the core layer 12 and the first and second bottom copper layers i4, i6 in the substrate ίο As shown in Fig. 3, a through-hole metallization process is also performed (the process of depositing a chemical seed layer (10) on the surface of the substrate 1G and the inner surface of the via hole 18, not shown). The electroplating contacts are formed. The first and second bottom copper layers 14, 16 form a copper layer 2 on the surface of the via hole 18. The through hole 18 is formed with a plating via 19 electrically connected to the upper and lower bottom copper layers. As shown in Fig. 4, next, a plugging process is performed for the aforementioned electric ore via 19, and the electric scale is 19 _ full _ 22 or the like (four). After the plugging process is completed, the first surface 13 and the second surface 15 of the substrate 1G are both flattened surfaces for subsequent patterning process. The first figure of Jin Ding then used the micro-jingna light and the landscape to show more)
程，將基材10的第一表面13上的筮化I 囟13上的第一底銅層14以及銅層20圖 案化定義出第一線路圖案24。 如第6圖所示，在基^1Λ 隹暴材1〇的第一表面13及第二表面15上面 同時覆蓋一光阻層30。銶接，制m ^ + 乳後利用圖案化製程，在基材10的第一 1305406 表面13上的雜層3G巾形鱗電鍍區糊口 3卜城待電鑛區 域開口 31暴露出基材1〇上的部分第一線路圖案^以形成一待電 鑛區域32。此待電鍍區域32 一般被稱作為「打線塾^^㈣ pad)」。其中，該待電趣域32 —般係用於供半導體晶片打金線於 封裝基板時所用之電性連接墊。 第圖所示’進行一電鑛製程，在基材！㈣第一表面13上 的待電舰域32 ’鏟上—第—金屬層34，其中該第—金屬層一般 為錄/金層。本㈣之—主要概即在赠狀魏金屬過程中， 係經由基材10的第二表面上的銅層，以及電鍍導通孔D，提 供待電鍍區域32進行驗製轉f要的電鱗通路徑。 驻因本㈣之轉伽在料轉另外軸電舰伸導線， 曰此提昇封裝基板的佈線密度，並且可以避免電鍍延伸導線所導 致的訊號干擾及雜訊問題。 如第8圖所示’完成第一金屬層34的電鐘製程之後，隨即將 材0的第-表面13及第二表面15上的光阻層邓剝除。 15如第9圖所示，接著進行圖案化製程，將基材10的第二表面 上的第二底銅層16以及銅層20圖案化定義出第二線路圖案26。 如第1〇圖所示’接下來’在基材10的第一表面13及第二表 11 1305406 面15上同時形成一絕緣伴罐思w 呆。蔓層40，其中該絕緣保護層40 —般係 為業界所謂的「綠漆」或「防揑 版诉 」X丨方谇層」。爾後進行圖案化製程將該第 ^二表面上之絕緣保護層4_化，以形成有複數開口 41， 以顯露出第—表面13之第-金屬層34及第二表面15上的第二線 路圖案26後續欲電鍍金屬層的電性接觸區域42。 ㈣此 1卜，明之另—特徵在於基材ig第一表面13上的絕_ 麵層之後細彡成，因此，齡部分覆蓋至| 第一金屬層34。 根據本發a狀較佳實麵，接下來可財紐η帛二表面1 上電性接觸區域42内電鍍形成與基材ig第一表面13相同細 金屬層，其流程如同第11圖至第15圖所繪示者。 又’根據本發明之另一較佳實施例，如第16圖所緣示者，在 基^ 1〇第二表面15上之電性接觸區域42可以覆蓋形成與基材1〇 第表面13不同種類的非金屬材料膜9〇，例如，有機保焊劑 (organic solder-abilily preservative，〇sp)等等。 目前市面上_膠球閘_(PBGA)封裝基板產品的第一、第二 表面表面處理錢同—種類，脚、第二表面絲處理都是 又金屬層且第一、第二表面的種類相同。但市場上對於第一、 第一表面表面處理分屬抑規格的歸球神雕B GA)等此類封 12 1305406 裝基板產品亦有其需求’因此，本發明之另一優點在於所提供之 方法可在第-表面為鍍金屬層處理，而在第二表賴以有機保焊 劑代替鑛金屬之表面處理。 以下即配合第11圖至第15圖所繪示者，詳細說明本發明較佳 實關在紐1G第二表面15上電性接觸區域42喊鍍形成與基 材10第一表面13相同種類的金屬層之步驟。 如第11圖所示’以無電電錢或減鏟等方式，僅在基材10第-表面13上覆蓋-導電層52，例如銅晶種層㈣d la㈣等。 如第12圖所不，接著，在基材1()的第一表面η及第二表召 5^面同時覆蓋一光阻層6Q。然後，利用圖案化製程，在基材】 ^-表面15上的光阻層㈣形成開口 61，且開口 61暴露出』 置。—表面15之第：線路_ 26作為電性接樞域42的相 如第13圖所示，進行—電鍍製程 上的電性接觸區域42㈣μ ㈣一表 凰、Ά 、又上一第二金屬層64。於前述之電身 屬過程中，係經由基材 、狀〈电菊 路圖案-以及電錢^一:面㈣^ 製程所需要的電流導通;^19 編域42進行電 13 1305406 基屬層64的電鍍製程之後，隨印將 、第表面13及第二表面15上的光阻層6〇剝除。 1，如第15圖所示，將導電層52從基材10的第-表面13去 除，即完成本發3月封裝基板之製作。 美滅不限於如第1圖至第15财所繪示「先形成 表面之打線塾之鍍金屬層，後形成基板第二表面電性接 ❿賴域之表面處理」之步驟順序，亦可以進行如第17圖至第29 「先形成餘第二表面電性接觸區域之鍍金屬層，後形 、土苐-表面之打線墊之表面處理」之步驟順序。 、下Ρ藉由第17圖至第29圖簡要說明本發明另一實施例「先 =成基板第二表面電性接觸_之鍍金屬層層，後形成基板第一 表面之打線墊之表面處理」之步驟順序。 如第17圖所示，提供—基材⑴，其職包含有—核心層⑴ =別:於基材10巧一表面13及第二表面Μ之第一底銅層 姑川_ 16 °接者’進行—綱孔處理，以機械方式在基 材Κ)中鑽㈣'-貫穿核心層12與第—及第二底銅層ΐ4，ΐ6之通 。接著進行-通孔金屬化製程，於基材1〇的表面上以及電鍍 二孔I9的侧壁上’沈積—化學晶種層(圖未示〕，接者進行電鑛 裏程以於第-及第二底鋼層14，16與通孔18表面形成—銅層2〇， 而該通孔18靡彡成紐連接上下底崎之顿導通孔19。接下 1305406 來，進行-塞孔製程，在電鍍導通孔19内填滿樹脂22等材料。 =絲孔製程之後，此時，基材1G的第—表面13及第二表面15 皆為一平坦的表面，以利後續進行圖案化線路製程之進行。 如第18圖所不，接著利用微影及韻刻等圖案化製程，將基材 10的第二表面15上的銅棚案化絲出第二線路圖案％。 如第19圖所示’在基材10的第一表面13及第二表面15上面 同時覆蓋雜層6G。錢，利關案化製程，在基材1()的第二表 …上的光阻層60中形成電性接觸區域開口 &，且該電性 區域開叫暴露出基材K)上的部分第二線路_ 26以形成— 性接觸區域42。 電 如第20圖所示，進行—電鍍製程，在基材ι〇的第二表面Η 上的電性接觸區域42鍍上一層第二金屬層64。 如第麟示，完成基㈣第二表面15上的第二金屬層糾 沾二鍍製程之後，隨即將基材1〇的第一表面13及第二表面 的光阻層60完全剝除。 如第22圖所示，接著進行圖案化製程，將基材ι〇的第 上的鋼層，圖案化定義出第一線路圖案24。 如第23圖所示，接下來，在基材ω的第—表面13及第二表 15 1305406 面15上同時形成一絕緣保護層4〇。由於在基材ι〇第二表面u / 舰雜護層4G或「鱗」或「_層」係在魏完第二金屬層64 之後始频’目此，齡部分覆蓋雕二金屬層Μ有部分的重疊。 此外，在紐10第一表面13上，絕緣保護層40中形成有開 口 41 ’暴露出基材10第—表面13上的第—線路_ 24的—待電 鍍區域32。根據本發明之較佳實施例，接下來可以在基材1〇第一 _ 表面13上待電鍍區域32内電鍍形成與基材10第二表面15相同 種類的金屬層，其流程如同第24圖至第28圖所綠示者。 又，根據本發明之另一較佳實施例，如第29圖所繪示者，在 基材10第一表面13上之待電鍍區域32可以形成與基材1〇第二 表面15不同麵的非金屬材料膜9〇，例如，有機保焊劑(〇聊^ solder-ability preservative，〇sp)等等，將基材 1〇 第—表面 u 上的 銅質「打線墊」區域覆蓋住，避免其氧化。 如第24圖所示，以無電電鍍或濺鍍等方式，僅在基材ι〇第二 表面15上覆盍一導電層52，例如銅晶種層(see(j iayer)等。 如第25圖所示，接著，在基材10的第一表面13及第二表面 15上面同時覆蓋_光阻層3〇。然後，利用圖案化製程，在基材⑴ 的第一表面13上的光阻層30中形成一開口 31，且開口幻暴露出基 材10第一表面13之第一線路随24作為待電鍵區域32的位置。 16 1305406 *.上的如二26圖所示，進行一電鍍餘，在基材w的第-表面13 ， 场㈣_/金_32位置鍍上—第—金屬層34。 基材n細34纖版後，隨即將 、表面】3及第二表面】5上的光阻層3〇剝除。 最後’如第28圖所示，將導電層52從基材1〇的第二表面^ 去除，即完成本發明封裝基板之製作。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應羼本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第15圖繪示的是根據本發曰月較佳實施例之封震基板 • 第-、第二表面形成相同種類材質之製作方法之剖面示意圖: 第16圖繪示的是根據本發明較佳實施例之封裝基板第一、第 二表面形成不同種類材質之製作方法之剖面示意圖。 第Π圖至第28圖繪示的是根據本發明另一較佳實施例之封裂 基板第-、第二表面形成相同種類材質之製作方法之剖面示意圖: 第29圖搶示的是根據本發明另-較佳實施例之封裝基板第 —、第二表面形成不_類材質之製作方法之剖面示意圖。 17 1305406 【主要元件符號說明】 10 基材 12 核心層 13 第一表面 14 第一底銅層 15 第二表面 16 第二底銅層 18 通孔 19 電鍍導通孔 20 銅層 22 樹脂 24 第一線路圖案 26 第二線路圖案 30 光阻層 31 待電鍍區域開口 32 待電鐘區域 34 第一金屬層 40 絕緣保護層 41 開口 42 電性接觸區域 52 導電層 60 光阻層 61 開口 64 第二金屬層 90 非鎳/金材料膜 18The first underlying copper pattern 14 on the first surface 13 of the substrate 10 and the copper layer 20 on the first surface 13 of the substrate 10 are patterned to define a first line pattern 24. As shown in Fig. 6, a photoresist layer 30 is simultaneously covered on the first surface 13 and the second surface 15 of the substrate 1 . After the m ^ + milk is used, the patterning process is performed on the surface 1 of the first 1305406 of the substrate 10, and the 3G towel-shaped scale plating area 3 is exposed to the substrate 1 A portion of the first line pattern is formed to form a to-be-grounded area 32. This area to be plated 32 is generally referred to as "line 塾^^(4) pad)". The electrical area 32 is generally used for an electrical connection pad for use in mounting a semiconductor wafer on a package substrate. Figure 1 shows an electric ore process in the substrate! (d) The to-be-grounded area 32 on the first surface 13 is shovel-first metal layer 34, wherein the first metal layer is generally a recording/gold layer. (4) - mainly in the gifted Wei metal process, through the copper layer on the second surface of the substrate 10, and the plating via D, providing the area to be plated 32 for the inspection and conversion of the electric scale path. According to this (4), the transfer gamma is transferred to another shaft electric ship to extend the wire, thereby increasing the wiring density of the package substrate, and avoiding signal interference and noise caused by plating the extended wire. After the completion of the electric clock process of the first metal layer 34 as shown in Fig. 8, the photoresist layer on the first surface 13 and the second surface 15 of the material 0 is stripped. As shown in Fig. 9, a patterning process is then performed to pattern the second underlying copper layer 16 and the copper layer 20 on the second surface of the substrate 10 to define the second line pattern 26. As shown in Fig. 1 'next', an insulating ferrule is simultaneously formed on the first surface 13 of the substrate 10 and the surface 15 of the second surface 11 1305406. The vine layer 40, wherein the insulating protective layer 40 is generally referred to as the so-called "green lacquer" or "anti-pinch version" X 丨 square layer. Then, a patterning process is performed to form the insulating protective layer on the second surface to form a plurality of openings 41 to expose the first metal layer 34 of the first surface 13 and the second line on the second surface 15. The pattern 26 is subsequently plated with an electrical contact region 42 of the metal layer. (4) This is characterized in that the surface layer on the first surface 13 of the substrate ig is finely divided, and therefore, the aged portion is covered to the first metal layer 34. According to the preferred embodiment of the present invention, the same fine metal layer as the first surface 13 of the substrate ig is formed by electroplating in the surface 1 of the upper surface 1 of the second surface of the substrate. The flow is as shown in FIG. 11 to Figure 15 shows the person. Further, in accordance with another preferred embodiment of the present invention, as shown in FIG. 16, the electrical contact region 42 on the second surface 15 of the substrate may be covered to form a different surface than the first surface 13 of the substrate 1 A type of non-metallic material film, for example, an organic solder-abilily preservative (〇sp) or the like. At present, the first and second surface surfaces of the PBGA package substrate product are treated with the same type, the foot and the second surface wire are both metal layers and the first and second surfaces are of the same type. . However, there is also a demand for such a 12 1305406 substrate product for the first and first surface surface treatments, which are classified as a standard, and so on. Therefore, another advantage of the present invention is that it is provided. The method can be treated with a metallized layer on the first surface and a surface treated with an organic solder resist instead of the mineral metal on the second surface. Hereinafter, in conjunction with FIGS. 11 to 15 , the present invention is described in detail. The preferred embodiment of the present invention is to provide the same type of electrical contact region 42 on the second surface 15 of the New 1G as the first surface 13 of the substrate 10 . The step of the metal layer. As shown in Fig. 11, the conductive layer 52 is covered only on the first surface 13 of the substrate 10 by means of no electricity or reduced shovel, for example, a copper seed layer (d) d la (four) or the like. As shown in Fig. 12, next, a photoresist layer 6Q is covered on both the first surface η and the second surface of the substrate 1(). Then, using the patterning process, an opening 61 is formed in the photoresist layer (4) on the substrate], and the opening 61 is exposed. - the surface 15: the line _ 26 as the electrical junction field 42 as shown in Figure 13, the electrical contact area on the electroplating process 42 (four) μ (four) a phoenix, Ά, and a second metal layer 64. In the process of the above-mentioned electric body, the current required by the substrate, the shape of the electric chrysanthemum pattern, and the electric money ^1: surface (four) ^ process is turned on; ^19 the domain 42 is used to conduct electricity 13 1305406 basic layer 64 After the electroplating process, the photoresist layer 6 on the first surface 13 and the second surface 15 is removed. 1. As shown in Fig. 15, the conductive layer 52 is removed from the first surface 13 of the substrate 10, that is, the fabrication of the package substrate of the present invention is completed. Meishen is not limited to the sequence of steps shown in Figure 1 to Figure 15 "the surface of the metallization layer of the surface of the substrate is formed first, and then the surface treatment of the second surface of the substrate is formed". For example, the sequence of steps from the 17th to the 29th "first forming the metallized layer of the second surface electrical contact area, the surface treatment of the back shape, the soil-surface wire pad". FIG. 17 to FIG. 29 schematically illustrate a surface treatment of a metallization layer of a first surface of a substrate, and a metallization layer of a first surface of the substrate, which is formed by another embodiment of the present invention. The sequence of steps. As shown in Fig. 17, the substrate (1) is provided, and its core layer (1) is included: the surface of the substrate 10 and the surface of the second surface are the first copper layer. 'Processing - the hole treatment, mechanically drilling in the substrate () (4) '-through the core layer 12 and the first and second bottom copper layers ΐ4, ΐ6. Then, a through-hole metallization process is performed to deposit a chemical seed layer on the surface of the substrate 1 and on the sidewall of the plated two-hole I9 (not shown), and the electrification mileage is used for the first And the second bottom steel layer 14, 16 forms a copper layer 2 与 with the surface of the through hole 18, and the through hole 18 is connected to the upper and lower slabs of the through hole 19. The next 1305 406 is used to perform the plug hole process. The plating via 19 is filled with a material such as a resin 22. After the wire hole process, at this time, the first surface 13 and the second surface 15 of the substrate 1G are all a flat surface for subsequent patterning. The process proceeds. As shown in Fig. 18, the copper pattern on the second surface 15 of the substrate 10 is then subjected to a second line pattern % by a patterning process such as lithography and rhyme. The first surface 13 and the second surface 15 of the substrate 10 are shown to simultaneously cover the impurity layer 6G. The money is processed in a photoresist layer 60 on the second surface of the substrate 1 (). Forming an electrical contact area opening & and the electrical area opening reveals a portion of the second line _ 26 on the substrate K) to form a sexual contact area 42. Electrical As shown in Fig. 20, an electroplating process is performed to coat a second metal layer 64 on the electrical contact region 42 on the second surface Η of the substrate. After the completion of the second metal layer etching process on the second surface 15 of the base (4), the first surface 13 of the substrate 1 and the photoresist layer 60 of the second surface are completely stripped. As shown in Fig. 22, a patterning process is then performed to pattern the first steel layer of the substrate ι by defining the first line pattern 24. As shown in Fig. 23, next, an insulating protective layer 4 is simultaneously formed on the first surface 13 of the substrate ω and the surface 15 of the second surface 15 1305406. Since the second surface u / ship barrier layer 4G or the "scale" or "_ layer" of the substrate ι〇 is in the beginning of the second metal layer 64, the age portion is covered with the two metal layers. Partial overlap. Further, on the first surface 13 of the button 10, an opening 41' is formed in the insulating protective layer 40 to expose the to-be-plated region 32 of the first line _24 on the first surface 13 of the substrate 10. According to a preferred embodiment of the present invention, a metal layer of the same kind as the second surface 15 of the substrate 10 may be electroplated in the region 32 to be plated on the first surface 13 of the substrate 1 as shown in Fig. 24. To the green of the 28th. Moreover, in accordance with another preferred embodiment of the present invention, as shown in FIG. 29, the region 32 to be plated on the first surface 13 of the substrate 10 may be formed to be different from the second surface 15 of the substrate 1 The non-metallic material film 9〇, for example, a solder-resist preservative (〇sp), etc., covers the copper "wire pad" area on the substrate 1 - surface u, avoiding it Oxidation. As shown in Fig. 24, a conductive layer 52 is coated on the second surface 15 of the substrate ι, such as a copper seed layer (see iayer) or the like by electroless plating or sputtering. As shown, next, the photoresist layer 3 is simultaneously covered on the first surface 13 and the second surface 15 of the substrate 10. Then, the photoresist on the first surface 13 of the substrate (1) is patterned by a patterning process. An opening 31 is formed in the layer 30, and the opening reveals a first line of the first surface 13 of the substrate 10 as a position to be the key area 32. 16 1305406 *. As shown in FIG. I, on the first surface of the substrate w, the field (four) _ / gold _32 position plated - the first metal layer 34. After the substrate n fine 34 fiber version, then, surface 3 and the second surface] 5 The photoresist layer 3 is stripped. Finally, as shown in Fig. 28, the conductive layer 52 is removed from the second surface of the substrate 1 to complete the fabrication of the package substrate of the present invention. The preferred embodiments of the present invention are intended to be within the scope of the present invention. FIG. 1 to FIG. 15 are schematic cross-sectional views showing a method of fabricating the same type of material according to the preferred embodiment of the present invention; FIG. 16 is a view A cross-sectional view showing a method of fabricating different types of materials on the first and second surfaces of the package substrate according to a preferred embodiment of the present invention. FIGS. 28 to 28 illustrate a cracked substrate according to another preferred embodiment of the present invention. FIG. 29 is a schematic view showing a method for forming a non-type material on a first surface and a second surface of a package substrate according to another preferred embodiment of the present invention. 17 1305406 [Description of main components] 10 substrate 12 core layer 13 first surface 14 first bottom copper layer 15 second surface 16 second bottom copper layer 18 through hole 19 electroplated via 20 copper layer 22 resin 24 first line pattern 26 second line pattern 30 photoresist layer 31 area to be plated opening 32 to be clocked area 34 first metal layer 40 insulating protective layer 41 opening 42 electrical contact area 52 conductive 60 a second photoresist layer 61 opening 64 non-metal layer 90 of nickel / gold material film 18