200807658 九、發明說明： 【發明所屬之技術領域】 1 本發明係關於一種封裝基板之製造方法，尤指一種無需形成電 鍍金屬導線電鍍金屬保護層之封裝基板製造方法。 【先前技術】 近年來，隨著電子產品輕小化的趨勢以及電子產業相關技術的 _ 快速提昇，半導體晶片封裝基板(或稱ic載板)製造業者正面臨著 許多製程上的關鍵及挑戰。 如熟習該項技藝者所知，封裝基板之製作過程中，除了於其上 形成細密的導線圖案(一般為銅質導線)之外，且各導線線路上的 接2通$另而再鍍上一層所謂的「軟金」，也就是鎳/金^U) f ’以提升封裝基板與⑼之财進行打金線擁中構成穩固的 Φ电性連接’同時’此錄/金層亦有防止®案化銅質導線氧化之功能。 習知電鍍錄/金表面處理之作法係在具圖案化銅質線路之基板 ==剛伽攸。，蝴剛遮蔽之區 有4板表面上⑼路延伸絲板關之電鍍延伸導線 露 作她轉幢。城，獅基板上外 '曰之各待鍍金區域上魏—層特定厚度的鎳/金層。200807658 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a package substrate, and more particularly to a method of manufacturing a package substrate which does not require the formation of a metal plating layer for electroplating metal wires. [Prior Art] In recent years, with the trend of miniaturization of electronic products and the rapid advancement of related technologies in the electronics industry, manufacturers of semiconductor chip package substrates (or ic carrier boards) are facing many key challenges and challenges in the manufacturing process. As is known to those skilled in the art, in the fabrication process of the package substrate, in addition to forming a fine wire pattern (generally a copper wire) thereon, and the connection on each wire line is further plated. A layer of so-called "soft gold", that is, nickel / gold ^ U) f 'to enhance the package substrate and (9) for the gold wire to form a solid Φ electrical connection 'at the same time' this record / gold layer also prevent ® The function of oxidizing copper wire. The conventional plating/gold surface treatment is performed on a substrate with a patterned copper line == Gengjia. The area that has just been shaded has a plated extension wire on the surface of the 4th board (9) extending the silk plate. On the outside of the city, the lion's substrate is surrounded by a layer of nickel/gold with a specific thickness on the gilded area.
Kj 然而 述驾知作去之主要缺點在於電鍍延伸導線勢必佔據封 6 200807658 裝基板表面可利用的佈線空間，使得基板的佈線密度無法提升。 此外’在高頻制時，因錄之電料線會影響待魏區域之電 ^訊品f，而為所謂的天線效應而造成雜訊產生。而如果使用回: 刻方式（Eetchback)雖可切除電鍍延伸導線，但仍會遺留下電參 導線尾端部份。因此在基板上雖形成待電鍍區域有錄/金層之結X f ’但又包含-堆電鍍導線尾端之紊亂結構。當然，降低線路°佈 设面積密度及在高頻使用易產生雜訊干擾之問題依舊存在 _ 影響電訊傳輸品質。 【發明内容】 據此 ，本發明之主要目的即在於㈣—槪（之雜基板之製 作方法’可不需於職基板上另佈設驗獻金導線， 習知技藝的缺點。 處理材料 本發明之另—目的即在於提出—麵裝基板之製作方法，可以 ，封衣基板之第-、第二表面待鏟覆區域上進行不_類之表面 法 根據本㈣讀佳實關，树0服供_種職絲之製造方 ’包含有下列步驟: 提供一基材，在該基材的第一 層以及一第二銅層； 第二表面上分別設有一第一銅 義形成一第一線路圖 進行線路圖案化製程，將該第一銅層定 200807658 案’其中該第—線路圖案包含 區域經由，導通孔與該第二_==域，且該待電鑛 某::第基、第二表面上設置—光，且該光阻層於該 =的弟—表面上形成有待電舰域如，以暴露出該待電鑛區 於該待電鍍區域内魏-金屬層； 剝除該光阻層； 進行線路職化製程，將該第 索，豆Φ访馀一 a 弋我形成一弟一線路圖 ” /、中以弟一線路圖案包含有至少一電性技g 妹總Ft 电性接觸區域，且該電性 接觸£域_該電鍍導通孔與該第—線路_電連* · 於該基材的第-、第二表面上形成 ;’ 镬芦於兮㈣㈣ 滅喊m且該絕緣保 ^層於該基材的弟-、第二表面上分別形成有開口，以分別暴露 出該待電鑛區域及電性接觸區域；以及 於該電性接觸區域内形成一保護層。 根據本發明以-難實關，本翻提供—觀裝基板之製 &方法，包含有下列步驟： 提供-基材，在縣材㈣―、第二表面上分舰有一第一鋼 層以及一第二銅層； 進行線路_化製程，將料二銅層絲形成—第二線路圖 案’其中該第二線路圖案包含有至少一電性接觸區域，且該電性 接觸區域經由-電鑛導通孔與該第—銅層電性連結； 於該基材的第一、第二表面上形成一光阻層，且該光阻層於該 基板的第-表©上形成有電性接娜域開口，暴露出該電性接觸 200807658 區域； 於該電性接觸區域内形成—保護層； 剝除該光阻層； 路圖案化製程’將該第一銅層在該基材的第一表面上定 蚀 #線路圖案，其中該第一線路圖案包含有至少一待電 、二域，且該待電鑛區域經由該電鐘導通孔與該第二線路圖案電 運結； 兮絕缘伴、第—表面第二表面上形成—絕緣保護層，且 ==_軸帛—^_彡細口，暴露出 違待電鍍區域及電性接觸區域；以及 於該待電鍍區域内電鍍一金屬層。 〜為 JT 、責審查委員能更進一步瞭解本發明之特徵及技術内 下有關本發明之詳細說明與關。細所附圖式僅 供參考與漏說a，並_來對本發明細限制者。 【實施方式】 月 > 閱第1 ϋ至第15圖，麟示的是根據本 之封裝基板製作方法剖面示意圖。 1j把η 首先，如第1圖所示，提供—基材1G，其包含有—核心層12， =職基材10的第一表面13及第二表面15之第一底銅層 及弟-底銅層16。其中，該核心層12可以是絕緣層或已完成 200807658 前段線路抛之魏板，科限於此。 接著如第2圖所不’進行一鑽通孔處理，以機械方式在基材 10中鑽出至少一貫穿核心肩 一 _ 曰12與弟一及弟一底銅層14,16之通孔 18 〇 如第3圖所示，接著進行—通孔金屬化(me刷zation德程， 同t於基材ίο的表面上以及前述之通孔18的内侧壁上沈積一 化學晶種層(圖未示）’接者進行電鍍製程以於第—及第二底銅層 14，16與通孔18表面形成一銅層2〇。而該通孔18則形成電性連接 上下底銅層之電鍍導通孔19。 如第4圖所示，接下來，針對前述之電鍍導通孔19進行一塞 孔製程，在電解通孔19峨_ 22等材料。完成塞孔製程 之後，此時，基材H)的第—表面13及第二表面15皆為一平坦的 表面，以利後續進行圖案化線路製程。 如第5圖所示，接著利用微影(曝光及顯影)及侧等圖案化製 私將基材ίο的第表面13上的第_底銅層14以及銅層圖 案化定義出第一線路圖案24。 如第6圖所示，在基材1G的第-表面13及第二表面15上面 同時覆蓋一光阻層30。然後，利用圖案化製程，在基材10的第— 200807658 表面I3上的光阻層30中形成待電鐘區域開口 Μ，且該 •域開口 Μ暴露出基材H)上的部分第-線路圖案24以形成一料 •鍍區域32。此待電鍍區域32 -般被稱作為「打線_〇nding pad)」。其巾，轉電無域％ —般制於供半導體晶片打金線於 封裝基板時所用之電性連接墊。 如第7圖所示’進行—電鑛製程，在基材10的第-表面13上 _的猶鍍區域32，鍍上—第—金制34，其中該第—金屬層一般 為鎳/金層。本發明之一主要特徵即在於前述之電鍵金屬過程中， 係經由基材10的第二表面15上的銅層，以及電鍍導通孔，提 供待電鍍區域32進行電鍍製程所需要的電流導通路徑。 因此，本發明之主要優點在於不需要另外形成電鍵延伸導線， 藉此提昇封裝基板的佈線密度，並且可以避免電鑛延伸導線所導 致的訊號干擾及雜訊問題。 如第8圖所不’完成第一金屬層34的電鍍製程之後，隨即將 基材10的第-表面13及第二表面15上的光阻層3〇剝除。 如第9圖所示，接著進行圖案化製程，將基材1〇的第二表面 15上的第二底鋼層以及銅層20圖案化定義出第二線路圖案26。 如第10圖所示，接下來，在基材10的第一表面13及第二表 11 200807658 面is上同時形成-絕緣保護層4〇， 為業界所謂的「綠漆」或「_ ^中該痛_ 4G 一般係 一乃筐—矣 €」爾後進仃圖案化製程將該第 一及弟一表面上之絕緣保護層4 靴叫成有稷數開口 4卜 1路出弟—表面13之第—金屬層34及第二表面15上的第一線 路圖案26後續欲電鍍金屬層的電性接觸區域42。 ^ 此外，本發明之另-特徵在於基材1〇第一表Μ 護層40係在f鍍第—麵# .、，彖保 第-金屬層34。顧之後飾成，因此，其會部分覆蓋到 根據本發明讀佳實_，接下來可以祕材ω第二表面Μ 上電性接觸區域42内電鑛形成與基㈣第—表面13相同規格的 金屬層，其流程如同第n圖至第15圖所繪示者。 又’根據本發明之另一較佳實施例，如第16圖所緣示者，在 ，材1〇第二表面15上之電性接觸區域42彳以覆蓋形成與基材⑺ 第一表面13不同種類的非金屬材料膜9〇，例如，有機保焊劑 (organic solder-ability preservative，OSP)等等。 目前市面上的塑膠球閘陣列(PBGA)封裝基板產品的第一、第二 表面表面處理多為同-義，亦即m面表喊理都是 鍍金屬層，且第一、第二表面的種類相同。但市場上對於第一 第二表面表面處理分屬不同規格的塑膠球閘陣列(pbga)等此,封 12 200807658 裝基板產品亦有其需求，因此，本㈣之另-伽在於所提供之 方法可在第-表面騎金顧歧，而在第二表面取保 劑代替鍍金屬之表面處理。 坪 實：在:合二圖严15圖所_，詳細說明本發明較佳 二10第;面13厂面15上電性接觸區域42内電鍍形成與基 材10弟-表面13相同種類的金屬層之步驟。 參 如第11圖所7F，以無電電鑛或濺鍍等方式僅在基材1〇第— 表面13上覆蓋一導電層52，例如銅晶種層㈣㈣等。 如弟12圖所不’接著，在基材1()的第—表面丨3及第二表 :二同時覆蓋一光阻層6。。然後’利用圖案化製程 中形細α6ι，且開_暴_ 置。、面之弟-線路圖案26作為電性接觸區域42的位 如第13圖所示，進行一雷梦，+甘μ 卜沾心 、 鑛衣私在基材10的第二表面15 的包性接觸區域42位置鍍上一第二全屬 屬過程中，係經由基材i。的第一表面13屬：=^ 24，19，^ 衣程所需要的電流導通路徑。 、又 13 200807658 如第14圖所示，完成第二金屬層64的電錢製程之後，隨即將 :材10的第-表面13及第二表面15上的轨層6〇剝除。 -最後’如第15圖所示’將導電層52從基材1〇的第一表面去 除，即完成本發明封裝基板之製作。 另外，本發明並不限於如第！圖至第15圖中所繪示「先形成 基板第-表蚊打、雜之鍍金顧，後形絲板第二表面電性接 •觸區域之表面處理」之步驟順序，亦可以進行如第17圖至第29 圖所繪示「先形成基板帛二表㈣性接樞域之齡屬層，後形 成基板第一表面之打線墊之表面處理」之步驟順序。 以下即藉由第17圖至第29圖簡要說明本發明另一實施例「先 形成基板第二表面電性接觸區域之鍍金屬層層，後形成基板第一 表面之打線墊之表面處理」之步驟順序。 • 如第17圖所示，提供一基材10，其同樣包含有一核心層12， 以及分別設於基材1G的第—表面13及第二表面15之第一底銅層 14及第二底銅層16。接著，進行—鑽通孔處理，以機械方式在^ 材10中鑽出至少-貫穿核心層12與第一及第二底銅層14，16之通 孔18。接著進行-通孔金屬化製程，於基材1〇的表面上以及電鍵 導通孔19的側壁上，沈積一化學晶種層(圖未示），接者進行電鍵 製程以於第-及第二底銅層14，16與通孔18表面形成—鋼層2〇， *該通孔18則形成電性連接上下底銅層之電鑛導通孔19。接下 200807658 ，仃-基孔製程，在電鏟導通孔19内填滿樹脂2等材料。 * 孔製程之後，此時，基材1()的第—表面13及第二表面b - 白…、一平坦的表面，以利後續進行圖案化線路製程之進行。 如—第18騎不’接著細微影及侧賴案化製程，將基材 10的第二表面15上的銅層圖案化定義出第二線路圖案％。 • - „圖所示，在基材1〇的第一表面13及第二表面15上面 同時覆蓋光阻層60。然後，利用圖案化製程，在基材1〇的第二表 面15上的光阻層60中形成電性接觸區域開口 61，且該電性接觸 區域開口 61暴露出基材1〇上的部分第二線路圖案％ 帝 性接觸區域42。 包 如第20圖所示，進行一電鏡製程，在基材1〇的第二表面μ 上的電性接觸區域42鍍上一層第二金屬層64。 如第21圖所示，完成基材1〇第二表面I5上的第二金屬層64 的電鍍製程之後，隨即將基材1〇的第一表面13及第二表面15上 的光阻層60完全剝除。 如第22圖所示，接著進行圖案化製程，將基材1〇的第一表面 13上的銅層，圖案化定義出第一線路圖案24。 Μ 一 如第23圖所示，接下來，在基材10的第一表面13及第二表 15 200807658 面15上同時形成一絕緣保護層4〇。由於在基材1〇第二表面13 • 的絕緣保護層40或「綠漆」或「防焊層」係在電鍍完第二金屬層64 之後始形成’因此，其會部分覆蓋到第二金屬層64有部分的重疊。 此外，在基材10第一表面13上，絕緣保護層40中形成有開 口 41’暴露出基材10第一表面13上的第一線路圖案％的一待電 鍍區域32。根據本發明之較佳實施例，接下來可以在基材第一 φ 表面13上待電鍍區域32内電鍍形成與基材10第二表面15相同 種類的金屬層，其流程如同第24圖至第28圖所繪示者。 又’根據本發明之另一較佳實施例，如第29圖所緣示者，在 基材10第-表面13上之待電鑛區域32可以形成與基材1〇第二 表面I5不同麵的非金屬材料㈣，例如’有機保焊劑㈣心 犯伽，祕_職测^，〇奶等等，將基材1〇第一表面13上的 銅質「打線墊」區域覆蓋住，避免其氧化。 如第24圖所示，以無電電鍍或濺鍵等方式，僅在基材10第二 表面I5上覆蓋-導電層52，例如銅晶種層(微dla㈣等。 ，在基材10的第一表面13及第二表面Kj, however, the main disadvantage of knowing that the electroplated extension wire is bound to occupy the wiring space available on the surface of the substrate, so that the wiring density of the substrate cannot be improved. In addition, in the high-frequency system, the recorded electric wires affect the electrical products f in the Wei area, and the noise is caused by the so-called antenna effect. However, if the Eetchback method can be used to cut off the plated extension wire, the tail portion of the wire electrode will remain. Therefore, on the substrate, a junction of the recording/gold layer, X f ', but a turbulent structure of the end of the electroplated wire is formed. Of course, the problem of reducing the area density of the line layout and the possibility of noise interference at high frequencies still exists _ affecting the quality of telecommunications transmission. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is that (four) - 槪 (the method of manufacturing a hetero-substrate) can eliminate the need to provide an additional test wire on the substrate, which is a disadvantage of the prior art. - The purpose is to propose a method for fabricating a surface-mounted substrate, which can be performed on the first and second surfaces of the sealing substrate on the surface to be shoveled. According to the (4) reading Jiashiguan, the tree 0 service _ The manufacturer of the seed yarn includes the following steps: providing a substrate on the first layer of the substrate and a second copper layer; and forming a first copper pattern on the second surface to form a first circuit pattern a circuit patterning process, the first copper layer is set to 200807658, wherein the first line pattern includes a region via, a via hole and the second _== domain, and the to-be-grounded mine:: the base and the second surface Setting a light, and the photoresist layer forms a to-be-grounded area on the surface of the body to expose the Wei-metal layer in the area to be electroplated; stripping the photoresist layer ; to carry out the line occupational process, the first cable, the bean Φ visit a 弋 I form a younger one-line diagram" /, the middle-sister-one line pattern contains at least one electrical technology g sister total Ft electrical contact area, and the electrical contact with the domain _ the plating via and the first - Line_Electrical Connection* is formed on the first and second surfaces of the substrate; 'Gourd in the 兮(4)(4) is shouted m and the insulating layer is formed on the second and second surfaces of the substrate Opening, respectively, to expose the to-be-grounded area and the electrical contact area; and forming a protective layer in the electrical contact area. According to the present invention, it is difficult to implement the present invention. The method comprises the following steps: providing a substrate, and having a first steel layer and a second copper layer on the second surface of the county material; and performing a line-chemical process to form a copper-silicon layer- a second circuit pattern ′ wherein the second circuit pattern includes at least one electrical contact region, and the electrical contact region is electrically connected to the first copper layer via an electric ore via; a photoresist layer is formed on the second surface, and the photoresist layer is on the first surface of the substrate Forming an electrical contact with the nano-domain opening to expose the electrical contact 200807658 region; forming a protective layer in the electrical contact region; stripping the photoresist layer; the road patterning process 'the first copper layer is in the An etched # line pattern on the first surface of the substrate, wherein the first line pattern includes at least one to-be-powered, two-domain, and the to-be-grounded area is electrically connected to the second line pattern via the electric clock via hole兮Insulating companion, forming an insulating protective layer on the second surface of the first surface, and ==_axis 帛-^_彡 fine opening, exposing the electroplating area and the electrical contact area; and plating in the area to be electroplated A metal layer. ~ For JT, the responsible review committee can further understand the features and techniques of the present invention and the detailed description and related to the present invention. The drawings are for reference and only a, and _ to the present Detail limiter. [Embodiment] Month > Referring to Figures 1 through 15, a schematic cross-sectional view of a method of fabricating a package substrate according to the present invention is shown. 1j, η First, as shown in FIG. 1, a substrate 1G is provided, which includes a core layer 12, a first surface 13 of the substrate 10, and a first copper layer of the second surface 15 and a brother- Bottom copper layer 16. Wherein, the core layer 12 may be an insulating layer or a board that has been completed in the previous paragraph of 200807658, and the section is limited thereto. Then, as shown in FIG. 2, a through hole processing is performed to mechanically drill at least one through hole 18 through the core shoulder _ 曰 12 and the younger brother and the bottom copper layer 14, 16 in the substrate 10. As shown in Fig. 3, a through-hole metallization is then performed (me brushing zation, depositing a chemical seed layer on the surface of the substrate ίο and the inner sidewall of the aforementioned via 18 (Fig. The soldering process is performed so that the first and second bottom copper layers 14, 16 form a copper layer 2 on the surface of the via hole 18. The via hole 18 is electrically connected to the upper and lower bottom copper layers. Hole 19. As shown in Fig. 4, next, a plugging process is performed for the above-mentioned plating via 19, and materials such as electrolytic vias 19峨22 are completed. After the plugging process is completed, at this time, the substrate H) Both the first surface 13 and the second surface 15 are a flat surface for subsequent patterning circuit processing. As shown in FIG. 5, the first line pattern is defined by patterning the first copper layer 14 and the copper layer on the first surface 13 of the substrate ί by lithography (exposure and development) and side patterning. twenty four. As shown in Fig. 6, a photoresist layer 30 is simultaneously coated on the first surface 13 and the second surface 15 of the substrate 1G. Then, using the patterning process, an opening Μ of the area to be clocked is formed in the photoresist layer 30 on the surface I3 of the surface of the substrate 10, and the opening Μ of the area Μ exposes a portion of the first line on the substrate H) Pattern 24 is formed to form a plating area 32. This area to be plated 32 is generally referred to as "lined_inging pad". The towel, the power transmission has no domain%, and is generally used for the electrical connection pad used for the semiconductor wafer to be gold-plated on the package substrate. As shown in Fig. 7, the electroplating process is carried out on the first surface 13 of the substrate 10, and is plated with a - gold 34, wherein the first metal layer is generally nickel/gold. Floor. One of the main features of the present invention is that in the above-described key metal process, the copper layer on the second surface 15 of the substrate 10 and the via holes are provided to provide a current conducting path required for the electroplating process to be performed in the region 32 to be plated. Therefore, the main advantage of the present invention is that it is not necessary to additionally form a conductor extension wire, thereby increasing the wiring density of the package substrate, and avoiding signal interference and noise problems caused by the extension of the conductor. After the electroplating process of the first metal layer 34 is completed as shown in Fig. 8, the photoresist layer 3 on the first surface 13 and the second surface 15 of the substrate 10 is subsequently stripped. As shown in Fig. 9, a patterning process is then performed to pattern the second bottom layer and the copper layer 20 on the second surface 15 of the substrate 1 to define the second line pattern 26. As shown in FIG. 10, next, the first surface 13 of the substrate 10 and the second surface 11 200807658 are simultaneously formed with an insulating protective layer 4, which is called "green paint" or "_ ^ in the industry. The pain _ 4G is generally a basket - 矣 」 」 尔 尔 尔 尔 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The first line pattern 26 on the first metal layer 34 and the second surface 15 is subsequently plated with an electrical contact region 42 of the metal layer. Further, another feature of the present invention resides in that the first surface of the substrate 1 is laminated on the f-plated surface, and the first metal layer 34 is provided. After the decoration, it will be partially covered to read according to the present invention, and then the second surface of the second surface Μ the electrical contact region 42 can be formed in the same size as the base (four) first surface 13 The metal layer is flowed as shown in Figures n to 15. Further, in accordance with another preferred embodiment of the present invention, as shown in Fig. 16, the electrical contact region 42 is formed on the second surface 15 of the material 1 to cover the first surface 13 of the substrate (7). Different kinds of non-metallic material films, for example, organic solder-ability preservative (OSP) and the like. At present, the first and second surface treatments of the plastic ball grid array (PBGA) package substrate products on the market are mostly the same meaning, that is, the m surface surface is a metallized layer, and the first and second surfaces are The same type. However, there are also plastic ball shutter arrays (pbga) of different specifications for the first and second surface treatments on the market, and there is also a demand for the packaged products of the package 12200807658. Therefore, the other method of this (4) lies in the method provided. The surface may be massaged on the first surface instead of the metallized surface treatment on the second surface.坪实: In the following: Figure 2, detailing the preferred embodiment of the present invention, the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the surface of the substrate The steps of the layer. Referring to Figure 7F of Fig. 11, a conductive layer 52 such as a copper seed layer (4) (four) or the like is covered only on the substrate 1 surface 13 by electroless ore or sputtering. As shown in Fig. 12, the photoresist layer 6 is simultaneously covered on the first surface 丨3 and the second surface ii of the substrate 1(). . Then 'using the patterning process to form a thin α6ι, and open _ _ _ set. As shown in FIG. 13 , the line pattern 26 as the position of the electrical contact region 42 performs a Raymond dream, and the baggage of the second surface 15 of the substrate 10 is privately held. The location of the contact region 42 is plated with a second all-genus process via the substrate i. The first surface of the 13 is: =^ 24,19,^ The current conduction path required for the clothing process. Further, 13 200807658 As shown in FIG. 14, after the electric money process of the second metal layer 64 is completed, the first surface 13 of the material 10 and the rail layer 6 of the second surface 15 are stripped. - Finally, as shown in Fig. 15, the conductive layer 52 is removed from the first surface of the substrate 1 to complete the fabrication of the package substrate of the present invention. In addition, the present invention is not limited to the first! In the figure to the fifteenth figure, the sequence of the steps of "forming the first surface of the substrate - the mosquito-repellent, the gilding of the miscellaneous, and the surface treatment of the second surface of the rear-shaped silk plate" can also be performed as shown in the figure. 17 to 29 show the sequence of the steps of "forming the surface layer of the first layer of the substrate (the fourth layer) and then forming the surface of the first surface of the substrate". The following is a brief description of another embodiment of the present invention, in which the metallization layer of the second surface electrical contact region of the substrate is formed first, and then the surface treatment of the wire pad of the first surface of the substrate is formed. Step sequence. • As shown in FIG. 17, a substrate 10 is provided, which also includes a core layer 12, and a first bottom copper layer 14 and a second bottom respectively disposed on the first surface 13 and the second surface 15 of the substrate 1G. Copper layer 16. Next, a through-hole processing is performed to mechanically drill at least a through hole 18 through the core layer 12 and the first and second bottom copper layers 14, 16 in the material 10. Then, a through-hole metallization process is performed to deposit a chemical seed layer (not shown) on the surface of the substrate 1 以及 and the sidewall of the key via 19, and then perform a key-bonding process for the first and second The bottom copper layers 14, 16 form a steel layer 2 与 with the surface of the through hole 18, and the through hole 18 forms an electric ore via 19 electrically connected to the upper and lower bottom copper layers. Next, 200807658, the 仃-base hole process is filled with the resin 2 and other materials in the shovel through hole 19. * After the hole process, at this time, the first surface 13 and the second surface b of the substrate 1 () are white, and a flat surface is used to facilitate the subsequent patterning process. The second layer pattern % is defined by patterning the copper layer on the second surface 15 of the substrate 10, e.g., the 18th ride does not follow the lithography and the side process. • - As shown, the photoresist layer 60 is simultaneously overlying the first surface 13 and the second surface 15 of the substrate 1 . Then, the light on the second surface 15 of the substrate 1 is patterned by a patterning process. An electrical contact region opening 61 is formed in the resist layer 60, and the electrical contact region opening 61 exposes a portion of the second line pattern % emperor contact region 42 on the substrate 1 。. As shown in FIG. 20, a In the electron mirror process, a second metal layer 64 is plated on the electrical contact region 42 on the second surface μ of the substrate 1 . As shown in FIG. 21, the second metal on the second surface I5 of the substrate 1 is completed. After the electroplating process of layer 64, the photoresist layer 60 on the first surface 13 and the second surface 15 of the substrate 1 is completely stripped. As shown in Fig. 22, the patterning process is followed to substrate 1 The copper layer on the first surface 13 of the crucible is patterned to define the first line pattern 24. As shown in Fig. 23, next, on the first surface 13 of the substrate 10 and the second surface 15 200807658 surface 15 An insulating protective layer 4 is simultaneously formed on the substrate. Due to the insulating protective layer 40 or "green" on the second surface 13 of the substrate 1 After "or" solder mask "End plating system in the beginning of the second metal layer 64 is formed to overlap with a portion 64 'so that partially covers the second metal layer. Further, on the first surface 13 of the substrate 10, an opening plate 41' is formed in the insulating protective layer 40 to expose a portion to be plated 32 of the first line pattern on the first surface 13 of the substrate 10. According to a preferred embodiment of the present invention, the same type of metal layer as the second surface 15 of the substrate 10 can be electroplated in the region to be plated 32 on the first φ surface 13 of the substrate, as shown in Fig. 24 to Figure 28 shows the person. Further, in accordance with another preferred embodiment of the present invention, as shown in Fig. 29, the area to be electropolished 32 on the first surface 13 of the substrate 10 may be formed to be different from the second surface I5 of the substrate 1 Non-metallic materials (4), such as 'organic solder resist (four) heart gamma, secret _ job test ^, milk, etc., cover the copper "wire pad" area on the first surface 13 of the substrate 1 to avoid Oxidation. As shown in Fig. 24, the electroconductive layer 52 is covered only on the second surface I5 of the substrate 10 by electroless plating or sputtering, for example, a copper seed layer (micro dla (four), etc.), first in the substrate 10. Surface 13 and second surface
如第25圖所示，接著，在基材1〇白 15上面同時覆蓋一光阻層30。然後，利 的第一表面13上的光阻層3〇中形成一開 16 200807658 如弟26圖所7^，進行一電鍍製程，在基材10的第一表面13 、待電鍍鎳/金區域32位置鑛上一第一金屬層。 如弟27圖所示’完成第一金屬層34的電錢製程之後，隨即將 材1〇的第—表面13及第二表面15上的級層3〇剝除。 • 最後，如第28圖所示，將導電層52從基材1〇的第二表面15 去除，即完成本發明封裝基板之製作。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第IS圖缘示的是根據本發日月較佳實施例之封裝基板 春第-、第二表面形成相同種類材質之製作方法之剖面示意圖。 第16 _示的是根據本發明較佳實施例之封裝基板第一、第 二表面形成不同種類材質之製作方法之剖面示意圖。 第17圖至第28 ®繪示的是根據本翻另—較佳實施例之封裝 基板第-、第二表面形成相同種崎f之製作方法之剖面示意圖。 第29圖繪不的是根據本發明另_較佳實施例之封裝基板第 -、第二表面形成不同種類材質之製作方法之剖面示意圖。 17 200807658 【主要元件符號說明】 10 基材 12 核心層 13 第一表面 14 第一底銅層 15 第二表面 16 第二底銅層 18 通孔 19 電鍍導通孔 20 銅層 22 樹脂 24 第一線路圖案 26 第二線路圖案 30 光阻層 31 待電鍛區域開口 32 待電鍵區域 34 第一金屬層 40 絕緣保護層 41 開口 42 電性接觸區域 52 導電層 60 光阻層 61 開口 64 第二金屬層 90 非鎳/金材料膜 18As shown in Fig. 25, next, a photoresist layer 30 is simultaneously covered on the substrate 1 white 15 . Then, an opening process is formed in the photoresist layer 3 on the first surface 13 of the substrate 13 , and an electroplating process is performed on the first surface 13 of the substrate 10 and the nickel/gold region to be electroplated. A 32-position mine has a first metal layer. As shown in Fig. 27, after the completion of the electromoney process of the first metal layer 34, the first surface 13 of the material 1 and the level 3 of the second surface 15 are stripped. • Finally, as shown in Fig. 28, the conductive layer 52 is removed from the second surface 15 of the substrate 1 to complete the fabrication of the package substrate of the present invention. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 1 are schematic cross-sectional views showing a method of fabricating the same type of material in the spring-first and second surfaces of the package substrate according to the preferred embodiment of the present invention. 16 is a schematic cross-sectional view showing a method of fabricating different types of materials on the first and second surfaces of the package substrate according to the preferred embodiment of the present invention. 17 to 28E are schematic cross-sectional views showing a method of fabricating the same type of the second and second surfaces of the package substrate according to the preferred embodiment. Figure 29 is a cross-sectional view showing a method of fabricating different types of materials on the first and second surfaces of the package substrate according to another preferred embodiment of the present invention. 17 200807658 [Description of main components] 10 substrate 12 core layer 13 first surface 14 first bottom copper layer 15 second surface 16 second bottom copper layer 18 through hole 19 electroplated via 20 copper layer 22 resin 24 first line Pattern 26 second line pattern 30 photoresist layer 31 to be electrically forged region opening 32 to be keyed region 34 first metal layer 40 insulating protective layer 41 opening 42 electrical contact region 52 conductive layer 60 photoresist layer 61 opening 64 second metal layer 90 non-nickel/gold material film 18