200948232 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種無導電線電鍍方法，尤指無導電線構裝載 板製作法。 【先前技術】 由於電子產品輕薄短小之趨勢，加上功能之不斷増多，使得 晶片之I/O數快速增加，相對的封裝技術也不斷更新，現今在高 ® 階產品中已多數採用覆晶封裝（Flip Chip)的技術’封裝密度也 隨之不斷地提高。 為了滿足更細線距的高密度載板的需求，必須盡可能保留更 多的佈線空間’尤其是在電麟束後便不再需要賴的導電線更 是值得考慮的對象。具體來說，需要在封賴板的線路層上電鍵 鎳金時’為了將電鑛時所需的電祕人載板，尤其是欲電鑛的線200948232 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a non-conductive wire plating method, and more particularly to a non-conductive wire loading plate manufacturing method. [Prior Art] Due to the trend of thin and light electronic products, and the increasing number of functions, the number of I/Os in the chip has increased rapidly, and the relative packaging technology has been continuously updated. Most of the high-order products have been flip-chip. The technology of the package (Flip Chip) is also increasing in package density. In order to meet the demand for higher-density carrier boards with finer pitches, it is necessary to retain as much wiring space as possible—especially the conductive lines that are no longer needed after the power bundle is more worthy of consideration. Specifically, when it is necessary to switch the nickel-gold on the circuit layer of the board, the electric board for the electric power is required, especially the line of the electric mine.
路層，必須透過姆接於線路層之導電線傳人，義此種做法可 以將線路層完全_電_金層包覆住，但是導電線在完成電鍵 後仍會保留在載板中，而佔用到有限的佈線空間。若欲減少導電 線所佔用的錄空間’而將導電線的寬度作得比較窄時，會導致 所電鍍出來㈣_金層厚度碼勻，因此縮小導電線的寬度仍 不是個提高佈線密度的好辦法。 為了制提高可佈線空_目的，已有許多廠商紛紛提出益 ^線電麵嫩，，樹，物爾線，卻 …、法元全地用额錄金純覆住線路層’亦即僅在線路層上面有 200948232 電鏡鎳金層，侧邊卻無法覆蓋電鑛鎳金。 現有無導電線電鍍技術中以NPL、Bottom Plating、 FBG(GPP)、選擇性鍍金(Selective Gold)、厚化學鎳金(ENAG)為 大宗。然而這些無導電線電鍍均存在者些許的問題。 無電鑛線(Non Plating Line, NPL)提供了一種無須於基板之 表面佈設電鍍導線亦可進行基板電性接觸墊之電鍍鎳/金的設 計，其主要以導電膜作為電流傳導路徑以導通基板上之各電性接 ❹ 觸墊’進而形成晶片封裝基板電性接觸墊之電鍍鎳/金製程與結 構，可大幅減少因電錄導線之佈設而造成之景4響。 NPL、Bottom Plating製程的缺點為流程繁複故成本較高，亦 即若佈線(layout)為同層獨立節點(net)的圖案㈣你叫，有時會很 難以此方式生產’也就是當該net未透過導通孔或via連接至另一 面(例如焊球墊(ball pad)及内層的power & ground)在設計或製造 上會有一些限制。 〇 GPP提供有別於的流程，使得1C載板設計無須於基板 之表面佈設電鐘導線亦可進行基板電性接觸墊之電鑛錄/金的設 '計’減少因電鍍導線之佈設而造成之影響。但由於Gpp需在線路 上皆鍍上鎳金，有成本高及防焊層綠漆與金面的結合力較銅面為 弱的缺點。 選擇性鏡金作法的缺點為製程操作窗(whdow)較小，電鍵錄 金時較易發生滲鍍而影響良率；厚化學鎳金在業界也有一些應 用’但問題點在於化學藥液管控不易，有時會發生化學藥液攻擊 200948232 防焊漆、賴、基材上金與錢制題，另相縣㈣㈣） 造成焊墊與鍚球結合力不良而脫落_〇ff)的問題，對製造者而言 一直是時有耳聞的惡夢。 13 除此之外’亦有廠商提出臨時性導電線的做法，不但避免上 述問題’更可利用可移除導電性的特性，實現高密度载板的目的。 、中華民國專利公告號第126275〇號「一種封裝基板之製造方 法」或第1240400號「防焊製程後的無導線電鑛製程方法」所使用 ❹的無導電線電鍍方法中’其主要通過核心通孔上的電錢金屬，由 载板的背祕魏紐傳遞至欲紐的焊墊上，並在電鍍完成後 移除臨時性的導電線。但是，此方法主要是針對整層金屬又層中某 個部分實施電鍍’而在這部分形成保護層。若是對於獨立的焊塾(和 其他載板中金y|部分均無連接者），此種方法絲法採用。 【發明内容】 ❹ 本發明之主要目的在提供一種無導電線構装載板製作法，其 利用可脫_承載板提供電鍍電流，並在製程結束或無須再電鑛 日守去除承載板，以達到無導電線電鍍的目的。 基於上述目的’在本發明無導電線構裝載板製作法中，主要 先製作出具有分離金屬層⑽的承載板(10) ’並细承載板(10)、 分離金屬層(12)傳遞電鍍電流，而在分離金屬層(12)上依序電鍍出 屬於線路層之蝕刻阻擋層（16)、電鍍金屬層（18)。接著，利用壓合 增層法逐漸完成其他線路層(仍利用承載板(10)傳遞電流），並在製 7 200948232 程結束或無縣電鍍時，去除承載板⑽與分離金屬層⑽，而繼 續完成如防焊製程’無導電線。 關於本發明之優轉精神可以藉由以下的發明詳述及所附圖 式得到進一步的瞭解。 【實施方式】 *月參閱第1A〜1J圖’第1A〜1J圖為本發明無導電線構裝載板 〇 製作法之示意圖。如第lc圖所示，承載板⑽的材質為可導電材 料、分離金屬層(I2)的材質為銅、侧阻擔層⑽的材質為鏡、電 鑛金屬層(I8)的材質為銅。這其中，利用承載板⑽ 、分離金屬層 (12)之間材質上的差異性，可使得承載板⑽得以順利被脫除，如 第1G圖所示。利用餘刻阻擋層⑽、分離金屬層(12)之間材質上 的差異性’在侧去除分離金屬層⑽時不會破壞到侧阻播 層(16)，同時避免破壞到電鍍金屬層(18)，如第出圖所示。 〇 解來說’在本發明無導電賴裝雜製作法巾，主要先製 作出如第1A圖所示之具有分離金屬層(η)的承載板(10)，並如lc 圖所不利用承載板(ίο)、分離金屬層⑽傳遞電鑛電流而在分離 金屬層⑽上依序電鍍出屬於線路層之侧阻擋層⑽、電鐘金屬 層⑽。接著，利用第1E圖所示之壓合增層法逐漸完成其他線路 層(仍利用承載板(ίο)傳遞電流），並在製程結束或無須再電鑛時， 如第1H圖所示去除承載板⑽與分離金屬層⑽，而繼續完成如 防焊製程，以達到無導電線，如第U圖所示。 200948232 具體來說，如第1B圖所示，為了定義出形成線路的位置， 在分離金屬層(12)上形成圖案化光阻層(U)。然後，利用承載板 (1〇)、分離金屬層(12)傳遞電鍍電流，並基於圖案化光阻層㈣而 在分離金屬層(12)上依序電鍍出蝕刻阻擋層(16)、電錢金屬層 (18)(即為線路層），如第1C圖所示。接著，如第1D圖所示去除 該圖案化光阻層(14)。 為了繼續完成载板的其他層面，如第1E〜1F圖所示，將介電 〇 膠膜(2〇)壓合至分離金屬層(12)及其上的與電鑛金屬層(18)，而遮 蔽住分離金屬層(12)與電鑛金屬詹⑽。為了讓屬於、線路層的餘刻 阻擋層(16)、電鍍金屬層(18)能夠對外傳輸訊號，還需進一步進行The road layer must pass through the conductive line connected to the circuit layer. This means that the circuit layer can be completely covered by the electric layer, but the conductive line will remain in the carrier after completing the key, and occupy To limited wiring space. If you want to reduce the recording space occupied by the conductive line and make the width of the conductive line narrower, it will cause the thickness of the (4) _ gold layer to be evenly distributed. Therefore, reducing the width of the conductive line is not a good way to improve the wiring density. Method. In order to improve the wiring of the vacant space, many manufacturers have proposed that the power line is tender, the tree, the object line, but ..., the whole country uses the amount of gold to cover the circuit layer 'that is only in There is a 200948232 electron microscope nickel gold layer on the circuit layer, but the side can not cover the nickel ore. Among the existing non-conductive plating technologies, NPL, Bottom Plating, FBG (GPP), Selective Gold, and Thick Chemical Nickel Gold (ENAG) are the bulk. However, there are some problems with these non-conductive wire plating. The Non Plating Line (NPL) provides a nickel/gold plating design that does not require the plating of wires on the surface of the substrate or the electrical contact pads of the substrate. The conductive film is used as a current conduction path to turn on the substrate. The electrical contact pads of the electrical contacts and the electroplated nickel/gold process and structure of the electrical contact pads of the chip package substrate can greatly reduce the brightness caused by the layout of the electric recording wires. The disadvantage of the NPL and Bottom Plating processes is that the process is complicated and the cost is high, that is, if the layout is a pattern of the same layer independent node (net) (four) you call, sometimes it is difficult to produce in this way 'that is when the net There is some limitation in the design or manufacture of a power & ground that is not connected through vias or vias to the other side, such as ball pads and inner layers. 〇GPP provides a different process, so that the 1C carrier board design does not need to lay the electric clock wire on the surface of the substrate, and the electrical recording/gold design of the substrate electrical contact pad can be reduced to reduce the layout of the electroplated wire. The impact. However, since Gpp needs to be plated with nickel gold on the line, there is a disadvantage that the cost is high and the bonding strength between the green paint and the gold surface of the solder resist layer is weaker than that of the copper surface. The shortcomings of the selective mirror gold method are that the processing window (whdow) is small, the plating is more likely to occur when the gold is recorded, and the yield is affected. The thick chemical nickel gold has some applications in the industry'. However, the problem lies in the difficulty in chemical liquid management. Sometimes chemical liquid attack will occur. 200948232 Anti-welding paint, Lai, gold and money on the substrate, and another county (4) (4)) The problem of poor bonding between the solder pad and the ball is _ 〇 ff) For the time being, it has always been a nightmare. 13 In addition, there are also manufacturers who propose temporary conductive lines, which not only avoid the above problems, but also make use of the characteristics of removable conductivity to achieve high-density carrier. In the non-conductive wire plating method used in the Republic of China Patent Publication No. 126275 No. "Method for Manufacturing a Package Substrate" or No. 1240400 "Wireless Oven Process for Soldering Process" The money metal on the through hole is transferred from the back of the carrier board Wei Wei to the solder pad of the button, and the temporary conductive wire is removed after the plating is completed. However, this method mainly performs plating on a portion of the entire metal layer and forms a protective layer in this portion. If it is for an independent soldering iron (and no connection to the gold y| part of other carriers), this method is used by wire method. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a non-conductive wire-loading plate, which uses a detachable carrier plate to provide a plating current, and at the end of the process or without the need to remove the carrier plate, Achieve the purpose of non-conductive wire plating. Based on the above object, in the manufacturing method of the non-conductive wire-loading plate of the present invention, the carrier plate (10) having the separated metal layer (10) is prepared first, and the thin carrier layer (10) and the separated metal layer (12) are used to transfer the plating current. An etching barrier layer (16) and a plating metal layer (18) belonging to the wiring layer are sequentially plated on the separation metal layer (12). Then, the other circuit layers are gradually completed by the press-bonding layering method (the current is still transmitted by the carrier board (10)), and the carrier board (10) and the separated metal layer (10) are removed while the system is finished at the end of 2009/48, or continue to be electroplated. Complete the soldering process as 'no conductive line'. The spirit of the present invention will be further understood from the following detailed description of the invention and the accompanying drawings. [Embodiment] *Monday refers to Figs. 1A to 1J. Figs. 1A to 1J are schematic views showing a method of manufacturing a non-conductive wire-loading plate. As shown in the figure lc, the material of the carrier plate (10) is a conductive material, the material of the separated metal layer (I2) is copper, the material of the side resist layer (10) is a mirror, and the material of the metallized metal layer (I8) is copper. Among them, the difference in material between the carrier plate (10) and the separation metal layer (12) allows the carrier plate (10) to be smoothly removed, as shown in Fig. 1G. Utilizing the difference in material between the residual barrier layer (10) and the separation metal layer (12), the side barrier layer (16) is not broken when the separation metal layer (10) is removed on the side, while avoiding damage to the plated metal layer (18) ), as shown in the figure above. In the present invention, the carrier sheet (10) having the separated metal layer (η) as shown in FIG. 1A is mainly produced in the non-conductive woven fabric of the present invention, and the carrier is not used as the lc diagram. The plate (ίο) and the separated metal layer (10) transmit an electric current, and the side barrier layer (10) and the electric clock metal layer (10) belonging to the circuit layer are sequentially electroplated on the separation metal layer (10). Next, the other circuit layers (still using the carrier plate) are gradually completed by the press-bonding method shown in FIG. 1E, and the carrier is removed as shown in FIG. 1H at the end of the process or when no further electricity is required. The plate (10) is separated from the metal layer (10) and continues to be completed, such as a solder mask process, to achieve a non-conductive line, as shown in FIG. 200948232 Specifically, as shown in FIG. 1B, in order to define the position at which the line is formed, a patterned photoresist layer (U) is formed on the separation metal layer (12). Then, the plating current is transmitted by the carrier plate (1〇), the separation metal layer (12), and the etching barrier layer (16) is sequentially plated on the separation metal layer (12) based on the patterned photoresist layer (4), and the electricity money The metal layer (18) (ie, the wiring layer) is as shown in FIG. 1C. Next, the patterned photoresist layer (14) is removed as shown in Fig. 1D. In order to continue to complete other layers of the carrier, as shown in FIGS. 1E to 1F, the dielectric silicone film (2〇) is laminated to the separated metal layer (12) and the electro-mineral metal layer (18), The shielding metal layer (12) and the electric metal (Z) are shielded. In order to allow the residual barrier layer (16) and the plated metal layer (18) belonging to the circuit layer to transmit signals externally, further processing is required.
一次或多次鑽孔與填孔電鍍等製程，以形成層間導通孔，如第1G 圖所示在填孔電鑛完成後，視情況作研磨拋光，並且視情況作 電鑛錄金處m。需特別注意的是’上述電鑛製程均可利用承載板 (10)刀離金屬層(12)來傳遞電鑛電流，而無須導電線或臨時導電 ^ 線來傳遞電流。 -如第1H〜II圖所示’在無須利用承載板(1〇)、分離金屬層(12) 傳遞電鑛電流時，可依序去除承載板(1〇)、分離金屬層⑽，以曝 露出介電膠膜(20)、钮刻阻擋層⑽。最終，在絲承載板(1〇)、 刀離金屬層(I2)之後’在被曝露出的介電膠膜(2〇)上形成防焊層 (22) ’如第1J圖所示。 藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本 發月之特徵與精神並非以上賴_揭露的較佳具體實施例來對 200948232 本發明之射細_。城地，其目喊__各種改變 及具相雜的鶴於本發騎欲ψ請之翻_的齡内。 【圖式簡單說明】 第1Α〜1J圖為本發明無導電線構裝載板製作法之示意圖。 【主要元件符號說明】 10承載板 12分離金屬層 14圖案化光阻層 16餘刻阻擋層 18電鍍金屬層 20介電膠膜 22防焊層One or more drilling and hole-filling processes are used to form interlayer vias. As shown in Figure 1G, after filling of the filled ore, it is polished and polished as appropriate, and is used as the gold deposit. It is important to note that the above-mentioned electro-mineral process can use the carrier plate (10) to transfer the ore current from the metal layer (12) without the need for conductive wires or temporary conductive wires to transfer current. - As shown in Figures 1H to II, the carrier plate (1〇) and the separated metal layer (10) can be removed in order to remove the metal current (12) without using the carrier plate (1〇) and the separation metal layer (12). A dielectric film (20) and a button barrier layer (10) are removed. Finally, a solder resist layer (22) is formed on the exposed dielectric film (2 Å) after the wire carrier (1 〇) and the knives are separated from the metal layer (I2) as shown in Fig. 1J. With the above detailed description of the preferred embodiments, it is intended that the features and spirit of the present invention will be described more clearly than the preferred embodiment disclosed herein. The city, its eyes shouted __ various changes and the mixed cranes in the age of the horse. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 1J are schematic views showing a method of fabricating a non-conductive wire-loading plate of the present invention. [Main component symbol description] 10 carrier board 12 separation metal layer 14 patterned photoresist layer 16 residual barrier layer 18 plating metal layer 20 dielectric film 22 solder mask