TWI594349B - Ic carrier of semiconductor package and manufacturing method thereof - Google Patents

Description

Semiconductor package carrier and manufacturing method thereof

The present invention relates to a carrier board and a method of fabricating the same, and more particularly to a semiconductor package carrier board suitable for use in the field of integrated circuit packages of medium and low pin counts and a method of fabricating the same.

With the demand for improved convenience of human beings, the explosion of various electronic products has rapidly expanded, and the integrated circuit packaging technology that plays a pivotal role in the manufacturing process of electronic components has also responded to the high-speed processing and multi-functionality of this demand. We are eager to achieve miniaturization and high density, and we are eager to integrate and integrate small size and light weight.

At present, semiconductor packaging technology is mainly based on lead frame, quad flat no-lead package (QFN) or wafer level chip package (WB CSP). However, if it is to be applied to the functions of small size, light weight, low cost, and fine pitch required for smart phones or wearable devices, the carrier board or lead frame for the above package has faced a technical bottleneck.

For example, the thickness of the leadframe used in the packaging process architecture on the lead frame tends to be large, and because it cannot form finer lines and current spacing, and un-routable, Therefore, the lead frame cannot have electromagnetic wave protection effect on the wafer disposed thereon. In addition, the dielectric material of the existing carrier plate is a core layer of glass fiber (CCL) or a resin film (PP: Prepreg), and a laser via is used as an electrical connection, but the laser is used for the glass fiber. The drilling of the material is slow in production, high in cost, and the aperture is not easily miniaturized. Further, when the dielectric material is made of a material such as BT, FR4, FR5 or ABF of glass fiber and a solder resist material, in the case of thinning, the warpage is very likely to occur, resulting in difficulty in thinning. Moreover, the dielectric material composed of the glass fiber group also increases the difficulty and cost of the fine line processing.

Therefore, various packaging companies have to conduct research to meet the lead frame required for the current low-to-medium package structure market. The present invention is directed to this need, and proposes a brand new carrier board and a method of manufacturing the same to meet this need.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor package carrier and a method of fabricating the same, which have the advantages of being windable, having a fine line pitch and a thin thickness.

Another object of the present invention is to provide a semiconductor package carrier and a method of fabricating the same, which can meet the requirements of light weight and low cost in the field of integrated circuit packages with medium and low pin counts.

To achieve the above object, the present invention provides a semiconductor package carrier comprising a die cast dielectric layer and a patterned conductor layer. The die cast dielectric layer has at least one open slot. The patterned conductor layer is embedded in the die-cast dielectric layer, wherein a portion of the patterned conductor layer is exposed from the open trench, and the upper and lower ends are open ends as conductive pillars, and the remaining patterned conductor layers are open only at one end. The end is used as a wire.

In addition, in order to achieve the above object, the present invention further provides a method for fabricating a semiconductor package carrier, which first forms a patterned conductor layer on a surface of a temporary carrier; subsequently, a temporary carrier is formed on the carrier. Covering the patterned dielectric layer of the patterned conductor layer; subsequently, forming at least one open trench on the die-cast dielectric layer to expose a portion of the patterned conductor layer, wherein the open trench is an open end; and, finally The temporary carrier is removed to reveal one side of the patterned conductor layer as another open end and a portion of the dielectric material layer is exposed. The partially patterned conductor layer is exposed from the open trench, and the upper and lower ends are open-ended as the conductive pillar, and the patterned conductor layer is open-ended only as one end.

10, 50‧‧‧ semiconductor package carrier

12‧‧‧Molded dielectric layer

14‧‧‧ patterned conductor layer

14a‧‧‧conductive column

14b‧‧‧Wire

16‧‧‧Protective layer

18‧‧‧Open slot

20, 60‧‧‧Package structure

22‧‧‧ wafer

23‧‧‧Connecting bumps

24‧‧‧ Sealing layer

25‧‧‧Fixed glue

26‧‧‧ solder balls

32‧‧‧Metal wire

40‧‧‧ Temporary carrier board

42‧‧‧ patterned photoresist layer

422‧‧‧opening

44‧‧‧Conductor materials

52‧‧‧ Conductive layer

1 is a schematic view showing a semiconductor package carrier of a first embodiment of the present invention.

2 is a schematic diagram of an embodiment of the semiconductor package carrier of FIG. 1 applied to a ball grid array package.

3 is a schematic diagram of another embodiment of the semiconductor package carrier of FIG. 1 applied to a ball grid array package.

4A to 4F are schematic diagrams showing the steps of fabricating the semiconductor package carrier shown in FIG. 1.

4G is a schematic diagram of a semiconductor package carrier with a protective layer.

FIG. 5 is a schematic diagram of a semiconductor package carrier according to a second embodiment of the present invention.

6 is a schematic diagram of an embodiment of the semiconductor package carrier of FIG. 5 applied to a planar grid array package.

7 is a schematic diagram of another embodiment of the semiconductor package carrier of FIG. 5 applied to a planar grid array package.

8A to 8F are schematic diagrams showing the steps of fabricating the semiconductor package carrier shown in FIG. 5.

The present invention is not limited by the embodiment, and the embodiment of the present invention is not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that, in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the components in the drawings are merely for ease of understanding and are not intended to limit the actual ratio. In the following embodiments, the same elements will be described with the same element symbols.

The invention is a carrier board which has the characteristics of small volume, thin thickness, low cost, and fine wire spacing, and can be applied to the field of integrated circuit package with medium and low pin count. Please refer to FIG. 1, which is a schematic view of a first embodiment of a semiconductor package carrier of the present invention. As shown in FIG. 1, the semiconductor package carrier 10 mainly includes a die cast dielectric layer 12 and at least one patterned conductor layer 14. The patterned conductor layer 14 is embedded in the die-cast dielectric layer 12, and the patterned conductor layer 14 includes at least one first conductor portion and at least one second conductor portion. The first conductor portion and the second conductor portion are separated by a die-cast dielectric layer 12. The die-cast dielectric layer 12 has at least one opening groove 18 to expose the first conductor portion, so that the first conductor portion has an open upper and lower ends, that is, the first conductor portion has upper and lower ends exposed to the die-casting medium. The open end outside the electrical layer 12 allows the first conductor portion to serve as a conductive post 14a for electrical transmission of the upper and lower layers. The second conductor portion is only open at one end and exposed outside the die-cast dielectric layer 12, and serves as the wire 14b, which can be used as the same layer. Line layout (winding). In addition, part of the wire 14b can also serve as an electrical connection pad for use in connection with electronic components.

Here, it is to be noted that the so-called open type refers to a portion of the patterned conductor layer 14 that is not covered by the die-cast dielectric layer 12. In other words, the partially patterned conductor layer 14 exposed to the die-cast dielectric layer 12, whether or not it is covered by other components, is referred to as open.

The above definition means that the conductive pillars 14a and the wires 14b are formed by the single patterned conductor layer 14 in synchronization with each other, except for the presence or absence of the opening grooves 18, to define the patterned conductor layer 14 as the upper and lower layers. The electrically conductive conductive post 14a is either a wire 14b that is electrically transmitted as a single plane. In addition, the patterned conductor layer 14 is embedded in the die-cast dielectric layer 12, so the height of the die-cast dielectric layer 12 can be very similar to that of the patterned conductor layer 14 because it only needs to be slightly covered to cover the patterned conductor layer 14. The height of one side is only available. As a result, the thickness of the overall carrier can be greatly reduced.

Furthermore, the patterned conductor layer 14 is further formed with a protective layer 16 from the exposed portion of the die-cast dielectric layer 12 to prevent the exposed patterned conductor layer 14 from undergoing an oxidation reaction under a normal environment.

The semiconductor package carrier 10 described above can be applied to a ball grid array (BGA) package. For example, as shown in FIG. 2, the package structure 20 includes a wafer 22, an adhesive layer 24, and at least one solder ball 26. The wafer 22 is electrically connected to the wires 14b of the semiconductor package carrier 10 through the protective layer 16 by at least one bump bump 23 in a Flip-Chip manner. The encapsulant layer 24 simultaneously encloses the wafer 22 and the conductive pillars 14a, the wires 14b and the protective layer 16 exposed on the wafer 22 side outside the die-cast dielectric layer 12 to prevent moisture from entering from the outside. The solder ball 26 is disposed on the open slot 18 of the conductive post 14a that is not enclosed by the sealant layer 24, and is used as an electrical pin to be connected to an electrical contact of a subsequent circuit board (not shown).

Of course, as shown in FIG. 3, the wafer 22 can also be temporarily fixed to the semiconductor package carrier 10 by using the fixing glue 25, and then transmitted through the protective layer 16 by the wire bonding 32 to the semiconductor package carrier 10. The conductive pillars 14a are electrically connected. Since the packaging process is a conventional technique, it will not be described here.

As further shown in FIG. 1, the semiconductor package carrier 10 uses a die-cast dielectric layer 12 as a substrate to carry the patterned conductor layer 14 and thereby insulate and protect the patterned conductor layer 14. The material of the die-cast dielectric layer 12 may be a mold compound for wafer encapsulation, such as, but not limited to, having a phenolic resin (Novolac-Based Resin), an epoxy resin (Epoxy-Based Resin), and a ruthenium resin. Silicone-Based Resin or other suitable mold compound, and the mold compound may also contain a suitable filler such as powdered cerium oxide.

In the present embodiment, the material of the patterned conductor layer 14 is a metal such as, but not limited to, selected from the group consisting of copper, iron, silver, nickel, and combinations thereof.

Please refer to FIG. 4A to FIG. 4F , which are schematic diagrams showing the steps of fabricating the semiconductor package carrier 10 of FIG. 1 . First, as shown in FIG. 4A, a detachable temporary carrier 40 is provided, and a patterned photoresist layer 42 having a plurality of openings 422 is formed on the surface of the temporary carrier 40. The patterned photoresist layer 42 is formed using an exposure development technique. In this embodiment, the material of the temporary carrier 40 may be made of iron, nickel, copper metal or a composite material, and may of course be arbitrarily changed according to different technical requirements.

Subsequently, as shown in FIG. 4B, a conductor material 44 is formed in the openings 422 of the patterned photoresist layer 42. In this embodiment, the material of the conductor material 44 is a metal, such as, but not limited to, selected from the group consisting of copper, iron, silver, nickel, and combinations thereof, and electroplating technology, electroless plating (Electroless Plating) technology may be applied according to different materials. Sputtering Coating technology or Thermal Coating technology.

Next, as shown in FIG. 4C, the patterned photoresist layer 42 is removed to obtain the patterned conductor layer 14 having at least one first conductor portion and at least one second conductor portion as previously described. Subsequently, as shown in FIG. 4D, a molded dielectric layer 12 covering one of the patterned conductor layers 14 is formed by a molding technique. In the present embodiment, the die-cast dielectric layer 12 can be formed using vacuum compression molding techniques or molding techniques. When the molding technique is applied, the material of the die-cast dielectric layer 12 may be a mold compound for wafer encapsulation, such as, but not limited to, having a phenolic resin, an epoxy resin, a ruthenium-based resin, or other suitable mold compound, and The mold compound may also contain a suitable filler such as powdered cerium oxide.

In addition, when the molding technique is applied, the step of forming the die-cast dielectric layer 12 may further include: providing a mold compound in which the mold compound has resin and powdered cerium oxide; heating the mold compound to a liquid state; and injecting into a liquid state The mold compound is in the third opening, and the mold compound is coated with the patterned conductor layer at a high temperature and a high pressure; the mold compound is cured to form the mold compound into the die-cast dielectric layer 12.

Subsequently, as shown in FIG. 4E, the portion of the die-cast dielectric layer 12 on the patterned conductor layer 14 is removed to form a plurality of open trenches 18 to expose portions of the patterned conductor layer 14. The removal step referred to herein may optionally remove the partially molded dielectric layer 12 by means of grinding, plasma or reactive ion etching (RIE).

Finally, as shown in FIG. 4F, the temporary carrier 40 is removed, that is, the semiconductor package carrier 10 is obtained. As shown in the figure, after the temporary carrier 40 is removed, the other side of the patterned conductor layer 14 will be exposed for subsequent electrical connection purposes. At this time, the upper and lower ends of the partially patterned conductor layer 14 are partially patterned. The die-cast dielectric layer 12 is exposed as the conductive pillar 14a, and the other portion of the patterned conductor layer 14 is exposed at one end only to the die-cast dielectric layer 12 as the wire 14b.

In addition, as shown in FIG. 4G, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the patterned conductor layer 14 exposed outside the die-cast dielectric layer 12. This protective layer 16 may be an organic solder resist film (OSP), a Ni/Pd/Au plating film, or a Ni/Ag plating film.

Please refer to FIG. 5, which is a schematic diagram of a semiconductor package carrier 50 according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that a conductive layer 52 is further filled in the open trench 18 of the die-cast dielectric layer 12 of the semiconductor package carrier 50 to add the height and mode of the conductive pillar 14a to the conductive layer 52. The height of the cast dielectric layer 12 is approximately the same.

At this time, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the conductive pillar 14a, the wire 14b or the conductive layer 52 exposed outside the die-cast dielectric layer 12.

Please refer to FIG. 6 , which is a schematic diagram of an embodiment of the semiconductor package carrier 50 shown in FIG. 5 applied to a planar grid array package. As shown in FIG. 6, the package structure 60 includes a wafer 22 and an adhesive layer 24. The wafer 22 is covered by the connecting bump 23 The bonding method is electrically connected to the exposed wires 14b of the semiconductor package carrier 50 through the protective layer 16. The encapsulant layer 24 encloses the wafer 22 with the wires 14b on the wafer side that are exposed from the molded dielectric layer 12 to prevent moisture from entering from the outside. Since the packaging process is a conventional technique, it will not be described here. Of course, as shown in FIG. 7 , the wafer 22 can also be temporarily fixed to the semiconductor package carrier 50 by the fixing glue 25 , and then the conductive layer 16 can be used to pass through the protective layer 16 and the conductive pillar on the semiconductor package carrier 50 by using the metal wire 32 . 14a electrical connection.

Please refer to FIG. 8A to FIG. 8F , which are schematic diagrams showing the steps of fabricating the semiconductor package carrier 50 of the second embodiment of the present invention. First, as shown in FIG. 8A, a detachable temporary carrier 40 is provided, and a patterned photoresist layer 42 having a plurality of openings 422 is formed on the surface of the temporary carrier 40.

Subsequently, as shown in FIG. 8B, a conductor layer is formed on the opening 422 of the patterned photoresist layer 42, and the patterned photoresist layer 42 is removed to obtain a patterned conductor layer 14. Subsequently, as shown in FIG. 8C, a die-cast dielectric layer 12 covering the patterned conductor layer 14 is formed.

Subsequently, as shown in FIG. 8D, at least one open trench 18 is formed on the die-cast dielectric layer 12 by means of grinding, plasma or reactive ion etching (RIE) to reveal a partial pattern. The surface of the conductor layer 14 is formed.

Continuing, as shown in FIG. 8E, a conductive layer 52 is filled in the opening groove 18 so that the height of the portion of the patterned conductor layer 14 exposed from the opening groove 18 is increased by the height of the conductive layer 52. The height of the dielectric layer 12 is approximately the same.

Finally, as shown in FIG. 8F, the temporary carrier 40 is removed to form the semiconductor package carrier 50. As shown in the figure, after the temporary carrier 40 is removed, the other side of the patterned conductor layer 14 will be exposed for subsequent electrical connection purposes. At this time, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the patterned conductor layer 14 and the conductive layer 52 exposed outside the die-cast dielectric layer 12.

The details of the process steps in the above-described FIGS. 8A to 8F, such as the material of the temporary carrier, the formation method of the patterned photoresist layer, and the like, can follow the teachings of FIGS. 4A to 4F, and thus will not be described again.

In summary, the present invention provides a novel semiconductor package carrier and a method of fabricating the same, wherein the conductive pillars and wires are simultaneously formed by a patterned conductor layer and are enclosed by a die-cast dielectric layer having a height approximately The height of the die-cast dielectric layer is similar to the height of the conductive pillar or wire, so the overall thickness of the carrier can be reduced, and since the patterning process of the conductive layer is already a mature technology, the line pitch can be greatly reduced, and A wraparound wire layout can be formed to provide electromagnetic protection of the wafer.

The invention complies with the requirements of the invention patent, and proposes a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Any person who is familiar with the skill of the case, equivalent modifications or changes made in accordance with the spirit of the invention shall be included in the scope of the following patent application.

10‧‧‧Semiconductor package carrier

12‧‧‧Molded dielectric layer

14‧‧‧ patterned conductor layer

14a‧‧‧conductive column

14b‧‧‧Wire

16‧‧‧Protective layer

18‧‧‧Open slot

Claims (15)

A method of fabricating a semiconductor package carrier includes: forming a patterned conductor layer on a surface of a temporary carrier; forming a die-cast dielectric layer on the surface of the temporary carrier, the die-cast dielectric a layer covering the patterned conductor layer; forming at least one open trench on the die-cast dielectric layer, the open trench revealing a portion of the patterned conductive layer; and removing the temporary carrier to expose the patterned conductor a molded dielectric layer on one side and a portion of the layer, wherein a portion of the patterned conductor layer is exposed from the open trench, and the upper and lower ends are open ends as a conductive pillar, and only one end of the patterned conductor layer The open end is used as a wire, and the conductive pillars and wires are simultaneously formed by the patterned conductor layer. The method of fabricating a semiconductor package carrier according to claim 1, wherein the temporary carrier is made of iron, nickel, copper metal or a composite material with a dielectric material. The method of fabricating a semiconductor package carrier according to claim 1, wherein the step of forming the patterned conductor layer comprises: forming a patterned photoresist layer on the surface of the temporary carrier, the patterned photoresist layer Having a plurality of openings; forming a conductor material in the openings; and removing the patterned photoresist layer to form the patterned conductor layer. The method of fabricating a semiconductor package carrier according to claim 3, wherein the conductor material is formed by a plating technique, an electroless plating technique, a sputtering technique, or an evaporation technique. The method of fabricating a semiconductor package carrier according to claim 1, wherein the die-cast dielectric layer is formed by a vacuum compression molding technique or a molding technique. The method of manufacturing a semiconductor package carrier according to claim 1, wherein after forming the open trench, further comprising filling a conductive layer in the open trench. The method for fabricating a semiconductor package carrier according to claim 6, further comprising: forming a protective layer on the surface of the conductive layer and the surface of the patterned conductor layer exposed outside the molded dielectric layer. The method for fabricating a semiconductor package carrier according to claim 1, further comprising: forming a protective layer on the surface of the patterned conductor layer exposed outside the die-cast dielectric layer. A semiconductor package carrier comprising: a die cast dielectric layer having at least one open trench; and at least one patterned conductor layer embedded in the die cast dielectric layer, wherein a portion of the patterned conductor layer The open slot is exposed, and the upper and lower ends are open ends as a conductive pillar, and only one end of the patterned conductor layer is an open end as a wire, and the conductive pillar and the wire are connected by the die The cast dielectric layer is isolated. The semiconductor package carrier of claim 9, wherein the die-cast dielectric layer is a die-cast dielectric layer formed by vacuum compression molding or molding. The semiconductor package carrier of claim 9, further comprising a conductive layer filled in the open trench. The semiconductor package carrier of claim 11, wherein a surface of the conductive layer and a surface of the patterned conductor layer exposed outside the die dielectric layer are formed with a protective layer. The semiconductor package carrier of claim 9, wherein a protective layer is formed on a surface of the patterned conductor layer exposed outside the die dielectric layer. A package structure formed using the semiconductor package carrier of claim 9, comprising: a wafer disposed on a surface of the carrier; and a glue layer enclosing the wafer. The package structure of claim 14, further comprising at least one solder ball disposed in the open slot and electrically connected to the conductive post.