JP3546961B2 - Wiring board for mounting semiconductor device, method of manufacturing the same, and semiconductor package - Google Patents

Description

【００６８】
式中、Ｒは、それぞれ独立に、水素原子またはメチル、エチル、ｎ−プロピル若しくはイソプロピル等の低級アルキル基、ｎは０〜２０の整数を示す。
【００６９】
以上のような樹脂材料を絶縁層に用いることで膜強度や破断伸び率に優れ、特に耐クラック性に優れた配線基板を得ることができ、エリアアレイで１００μｍピッチ以下の狭ピッチかつ多ピンの半導体チップを搭載可能である。
【００７０】
本発明者らは、これらの樹脂からなる絶縁層を有する配線基板について、プレッシャークッカー試験（温度１２１℃、湿度１００％）を行ったところ、１９２時間経過後もまったく樹脂層間剥離は観測されなかった。
【００７１】
また、下記の４種の樹脂をそれぞれ絶縁層６とする図９（ｃ）に示す半導体パッケージについて温度サイクル試験（−６５℃で３０分、１５０℃で３０分で１サイクルとする。）を行ったところ、１０００サイクル後においても断線やクラックは生じなかった。
【００７２】
樹脂ａ；膜強度７８ＭＰａ、破断伸び率８．５％、ガラス転移温度１７５℃、熱膨張率５５ｐｐｍ、弾性率２．５ＧＰａ、
樹脂ｂ；膜強度１８０ＭＰａ、破断伸び率３０％、ガラス転移温度３８５℃、熱膨張率２８ｐｐｍ、弾性率６．０ＧＰａ、
樹脂ｃ；ガラス転移温度１８０℃、熱膨張率１１ｐｐｍ、弾性率１１ＧＰａ、
樹脂ｄ；ガラス転移温度２００℃、熱膨張率１８ｐｐｍ、弾性率１２ＧＰａ。
【００７３】
本発明の配線基板は、配線が設けられた絶縁層の上面にさらに絶縁層とこの絶縁層の上面に形成された配線とが順次交互に一組以上形成された多層配線構造を有することができる。図６に、この一実施形態として、図１に示す構造にさらに絶縁層と配線を一組積層した多層配線構造を有する形態を示す。絶縁層６上には配線８を覆うように絶縁層１２が設けられ、この絶縁層１２上には配線１３が設けられ、この配線１３と配線８とを導通するように絶縁層１２内にヴィアが設けられている。このような多層配線構造において、絶縁層の少なくとも一層が絶縁材料Ａ又はＢからなることが好ましく、さらに他の絶縁層が前記のフルオレン系樹脂からなることが好ましい。
【００７４】
本発明の配線基板は、図７に示す実施形態のように、下面側に設けられた複数の電極の一部の電極５の上面に誘電体層９３を設け、この誘電体層９３上にヴィア導電体７を設けて、電極５と誘電体層９３とヴィア導電体７からなるコンデンサを有することもできる。このようなコンデンサを形成することにより、伝送ノイズを低減することができ、高速化に最適な配線基板を得ることができる。誘電体層の材料としては、酸化チタン（ＴｉＯ_２）、酸化タンタル（Ｔａ_２Ｏ_５）、酸化アルミニウム（Ａｌ_２Ｏ_３）、酸化ケイ素（ＳｉＯ_２）、酸化ニオブ（Ｎｂ_２Ｏ_５）、ＢＳＴ（Ｂａ_ｘＳｒ_１−ｘＴｉＯ_３）、ＰＺＴ（ＰｂＺｒ_ｘＴｉ_１−ｘＯ_３）、ＰＬＺＴ（Ｐｂ_１−ｙＬａ_ｙＺｒ_ｘＴｉ_１−ｘＯ_３）、ＳｒＢｉ_２Ｔａ_２Ｏ_９などのペロブスカイト系材料を挙げることができる。
【００７５】
本発明の配線基板は、図８（ａ）、（ｂ）に示すように、二枚の支持基板１が貼り合わされた積層板の両面にそれぞれ上述の配線基板構造が形成された形態とすることもできる。この形態は、半導体チップの搭載前あるいは搭載後に二枚の支持基板を分離して二つの配線基板あるいは半導体パッケージとし、それぞれ前述のように電極５が露出するように支持基板１を除去して、他のボード等に実装可能な形態にすることができる。
【００７６】
［半導体パッケージ］
本発明の半導体パッケージは、本発明の配線基板の上面に半導体チップを搭載して形成することができる。半導体チップのパッド等の電気的接続部と配線基板の配線とは、種々の方式で電気的に導通することが可能であり、例えば、フリップチップ方式、ワイヤーボンディング方式、テープボンディング方式が挙げられる。
【００７７】
図９に、フリップチップ方式による一実施形態を示す。本発明の半導体パッケージは、図９（ａ）に示すように、配線基板の下面全面に基板１を備えた形態とすることができる。この場合、他のボード等に実装する際、電極５が露出するように基板１を除去する。電極５が露出した形態としては、図９（ｂ）に示すように絶縁層６下面に、フレーム状あるいは格子状やメッシュ状に基板１を加工して残し、半導体パッケージの補強のための支持体１６とすることができる。このような支持体を形成しなくても十分な強度が確保できる場合は、基板１全部を除去して、図９（ｃ）に示すような形態としてもよい。図９（ａ）〜（ｃ）に示すように、モールド樹脂により半導体チップを封入した場合は、モールド樹脂が支持体としても機能するため、支持体１６を設けなくても十分な強度を確保することが可能である。
【００７８】
また、本発明の半導体パッケージは、図９に示す実施形態のように、半導体チップ１８に設けられたパッド１９と、本発明の配線基板に相当する配線構造体９の配線８とは、例えば金属バンプ２０を介して電気的に接続することができる。その際、半導体チップ１８と配線構造体９との間には必要によりアンダーフィル樹脂２１を充填することができる。また、配線構造体９上の半導体チップはモールド樹脂２２を用いてトランスファーモールド法により封入することができる。あるいは、熱放射を高めるため、図９（ｄ）に示すように、半導体チップ１８上にヒートシンク３３を設けた後、他の封止法により封入することもできる。
【００７９】
また、本発明の半導体パッケージは、図１０に示すように、両面に半導体チップが搭載された形態とすることができる。このような形態は、図８を用いて説明した形態の配線基板の両面にそれぞれ半導体チップを搭載することにより形成することができる。この半導体パッケージは、他のボード等への実装の際、二枚の基板が貼り合わされた積層基板を二つに分離して二つの半導体パッケージとし、それぞれ前述のように配線構造体９の電極５が露出するように基板１を除去して、他のボード等に実装可能な形態にすることができる。
【００８０】
［配線基板および半導体パッケージの製造方法］
図１１に、本発明の製造方法の一実施形態の断面工程図を示す。
【００８１】
まず、図１１（ａ）に示すように、ステンレス鋼、Ｃｕ、Ｃｕ合金、Ａｌ、Ｎｉ等の金属板からなる基板１上に、電極パターン形成用のレジスト層を形成し、このレジスト層をパターニングして所定の電極パターンに相応した開口部３を有するレジストマスク２を形成する。
【００８２】
次に、図１１（ｂ）に示すように、基板１から通電を行い、電解めっき法により開口部３内の基板１上にメッキ層４を形成する。次いで、図１１（ｃ）に示すように、レジストマスク２を除去し、基板１上にレジストマスク２の開口部パターンに相応した所定の電極パターンを持つメッキ層４を残して、これを電極５とする。このように、電極５の形成には、信頼性の点から、緻密な金属を析出させることができる電解めっき法を用いることが望ましいが、無電解めっき法により開口部３にメッキ層４を析出させて電極５を形成することもできる。
【００８３】
次に、図１１（ｄ）に示すように、電極５が形成された基板１上に絶縁層６を形成し、この絶縁膜６にフォトリソグラフィ法あるいはレーザ加工法等により電極５に達するヴィアホール７ａを形成する。
【００８４】
絶縁層６の材料としては、エポキシ系樹脂、前記のフルオレン系樹脂、ポリイミド系樹脂、ポリベンゾオキサゾール、ポリベンゾシクロブテン等の種々の絶縁性樹脂を適用することができる。この絶縁層６は、実装信頼性を向上させるため、例えば図５に示すように、複数の樹脂層から構成することもできる。
【００８５】
次に、図１１（ｅ）に示すように、スパッタリング法、無電解めっき法、電解めっき法等によりヴィアホール７ａを埋め込むように絶縁層６上に導電体層を形成し、この導電体層をフォトリソグラフィ法によりパターニングして配線層８を形成する。または、ヴィアホール７ａを埋め込むように導電体層を形成した後、絶縁層６上面の不要な導電体層を除去してヴィアホール７ａのみに導電体を残してヴィア７を形成し、続いてこのヴィアに接続する同種あるいは異種の導電体層を形成し、これをパターニングして配線層８を形成することもできる。
【００８６】
以上のようにして本実施形態の配線基板を形成できるが、この配線基板を他のボード等に実装可能な形態とするには、例えば前述した図１及び図４に示すように、所定の領域の基板１を選択エッチングして、外部と電気的に接続するための電極５を露出させるとともに、絶縁層６の外周にフレーム状に残した基板を支持体１６とする。前述したように支持体１６は、フレーム状の他、格子状やメッシュ状に形成することも可能である。
【００８７】
その後、必要であれば、図３に示すように、電極５に半田ボールを搭載するために電極５の周囲にソルダーレジスト１７を形成してもよく、さらに半田ボール３１を搭載してもよい。
【００８８】
また、配線層８を形成した後、図１２に示すように、配線層８を覆うように絶縁層６上にカバーコート１０を形成し、このカバーコート１０の所定の位置に半導体チップと導通するためのパッド部１１として開口を設けることもできる。このパット部１１はその開口に導体を埋め込んで電極パッドとすることができる。
【００８９】
また、配線層８を形成した後、図６に示すように、配線層８を覆うように絶縁層６上に絶縁層１２を形成し、前述と同様にして、絶縁層１２中にヴィア及び絶縁層１２上に配線層１３を形成して多層配線構造を設けることができる。この工程を繰り返すことにより任意の層数に多層化することができる。
【００９０】
このような本実施形態の製造方法によれば、電極５の狭ピッチ化かつ高精度化が極めて容易である。また、電極５は絶縁膜６に埋め込まれた構造となっているので、電極５への応力やひずみを緩和でき、応力集中が少なくなるため、外部のボードや装置との実装信頼性にも優れた配線基板を製造することができる。本実施形態の配線基板に半導体チップを搭載して半導体パッケージとすれば、この半導体パッケージの、外部のボードや装置との実装信頼性を高めることができる。
【００９１】
さらに、電極５の形成に用いた基板１を、電極５の露出のための除去工程に際して配線基板の支持体１６として残すことができるため、別途に支持体を設ける工程が不要であり、簡便な方法で、取り扱い性に優れ、チップの搭載信頼性および他のボード等への実装信頼性に優れた配線基板を製造することができる。
【００９２】
図８に示すような積層板の両側に配線構造が形成された配線基板は、例えば次のようにして製造することができる。
【００９３】
まず、図１３（ａ）に示すように、第１の基板と第２の基板が貼り合わされた積層板２５を用意する。例えば、一方の基板１の周囲（接着領域２４）にエポキシ系またはポリイミド系の耐熱性の接着性樹脂を配置し、その面に他方の基板を貼り合わせ接着固定する。
【００９４】
次に、前述の方法と同様にして積層板の両面にそれぞれレジスト層を形成し、これらをパターニングして所定の第１及び第２の電極パターンに相応する開口パターンを形成する。次に、基板１から通電を行い、電解メッキ法によりレジスト層の開口内にメッキ層を形成し、続いてレジスト層を除去して積層板２５の両面にそれぞれ第１及び第２の電極５を形成する。次に、前述の方法と同様にして、積層板２５の両面にそれぞれ絶縁層６を形成し、次いでこれらの絶縁層にそれぞれヴィアホールを形成した後、これらのヴィアホールを埋め込むように導電膜を形成し、これらをパターニングして配線８を形成する（図１３（ｂ））。その後、図１３（ｂ）に示す点線の位置（接着領域２４の内側）で配線基板２６を切断することにより、図１３（ｃ）に示すように、貼り合わせた第１及び第２の基板１を分離して、二つの配線基板を得ることができる。あるいは、配線基板の少なくとも一方の面に半導体チップを搭載して、例えば図１０に示すように両面に半導体チップを搭載して半導体パッケージを形成した後、貼り合わせた第１及び第２の基板１を分離して、二つの半導体パッケージを得ることもできる。
【００９５】
このような製造方法によれば、工程を簡略化できるので、生産性が向上し、低コスト化をはかることができる。
【００９６】
［積層型電極を有する配線基板の製造方法］
図１４に、積層型電極を有する配線基板の製造方法の一実施形態を示す。
【００９７】
本実施形態の製造方法では、基板１としてステンレス鋼板を用い、配線基板の下面側からＡｕメッキ層、Ｎｉメッキ層、Ｃｕメッキ層をこの順で積層した３層構造の電極を形成する。
【００９８】
まず、図１４（ａ）に示すように、ステンレス鋼（例えば日新製鋼製；ＳＵＳ３０４）からなる基板１上に、メッキ膜形成用のレジスト層を形成し、このレジスト層をパターニングして所定の電極パターンに相応した開口部３を有するレジストマスク２を形成する。
【００９９】
ここで、基板１の好ましい板厚は０．１ｍｍ〜１．０ｍｍであり、より好ましくは０．２ｍｍ〜０．８ｍｍである。その理由は、板厚が薄すぎると、配線基板の製造工程において反りが発生しやすく、精度が低下して微細な配線形成が困難となってしまうためであり、また、板厚が厚すぎると、重量が大きくなるために取り扱い性が低下してしまうからである。
【０１００】
次に、図１４（ｂ）に示すように、電解めっき法あるいは無電解めっき法により、開口部３内の基板１上に、Ａｕメッキ層４ａ、Ｎｉメッキ層４ｂ、Ｃｕメッキ層４ｃをこの順で形成する。それぞれのメッキ層の厚さは、Ａｕメッキ層が０．３μｍ〜３μｍ、Ｎｉメッキ層が１μｍ〜７μｍ、Ｃｕメッキ層が５μｍ以上とすることが好ましい。
【０１０１】
次に、図１４（ｃ）に示すように、基板１上からレジストマスク２を除去し、基板１上にレジストマスク２の開口部パターンに相応した所定の電極パターンを持つメッキ層を残して、Ａｕ／Ｎｉ／Ｃｕの３層構造の電極５とする。
【０１０２】
次に、図１４（ｄ）に示すように、電極５が形成された基板１上に絶縁層６を形成し、この絶縁層６に、電極５に達するヴィアホール７ａを形成する。
【０１０３】
次いで、図１４（ｅ）に示すように、ヴィアホール７ａを埋め込むように絶縁層６上に導電体層を形成し、この導電体層をパターニングして配線層８を形成する。
【０１０４】
最後に、図１４（ｆ）に示すように、基板１の所定の領域を下面側からエッチングにより除去して電極５を露出させると同時に支持体１６を形成する。
【０１０５】
Ａｕ／Ｎｉ／Ｃｕの３層構造の電極５を有する本実施形態においては、ステンレス鋼からなる基板１とＡｕメッキ層との界面で十分な密着性を有するため剥がれが起きにくい。また、Ａｕメッキ層は、絶縁層６の形成などの製造時の熱履歴によっては、基板１やＮｉメッキ層に対して拡散しにくい。このため、Ａｕメッキ層は、基板１のエッチング時におけるバリアメタルとして十分な機能を果たすことができ、エッチング条件を幅広く選択することができる。よって、製造上の歩留まり、生産性、取り扱い性を向上させることができる。さらに、電極５に半田ボールを搭載して外部のボードや装置と電気的に接続する際に、Ｎｉメッキ層が半田の拡散防止層として機能するので、実装信頼性を高めることができる。
【０１０６】
他の積層型電極を有する配線基板の製造方法としては、基板１としてＣｕ板あるいはＣｕ合金板（例えば神戸製鋼製；ＫＦＣ）を用い、配線基板の下面側から、Ｎｉメッキ層、Ａｕメッキ層、Ｎｉメッキ層、Ｃｕめっき層をこの順で積層した４層構造の電極を形成することができる。この構造は、基板１と電極構造が異なる以外は上記の方法と同様にして形成することができる。
【０１０７】
基板１の厚さは上記の方法と同様に０．１ｍｍ〜１．０ｍｍが好ましく、基板１側からＮｉメッキ層の厚さは１μｍ以上、Ａｕメッキ層の厚さは０．３μｍ〜３μｍ、Ｎｉメッキ層の厚さは１〜７μｍ、Ｃｕメッキ層の厚さは５μｍ以上にすることが好ましい。
【０１０８】
ＣｕあるいはＣｕ合金からなる基板１（以下適宜「Ｃｕ基板」という）は、塩化銅あるいは塩化鉄系エッチング液で容易にエッチングすることができため、生産性がさらに向上する利点がある。
【０１０９】
また、本発明者等が鋭意検討したところによれば、Ｃｕ基板は、ステンレス鋼からなる基板とは特性が異なるために、このＣｕ基板上に直接Ａｕめっき層を形成すると、配線基板の製造工程における熱履歴により、Ｃｕ基板とＡｕめっき層との間で金属拡散が発生し、エッチング時のバリアメタルとして機能しないことがわかった。そこで、鋭意検討を重ねた結果、この金属拡散の問題は、Ｃｕ基板上にＮｉメッキ層５２を介して他のメッキ層を形成することで解決することを見いだした。さらに、中間層のＮｉ層は半田の拡散防止層としても機能するため、Ｎｉ／Ａｕ／Ｎｉ／Ｃｕめっき多層構造の電極５は、配線基板の電極として最適であることがわかった。
【０１１０】
その他の実施形態として、Ｃｕ／Ａｇ／Ｃｕ電極についても上記の方法と同様にして形成することができ、その際の基板としては特に制限されないが例えばＣｕ基板やステンレス鋼板を用いることができる。
【０１１１】
［凹型電極構造を有する配線基板の製造方法］
本発明の配線基板における電極は、図２（ａ）に示すように、絶縁層６の下面に設けられた凹部４１の底面から露出する構造にすることもできる。この構造は、例えば図１５に示すように、電極５を配線基板（絶縁層６）の下面側から所定の厚さ分だけエッチング除去して凹部４１を形成することにより得ることができる。図１５に示すように複数の異種材料層からなる多層構造をもつ電極の場合は、材料によるエッチングレートの違いにより容易に所定の厚さ分だけ層単位でエッチング除去することができる。例えば前記のＮｉ／Ａｕ／Ｎｉ／Ｃｕメッキ多層構造の電極５においては、Ｎｉメッキ層のみをエッチング除去して、絶縁層下面（配線基板下面）に対して窪んだ構造を形成することができる。このような構造にすることにより、電極５が狭ピッチな場合でも半田ボールを容易に搭載することができるようになる。
【０１１２】
［凸型電極構造を有する配線基板の製造方法］
本発明の配線基板における電極は、図２（ｂ）に示すように、絶縁層６の下面から突出した構造とすることもできる。この構造は、例えば以下のようにして形成することができる。
【０１１３】
まず、図１６（ａ）に示すように、金属板からなる基板１上に、電極パターン形成用のレジスト層を形成し、このレジスト層をパターニングして所定の電極パターンに相応した開口部３を有するレジストマスク２を形成する。
【０１１４】
次に、図１６（ｂ）に示すように、レジストマスク２をエッチングマスクとして基板１の上面をエッチングして、レジストマスク２の開口部３に相応した凹部５１を基板１上面に形成する。
【０１１５】
次に、図１６（ｃ）に示すように、露出した基板１上にめっき法により金属を析出させて凹部５１及び開口部３内にメッキ層４を形成する。次いで、図１６（ｄ）に示すように、レジストマスク２を除去し、基板１上にレジストマスク２の開口部パターンに相応した所定の電極パターンを持つメッキ層４を残して、これを電極５とする。
【０１１６】
次に、図１６（ｅ）に示すように、電極５が形成された基板１上に絶縁層６を形成し、この絶縁層６にフォトリソグラフィ法あるいはレーザ加工法等により電極５に達するヴィアホール７ａを形成する。
【０１１７】
次に、図１６（ｆ）に示すように、スパッタリング法、無電解めっき法、電解めっき法等によりヴィアホール７ａを埋め込むように絶縁層６上に導電体層を形成し、この導電体層をフォトリソグラフィ法によりパターニングして配線層８を形成する。
【０１１８】
その後、図２（ｂ）に示すように、所定の領域の基板１を下面側から選択エッチングして、外部と電気的に接続するための電極５を露出させるとともに、例えば絶縁層６の外周にフレーム状に基板を残して支持体１６とする。
【０１１９】
以上のようにして容易に凸型電極を形成することができる。なお、図１６（ｂ）に示す工程においてエッチング量を調整することによって、絶縁層下面からの電極の突出サイズを調整することができる。
【０１２０】
［コンデンサを有する配線基板の製造方法］
本発明の配線基板には、前述したように、例えば図７に示すようなコンデンサを有する構成とすることもできる。コンデンサを有する構成は、例えば以下のようにして形成することができる。
【０１２１】
まず、図１７（ａ）に示すように、前述のメッキ法を用いた方法にしたがって基板９１上に電極９２を形成する。
【０１２２】
次に、図１７（ｂ）に示すように、複数の電極のうち一部の電極上に、例えばメタルマスクを用いたスパッタリング法により誘電体層９３を形成する。
【０１２３】
次に、図１７（ｃ）に示すように、電極９２及び誘電体層９３が形成された基板９１上に絶縁層９４を形成し、この絶縁層９４にフォトリソグラフィ法あるいはレーザ加工法によりヴィアホール９５ａを形成する。
【０１２４】
次に、図１７（ｄ）に示すように、絶縁膜９４上にヴィアホール９５ａを埋め込むように導電体層を形成し、この導電体層をパターニングして配線層９６を形成する。
【０１２５】
その後、図１７（ｅ）に示すように、所定の領域の基板９１を下面側から選択エッチングして、外部と電気的に接続するための電極９２を露出させるとともに、支持体９７を形成する。
【０１２６】
誘電体層９３と、誘電体層９３下の電極９２と、誘電体層９３上のヴィア導電体層９５とがコンデンサとしての機能を有するため、伝送ノイズを低減することができる。これにより、高速化に最適な配線基板を得ることができる。
【０１２７】
【発明の効果】
以上説明したように本発明によれば、半導体デバイスの端子の増加や狭ピッチ化に対応した配線基板の高密度化、微細配線化を実現でき、かつ、システムの小型化、高密度化に対応した配線基板の外部電極の狭ピッチ化を実現することができる。さらに、実装信頼性に優れた配線基板を提供することができ、高性能かつ信頼性に優れた半導体パッケージを実現することができる。
【図面の簡単な説明】
【図１】本発明の半導体装置搭載用配線基板の一実施形態の概略断面図である。
【図２】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図３】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図４】本発明の半導体装置搭載用配線基板の一実施形態の概略底面（下面）図である。
【図５】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図６】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図７】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図８】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図９】本発明の半導体パッケージの実施形態の概略断面図である。
【図１０】本発明の半導体パッケージの他の実施形態の概略断面図である。
【図１１】本発明の半導体装置搭載用配線基板の製造方法の一実施形態を示す断面工程図である。
【図１２】本発明の半導体装置搭載用配線基板の他の実施形態の概略断面図である。
【図１３】本発明の半導体装置搭載用配線基板の製造方法の他の実施形態を示す断面工程図である。
【図１４】本発明の半導体装置搭載用配線基板の製造方法の他の実施形態を示す断面工程図である。
【図１５】本発明の半導体装置搭載用配線基板の製造方法の他の実施形態を示す断面工程図である。
【図１６】本発明の半導体装置搭載用配線基板の製造方法の他の実施形態を示す断面工程図である。
【図１７】本発明の半導体装置搭載用配線基板の製造方法の他の実施形態を示す断面工程図である。
【図１８】従来の半導体装置搭載用配線基板の製造方法を示す断面工程図である。
【符号の説明】
１ 基板
２ レジストマスク
３ 開口部
４ めっき層
５ 電極
６ 絶縁層
７ ヴィア
７ａ ヴィアホール
８ 配線層
９ 配線構造体
１０ カバーコート
１１ パッド部
１２ 絶縁層
１３ 配線層
１６ 支持体
１７ ソルダーレジスト
１８ 半導体チップ
１９ パッド
２０ 金属バンプ
２１ アンダーフィル樹脂
２２ モールド樹脂
２４ 接着領域
２５ 積層板
２６ 配線基板
３１ 半田ボール
３３ ヒートシンク
４１ 凹部
５１ 凹部
９１ 基板
９２ 電極
９３ 誘電体層
９４ 絶縁層
９５ ヴィア導電体
９６ 配線
９７ 支持体
１０１ 金属板
１０２ 絶縁層
１０３ ヴィアホール
１０４ 配線パターン
１０５ フリップチップパッド部
１０６ 絶縁層
１０７ 基板補強体
１０８ 外部電極端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is capable of mounting various semiconductor devices at high density, and is preferably used for realizing a high-speed and high-density module or system, a wiring board and a manufacturing method thereof, and a semiconductor device mounted on the wiring board. The present invention relates to a manufactured semiconductor package.
[0002]
[Prior art]
In recent years, with the increase in the number of terminals and the narrower pitch due to the higher speed, multi-functionality, and higher integration of semiconductor devices, the density and fine wiring of mounting wiring boards on which semiconductor devices are mounted have been increased more than ever. Is required.
[0003]
As a mounting wiring board often used at present, there is a build-up multilayer board which is a kind of a multilayer wiring board.
[0004]
This build-up multilayer board is manufactured as follows using a glass epoxy printed board as a base core board. First, an epoxy resin layer is formed on both sides of the glass epoxy printed circuit board. Next, via holes are formed in these epoxy resin layers by a photolithography method or a laser method. Thereafter, a wiring layer and a via conductor are formed on the epoxy resin layer by a combination of electroless or electrolytic Cu plating and photolithography. By repeating the above steps sequentially, a build-up laminated structure is formed.
[0005]
However, in this build-up multilayer board, since a glass epoxy printed board with low heat resistance is used for the base core board, shrinkage, warpage, There is a problem that a problem such as swelling occurs. These problems significantly reduce the accuracy in the exposure step, and it is difficult to form a high-density and fine wiring pattern on a glass epoxy printed circuit board.
[0006]
In addition, when a semiconductor device is mounted on such a build-up multilayer substrate by a flip chip method, poor connection or distortion between the semiconductor device and the build-up multilayer substrate may occur due to heat treatment during chip mounting or solder reflow. This may occur, and thus may reduce the long-term connection reliability.
[0007]
In order to solve the above problem, there has been proposed a mounting wiring board in which a build-up laminated structure is formed on a base board made of a metal plate (Japanese Patent Application Laid-Open No. 2000-3980).
[0008]
FIG. 18 shows a manufacturing process diagram of the mounting wiring board. First, as shown in FIG. 18A, an insulating layer 102 is formed on a metal plate 101, and a via hole 103 is formed in the insulating layer 102. Next, as shown in FIG. 18B, a wiring pattern 104 is formed on the insulating layer 102 including the via hole 103. Next, as shown in FIG. 18C, an insulating layer 106 is formed on the wiring pattern 104, and a flip chip pad portion 105 reaching the wiring pattern 104 is formed on the insulating layer 106. Finally, as shown in FIG. 18D, the metal plate 101 is etched from below to form the substrate reinforcing member 107 and the external electrode terminals 108.
[0009]
[Problems to be solved by the invention]
In recent years, for mounting wiring boards, in addition to the above-mentioned high density and fine wiring, in order to realize system miniaturization and high density, to electrically connect with external boards and devices It is strongly required that the pitch of the external electrodes be reduced.
[0010]
However, in the conventional mounting wiring board shown in FIG. 18, since the external electrode terminals 108 are formed by etching the metal plate 101, the external electrode terminals 108 having a narrow pitch are formed due to the limit of the side etching amount control at the time of etching. It is very difficult to do.
[0011]
Further, when this mounting wiring board is mounted on an external board or device, stress is structurally concentrated on the interface between the external electrode terminal 108 and the insulating layer 102, and an open defect is likely to occur. I can not get the nature.
[0012]
The present invention has been made in view of the above circumstances, and can realize high-density and fine wiring in response to an increase in the number of terminals and a narrow pitch of a semiconductor device. It is an object of the present invention to provide a wiring board for mounting a semiconductor device, a method of manufacturing the same, and a semiconductor package which can realize a narrower pitch of the external electrodes corresponding to the demand for semiconductor devices and have excellent mounting reliability.
[0013]
[Means for Solving the Problems]
The present inventionIt is a single layer with a concave part on the lower surface side and made of resinAn insulating layer, a wiring provided on an upper surface of the insulating layer, and the insulating layerInsideAn electrode provided on the lower surface side ofThe entire lower surface of the electrode forms the bottom surface of the recess andAn electrode provided so as not to be in contact with the insulating layer; a via provided in the insulating layer so as to be on the upper surface of the electrode and electrically connecting the electrode to the wiring; and a via provided on the surface of the insulating layer. The present invention relates to a wiring board for mounting a semiconductor device, comprising:
[0017]
The present invention also relates to the above-described wiring board for mounting a semiconductor device, which has a laminated structure in which a Cu layer is disposed at an upper end of the electrode and at least one different conductive layer is disposed at a lower end thereof.
[0018]
Further, the present invention provides the above-described semiconductor having a multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. The present invention relates to a wiring board for mounting a device.
[0019]
The present invention also provides the insulating layerInsideAn electrode provided on the lower surface side ofThe entire lower surface of the electrode forms the bottom surface of the recess andAn electrode provided so as not to be in contact with the insulating layer; a dielectric layer provided on the upper surface of the electrode; and a conductor layer provided on the upper surface of the dielectric layer, provided on the upper surface of the insulating layer. The present invention relates to the above-mentioned wiring board for mounting a semiconductor device, comprising a capacitor comprising a conductive layer which is conducted to the wiring.
[0021]
Further, according to the present invention, preferably, the support is a lower surface of the insulating layer.~ sideAnd a wiring board for mounting a semiconductor device.
[0023]
The present invention also relates to a semiconductor package in which a semiconductor device is mounted on the wiring board.
[0024]
Also, the present inventionIt is a single layer with a concave part on the lower surface side and made of resinAn insulating layer, a wiring provided on an upper surface of the insulating layer, and the insulating layerInsideAn electrode provided on the lower surface side ofThe entire lower surface of the electrode forms the bottom surface of the recess andA wiring board having an electrode provided so as not to be in contact with an insulating layer, a via located on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring, and the wiring BaseOn a boardThe present invention relates to a semiconductor package having a mounted semiconductor device.
[0028]
The present invention also relates to the above semiconductor package, wherein the electrode has a laminated structure in which a Cu layer is disposed at an upper end thereof and at least one different conductive layer is disposed at a lower end thereof.
[0029]
Further, the present invention provides the above-described semiconductor having a multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. Regarding the package.
[0030]
The present invention also provides the insulating layerInsideAn electrode provided on the lower surface side ofThe entire lower surface of the electrode forms the bottom surface of the recess andAn electrode provided so as not to be in contact with the insulating layer; a dielectric layer provided on the upper surface of the electrode; and a conductor layer provided on the upper surface of the dielectric layer, provided on the upper surface of the insulating layer. The present invention also relates to the above-described semiconductor package having a capacitor comprising a conductive layer that is connected to a wiring.
[0031]
Further, according to the present invention, a step of forming an electrode pattern on a substrate, a step of forming an insulating layer on the substrate so as to cover the electrode pattern, and a step of forming a via hole reaching the electrode pattern in the insulating layer Forming a conductor layer on the insulating layer so as to fill the via hole, and patterning the conductor layer to form a wiring patternRemoving the substrate so that the electrode pattern is exposed; and selectively etching the exposed electrode pattern to remove a predetermined thickness to form a recess on the lower surface of the insulating layer.The present invention relates to a method for manufacturing a wiring board for mounting a semiconductor device, the method including:
[0032]
Further, the present invention further comprises a step of forming a dielectric layer on a predetermined electrode pattern after forming the electrode pattern, wherein the dielectric layer and the electrode pattern below the dielectric layer and the dielectric layer The present invention relates to the above manufacturing method, characterized in that a capacitor is formed with the conductive layer embedded in the via hole.
[0033]
In addition, the present invention relates to the above-mentioned manufacturing method, further comprising a step of selectively removing the substrate to expose the electrode pattern and using a remaining portion of the substrate as a support.
[0034]
The present invention also incorporates a semiconductor device.Further comprising the step ofLater, the substrate is removedDoProcessDoThe present invention relates to the above manufacturing method.
[0036]
Also, in the present invention, in the step of forming an electrode pattern on the substrate, using a conductive substrate as the substrate, forming a resist layer having an opening pattern corresponding to the electrode pattern on the substrate, in the opening pattern The present invention relates to the above-described manufacturing method for forming the electrode pattern by depositing a metal by plating.
[0038]
Further, the present invention provides a step of preparing a laminated plate obtained by bonding a first substrate and a second substrate, forming a first electrode pattern on the first substrate, and forming a first electrode pattern on the second substrate. Forming a second electrode pattern; and forming the first and second electrode patternsThe first and second insulating layers are respectively covered to coverForming a via hole reaching the first electrode pattern in the first insulating layer; and forming a via hole reaching the second electrode pattern in the second insulating layer. Forming a conductor layer on each of the first and second insulating layers so as to fill the via hole,First and secondConductor layerRespectivelyPatter-UniForming first and second wiring patterns by performingSeparating the first substrate and the second substrate, removing the first and second substrates so that the first and second electrode patterns are exposed, respectively, Selectively etching the first and second electrode patterns and removing them by a predetermined thickness to form recesses on the lower surfaces of the first and second insulating layers, respectively;The present invention relates to a method for manufacturing a wiring board for mounting a semiconductor device, the method including:
[0040]
The present invention also relates to the aforementionedIn the step of removing the first and second substrates,Selectively removing the first and second substrates, respectively,First and secondExpose the electrode pattern andFirst and secondThe remaining part of the boardRespectivelyThe present invention relates to the above-described production method having a step of forming a support.
[0041]
The present invention also incorporates a semiconductor device.Further comprising the step ofLater, the first and second substrates are respectively removed.DoProcessDoThe present invention relates to the above manufacturing method.
[0043]
In the present invention, in the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and the first and second substrates are respectively formed on the first and second substrates. Forming a resist layer having an opening pattern corresponding to the second electrode pattern, and depositing a metal in the opening pattern by plating to form the first and second electrode patterns.RespectivelyThe present invention relates to a method for manufacturing the wiring board to be formed.
[0045]
Further, the present invention relates to the above-mentioned method for manufacturing a wiring board, wherein, in forming the electrode pattern, a laminated structure is formed in which a Cu layer is disposed on an upper end portion of the electrode pattern and at least one different conductive layer is disposed on a lower end side.
[0046]
Further, according to the present invention, in the formation of the electrode pattern,The electrode patternThe present invention relates to the above-mentioned method for manufacturing a wiring board, wherein a multilayer structure is formed in which a Cu layer is provided at an upper end portion, a barrier conductive layer for diffusion of solder is provided at a lower end side, and a barrier conductive layer is provided at a lower end side for etching removal of the substrate.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
A preferred embodiment of a wiring board for mounting a semiconductor device (hereinafter, appropriately referred to as a “wiring board”), a semiconductor package, and a method of manufacturing the same will be described.
[0048]
[Wiring board]
FIG. 1 shows a schematic cross-sectional view of one embodiment of the wiring board of the present invention.
[0049]
The wiring board according to the present embodiment includes an insulating layer 6, a wiring 8 provided on the upper surface of the insulating layer 6, an electrode 5 provided on the lower surface side of the insulating layer 6, and a position on the upper surface of the electrode 5. A via 7 provided in the insulating layer 6 so as to conduct the electrode 5 and the wiring 8 is provided, and a support 16 is provided on the lower surface of the insulating layer 6.
[0050]
In the present embodiment, the entire periphery of the side surface of the electrode 5 is in contact with the insulating layer 6, and the lower surface of the electrode 5 is in the same plane as the lower surface of the insulating layer 6. That is, the electrode 5 is embedded in the insulating layer 6 such that the lower surface is exposed from the insulating layer 6. According to the present invention, since the electrode 5 is embedded in the insulating layer 6 as described above, stress and strain on the electrode 5 can be relaxed and concentration of stress can be reduced, and mounting on an external board or device can be achieved. A wiring board having excellent reliability can be obtained.
[0051]
Also, the electrode on the lower surface of the insulating layer in the wiring board of the present invention may be provided so that at least the periphery of the upper end of the electrode is in contact with the insulating layer and at least the lower surface of the electrode is not in contact with the insulating layer. In addition to the structure shown, the structure shown in FIGS. 2A and 2B may be adopted.
[0052]
In the structure shown in FIG. 2A, the insulating layer 6 has a concave portion 41 on the lower surface side, and the electrode 5 is provided in the insulating layer 6 such that the lower surface forms the bottom surface of the concave portion. According to this structure, stress and strain on the electrode 5 are alleviated, stress concentration is reduced, and a wiring board having excellent reliability in mounting on an external board or device can be obtained. Even if they are arranged, solder balls can be easily provided on each electrode 5.
[0053]
In the structure shown in FIG. 2B, the lower end of the electrode 5 protrudes from the lower surface of the insulating layer 6. According to this structure, stress and strain on the electrode 5 are alleviated, stress concentration is reduced, and a wiring board having excellent reliability in mounting on an external board or device can be obtained. Connection reliability can be improved.
[0054]
FIG. 3 is a schematic sectional view showing a structure in which solder balls 31 are provided on electrodes 5 in the configuration shown in FIG. If necessary, a solder resist 17 may be provided around the electrode 5. This solder resist 17 can be similarly provided in the structure shown in FIGS. 2 (a) and 2 (b). The solder resist can be formed from a usual resist material. By providing such a solder resist, rolling can be prevented at the time of solder ball installation, workability can be improved, and after installation, stress concentration at the joint between the solder ball and the electrode can be reduced, Installation stability can be improved.
[0055]
The electrode on the lower surface side of the insulating layer in the wiring board of the present invention can be formed of various conductive materials such as metals and alloys such as Cu, Ag, Au, and Ni. Alternatively, a laminated structure including a reinforcing layer having electrode strength may be employed. As an electrode having a laminated structure, an electrode (Au / Ni / Cu electrode) in which Au, Ni, and Cu are laminated in this order from the lower end, and an electrode in which Ni, Au, Ni, and Cu are laminated in this order from the lower end (Ni / Au / Ni / Cu electrode), an Au / Ni / Cu electrode obtained by removing the lowermost Ni layer from the Ni / Au / Ni / Cu electrode, and Cu, Ag, and Cu in this order from the lower end side. A laminated electrode (Cu / Ag / Cu electrode) can be mentioned. In the above electrode, the intermediate Ni layer functions as a solder diffusion preventing layer. In the Cu / Ag / Cu electrode, the Ag layer functions as a reinforcing layer for improving the strength of the electrode.
[0056]
The support provided on the surface of the insulating layer in the wiring board of the present invention is provided to reinforce the wiring board. By providing the support on the wiring board, deformation such as warpage of the wiring board is suppressed, and the reliability of mounting the semiconductor chip (device) on the wiring board and the mounting reliability of the wiring board or the semiconductor package on an external board or the like. Can be secured.
[0057]
In the embodiment shown in FIG. 1, the support 16 is provided on the lower surface of the insulating layer 6 and is provided around the insulating layer 6 in a frame shape. FIG. 4 shows a schematic bottom view (bottom view) of the wiring board of the present embodiment. The shape of the support in the wiring board of the present invention may be a frame shape as shown in FIG. 4 or a grid shape or a mesh shape in a region other than the electrode 5 (so that the electrode 5 is exposed). Further, the support in the wiring board of the present invention may be provided on the upper surface of the wiring board within a range where the semiconductor device can be mounted. Further, in this case, when sufficient strength can be secured by the support provided on the upper surface, a wiring substrate having no support on the lower surface can be provided.
[0058]
In order to mount a wiring board or a semiconductor package having a semiconductor chip mounted on the wiring board, the electrodes 5 need to be exposed. However, if a process for exposing the electrodes 5 can be performed later, wiring A configuration in which a support (support plate) is provided on the entire lower surface of the substrate may be adopted. In this case, after forming the semiconductor package by mounting the semiconductor chip on the wiring board, the support 5 can be selectively removed in a frame shape or the like to expose the electrode 5. Since the support is formed on the entire lower surface, the flatness of the wiring substrate can be more sufficiently secured when the semiconductor chip is mounted, and the mounting reliability of the semiconductor chip can be improved. When removing the support for exposing the electrode 5, if the produced semiconductor package has sufficient strength to ensure sufficient mounting reliability on an external board even without the support, wiring The entire support on the lower surface of the substrate may be removed.
[0059]
The material of the support is not particularly limited as long as it is a material having heat resistance that can impart the above-described sufficient strength to the wiring board and that can withstand heat treatment during mounting of the semiconductor chip on the wiring board and mounting of the wiring board or the semiconductor package. Although not limited, a conductive material is preferable in terms of manufacturing electrodes, vias, and wiring. As such a conductive material, a metal made of stainless steel, copper, a copper alloy, aluminum, nickel, or the like is preferable because it is inexpensive and easily processed while having sufficient strength.
[0060]
The insulating layer in the wiring board of the present invention can be formed as a single layer made of a single material, but may have a laminated structure in which two or more different materials are laminated as shown in FIG. Good.
[0061]
This insulating layer is preferably 10 μm or more in view of the reliability of mounting the semiconductor chip on the wiring board and the reliability of mounting the wiring board or the semiconductor package on an external board or the like.
[0062]
Examples of the material for the insulating layer include an epoxy resin, a resin obtained from an acrylate compound having both ends having a fluorene skeleton, a polyimide resin, polybenzoxazole, polybenzocyclobutene, or a mixture of two or more of these. Can be applied. In particular, an insulating material having a film strength of 70 MPa or more, an elongation at break of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less (hereinafter abbreviated as “insulating material A” as appropriate). At least a single-layer film made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more (hereinafter abbreviated as “insulating material B” as appropriate). Is preferred. The thickness of these single-layer films is preferably 10 μm or more. Here, the film strength and the elongation at break are values measured by a tensile test of an insulating material in accordance with JIS K 7161 (tensile property test), and the elastic modulus is 0.1% of strain based on the result of the tensile test. Is a value calculated from the intensity at. The coefficient of thermal expansion is a value measured by the TAM method according to JIS C 6481, and the glass transition temperature is a value measured by the DMA method according to JIS C 6481.
[0063]
Examples of the insulating material A include an epoxy resin (manufactured by Hitachi Chemical; MCF-7000LX), a polyimide resin (manufactured by Nitto Denko; AP-6832C), a benzocyclobutene resin (manufactured by Dow Chemical; Cyclotene 4000 series), A polyphenylene ether resin (manufactured by Asahi Kasei; Zylon), a liquid crystal polymer film (manufactured by Kuraray; LCP-A), and a thermosetting resin impregnated with a stretched porous fluororesin (manufactured by Japan Gore-Tex; MICROLAM600) are suitable.
[0064]
Examples of the insulating material B include a glass cloth impregnated epoxy resin (manufactured by Hitachi Chemical; MCL-E-679), an aramid nonwoven fabric impregnated epoxy resin (manufactured by Shin-Kobe Electric Machinery; EA-541), and a stretched porous fluororesin impregnated thermosetting resin. (Manufactured by Japan Gore-Tex; MICROLAM400) and the like are preferable.
[0065]
When the insulating layer in the wiring board of the present invention has a laminated structure, it is preferable to have a layer composed of an insulating material A or B, but as a material constituting the other layer is obtained from an acrylate-based compound having a fluorene skeleton at both ends. It is preferable to use the obtained resin (hereinafter, appropriately referred to as “fluorene-based resin”). Further, in order to further add or improve desired characteristics, a resin mixture containing a fluorene-based resin mixed with another resin as a main component may be used. Such a resin mixture preferably contains a fluorene-based resin in an amount of 80% by mass or more. For example, a resin mixture containing an epoxyoxy resin in an amount of about 5 to 20% by mass, preferably about 5 to 10% by mass is suitably used. be able to. Fluorene-based resins have excellent properties such as heat resistance, low dielectric constant, low thermal expansion coefficient, and low water absorption, and are suitable as insulating materials used for high-density and fine wiring boards. No. 214141.
[0066]
Examples of such a resin include a resin represented by the following general formula (I) and obtained from an acrylate-based compound having a 9,9-diphenylfluorene skeleton at both ends.
[0067]
Embedded image

[0068]
In the formula, R independently represents a hydrogen atom or a lower alkyl group such as methyl, ethyl, n-propyl or isopropyl, and n represents an integer of 0 to 20.
[0069]
By using the above resin material for the insulating layer, it is possible to obtain a wiring board having excellent film strength and elongation at break, particularly excellent crack resistance, and a narrow pitch of 100 μm pitch or less and a high pin count in the area array. A semiconductor chip can be mounted.
[0070]
The present inventors performed a pressure cooker test (temperature: 121 ° C., humidity: 100%) on a wiring board having an insulating layer made of these resins, and no delamination of the resin was observed even after 192 hours. .
[0071]
Further, a temperature cycle test (30 cycles at -65 ° C. for 30 minutes and 150 ° C. for 30 minutes for 1 cycle) is performed on the semiconductor package shown in FIG. As a result, no disconnection or crack occurred even after 1000 cycles.
[0072]
Resin a: film strength 78 MPa, elongation at break 8.5%, glass transition temperature 175 ° C., coefficient of thermal expansion 55 ppm, elastic modulus 2.5 GPa,
Resin b; film strength 180 MPa, elongation at break 30%, glass transition temperature 385 ° C., coefficient of thermal expansion 28 ppm, modulus of elasticity 6.0 GPa,
Resin c; glass transition temperature 180 ° C., thermal expansion coefficient 11 ppm, elastic modulus 11 GPa,
Resin d; glass transition temperature 200 ° C., coefficient of thermal expansion 18 ppm, elastic modulus 12 GPa.
[0073]
The wiring board of the present invention can have a multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately formed on the upper surface of the insulating layer provided with the wiring. . FIG. 6 shows an embodiment having a multilayer wiring structure in which a set of an insulating layer and a wiring is further stacked on the structure shown in FIG. An insulating layer 12 is provided on the insulating layer 6 so as to cover the wiring 8, a wiring 13 is provided on the insulating layer 12, and a via is formed in the insulating layer 12 so that the wiring 13 and the wiring 8 are conducted. Is provided. In such a multilayer wiring structure, it is preferable that at least one of the insulating layers is made of the insulating material A or B, and that the other insulating layer is made of the fluorene-based resin.
[0074]
In the wiring board of the present invention, as in the embodiment shown in FIG. 7, a dielectric layer 93 is provided on the upper surface of some of the plurality of electrodes 5 provided on the lower surface side, and a via layer is formed on the dielectric layer 93. By providing the conductor 7, a capacitor including the electrode 5, the dielectric layer 93, and the via conductor 7 can be provided. By forming such a capacitor, transmission noise can be reduced, and a wiring board optimal for high-speed operation can be obtained. As the material of the dielectric layer, titanium oxide (TiO 2)₂), Tantalum oxide (Ta)₂O₅), Aluminum oxide (Al₂O₃), Silicon oxide (SiO₂), Niobium oxide (Nb₂O₅), BST (Ba_xSr_1-xTiO₃), PZT (PbZr_xTi_1-xO₃), PLZT (Pb_1-yLa_yZr_xTi_1-xO₃), SrBi₂Ta₂O₉And other perovskite materials.
[0075]
As shown in FIGS. 8A and 8B, the wiring board of the present invention has a form in which the above-described wiring board structure is formed on both sides of a laminated board on which two support substrates 1 are bonded. You can also. In this embodiment, two support substrates are separated into two wiring substrates or a semiconductor package before or after mounting a semiconductor chip, and the support substrate 1 is removed so that the electrodes 5 are exposed as described above, respectively. It can be in a form that can be mounted on another board or the like.
[0076]
[Semiconductor package]
The semiconductor package of the present invention can be formed by mounting a semiconductor chip on the upper surface of the wiring board of the present invention. The electrical connection portion such as the pad of the semiconductor chip and the wiring of the wiring board can be electrically connected by various methods, for example, a flip chip method, a wire bonding method, and a tape bonding method.
[0077]
FIG. 9 shows an embodiment using the flip chip method. As shown in FIG. 9A, the semiconductor package of the present invention can be configured such that the substrate 1 is provided on the entire lower surface of the wiring substrate. In this case, when mounting on another board or the like, the substrate 1 is removed so that the electrodes 5 are exposed. As a form in which the electrode 5 is exposed, as shown in FIG. 9B, the substrate 1 is processed and left on the lower surface of the insulating layer 6 in a frame shape, a lattice shape or a mesh shape, and a support for reinforcing the semiconductor package is formed. 16 can be used. If sufficient strength can be ensured without forming such a support, the entire substrate 1 may be removed to obtain a form as shown in FIG. 9C. As shown in FIGS. 9A to 9C, when a semiconductor chip is sealed with a mold resin, the mold resin also functions as a support, so that sufficient strength is secured without providing the support 16. It is possible.
[0078]
Further, in the semiconductor package of the present invention, as in the embodiment shown in FIG. 9, the pad 19 provided on the semiconductor chip 18 and the wiring 8 of the wiring structure 9 corresponding to the wiring board of the present invention are made of, for example, metal. Electrical connection can be made via the bumps 20. At this time, the semiconductor chip 18 and the wiring structure9If necessary, an underfill resin 21 can be filled. Further, the semiconductor chip on the wiring structure 9 can be encapsulated by a transfer molding method using the molding resin 22. Alternatively, as shown in FIG. 9D, a heat sink 33 may be provided on the semiconductor chip 18 and then sealed by another sealing method in order to increase heat radiation.
[0079]
Further, as shown in FIG. 10, the semiconductor package of the present invention may have a form in which semiconductor chips are mounted on both sides. Such a configuration can be formed by mounting semiconductor chips on both surfaces of the wiring board described with reference to FIG. When this semiconductor package is mounted on another board or the like, the laminated substrate on which the two substrates are bonded is separated into two to form two semiconductor packages, and the electrode 5 of the wiring structure 9 is formed as described above. The substrate 1 can be removed so that the substrate is exposed, and can be mounted on another board or the like.
[0080]
[Method of Manufacturing Wiring Board and Semiconductor Package]
FIG. 11 shows a cross-sectional process drawing of an embodiment of the manufacturing method of the present invention.
[0081]
First, as shown in FIG. 11A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate of stainless steel, Cu, Cu alloy, Al, Ni, etc., and this resist layer is patterned. Thus, a resist mask 2 having an opening 3 corresponding to a predetermined electrode pattern is formed.
[0082]
Next, as shown in FIG. 11B, current is supplied from the substrate 1 and a plating layer 4 is formed on the substrate 1 in the opening 3 by electrolytic plating. Next, as shown in FIG. 11C, the resist mask 2 is removed, and a plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 is left on the substrate 1, and this is replaced with an electrode 5 And As described above, in order to form the electrode 5, it is desirable to use an electrolytic plating method capable of depositing a dense metal from the viewpoint of reliability. However, the plating layer 4 is deposited in the opening 3 by an electroless plating method. Thus, the electrode 5 can be formed.
[0083]
Next, as shown in FIG. 11D, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole reaching the electrode 5 is formed on the insulating film 6 by photolithography or laser processing. 7a is formed.
[0084]
As the material of the insulating layer 6, various insulating resins such as epoxy resin, fluorene resin, polyimide resin, polybenzoxazole, and polybenzocyclobutene can be used. This insulating layer 6 may be composed of a plurality of resin layers as shown in FIG. 5, for example, in order to improve the mounting reliability.
[0085]
Next, as shown in FIG. 11E, a conductor layer is formed on the insulating layer 6 so as to fill the via hole 7a by a sputtering method, an electroless plating method, an electrolytic plating method, or the like. The wiring layer 8 is formed by patterning by photolithography. Alternatively, after a conductor layer is formed so as to fill the via hole 7a, an unnecessary conductor layer on the upper surface of the insulating layer 6 is removed to leave a conductor only in the via hole 7a to form a via 7. The same or different conductive layers connected to the vias may be formed and then patterned to form the wiring layer 8.
[0086]
As described above, the wiring board of the present embodiment can be formed. To make the wiring board mountable on another board or the like, for example, as shown in FIGS. The substrate 1 is selectively etched to expose the electrode 5 for electrically connecting to the outside, and the substrate left in a frame shape on the outer periphery of the insulating layer 6 is used as a support 16. As described above, the support 16 can be formed in a lattice shape or a mesh shape in addition to the frame shape.
[0087]
Thereafter, if necessary, as shown in FIG. 3, a solder resist 17 may be formed around the electrode 5 to mount a solder ball on the electrode 5, and a solder ball 31 may be further mounted.
[0088]
After forming the wiring layer 8, as shown in FIG. 12, a cover coat 10 is formed on the insulating layer 6 so as to cover the wiring layer 8, and a predetermined position of the cover coat 10 is electrically connected to the semiconductor chip. An opening can be provided as the pad portion 11 for this. The pad portion 11 can be used as an electrode pad by embedding a conductor in the opening.
[0089]
After forming the wiring layer 8, as shown in FIG. 6, an insulating layer 12 is formed on the insulating layer 6 so as to cover the wiring layer 8, and the via and the insulating layer are formed in the insulating layer 12 in the same manner as described above. The wiring layer 13 can be formed on the layer 12 to provide a multilayer wiring structure. By repeating this process, the number of layers can be increased to an arbitrary number.
[0090]
According to such a manufacturing method of the present embodiment, it is extremely easy to narrow the pitch of the electrodes 5 and increase the accuracy. In addition, since the electrode 5 has a structure embedded in the insulating film 6, stress and strain on the electrode 5 can be reduced, and stress concentration is reduced, so that the mounting reliability with an external board or device is excellent. A wiring board can be manufactured. If a semiconductor chip is mounted on the wiring board of the present embodiment to form a semiconductor package, the reliability of mounting the semiconductor package on an external board or device can be improved.
[0091]
Furthermore, since the substrate 1 used for forming the electrode 5 can be left as the support 16 of the wiring board in the removing step for exposing the electrode 5, a separate step of providing a support is unnecessary, and the method is simple. According to the method, a wiring board excellent in handleability and excellent in chip mounting reliability and mounting reliability on another board or the like can be manufactured.
[0092]
A wiring board having a wiring structure formed on both sides of a laminate as shown in FIG. 8 can be manufactured, for example, as follows.
[0093]
First, as shown in FIG. 13A, a laminate 25 in which a first substrate and a second substrate are bonded is prepared. For example, an epoxy-based or polyimide-based heat-resistant adhesive resin is disposed around one substrate 1 (adhesion region 24), and the other substrate is bonded and fixed to the surface.
[0094]
Next, a resist layer is formed on both sides of the laminate in the same manner as described above, and these are patterned to form an opening pattern corresponding to predetermined first and second electrode patterns. Next, a current is supplied from the substrate 1 to form a plating layer in the opening of the resist layer by an electrolytic plating method. Subsequently, the resist layer is removed, and the first and second electrodes 5 are provided on both surfaces of the laminate 25, respectively. Form. Next, in the same manner as described above, the insulating layers 6 are formed on both surfaces of the laminate 25, and via holes are formed in these insulating layers, respectively. Then, a conductive film is formed so as to fill these via holes. Then, these are patterned to form the wiring 8 (FIG. 13B). Thereafter, by cutting the wiring substrate 26 at the position indicated by the dotted line (inside the bonding area 24) shown in FIG. 13B, the first and second substrates 1 bonded as shown in FIG. To obtain two wiring boards. Alternatively, a semiconductor chip is mounted on at least one surface of a wiring board, and a semiconductor package is formed by mounting semiconductor chips on both surfaces, for example, as shown in FIG. Can be separated to obtain two semiconductor packages.
[0095]
According to such a manufacturing method, the process can be simplified, so that productivity can be improved and cost can be reduced.
[0096]
[Method of Manufacturing Wiring Board Having Laminated Electrodes]
FIG. 14 shows an embodiment of a method for manufacturing a wiring board having stacked electrodes.
[0097]
In the manufacturing method of this embodiment, a stainless steel plate is used as the substrate 1, and an electrode having a three-layer structure in which an Au plating layer, a Ni plating layer, and a Cu plating layer are laminated in this order from the lower surface side of the wiring board is formed.
[0098]
First, as shown in FIG. 14A, a resist layer for forming a plating film is formed on a substrate 1 made of stainless steel (for example, Nisshin Steel; SUS304), and the resist layer is patterned to a predetermined shape. A resist mask 2 having an opening 3 corresponding to the electrode pattern is formed.
[0099]
Here, the preferable thickness of the substrate 1 is 0.1 mm to 1.0 mm, and more preferably 0.2 mm to 0.8 mm. The reason is that if the plate thickness is too thin, warpage is likely to occur in the manufacturing process of the wiring board, and it becomes difficult to form fine wiring with reduced precision. This is because the handleability is reduced due to the increase in weight.
[0100]
Next, as shown in FIG. 14B, the opening is formed by electrolytic plating or electroless plating.3The Au plating layer 4a, the Ni plating layer 4b, and the Cu plating layer 4c are formed on the substrate 1 in this order. The thickness of each plating layer is preferably 0.3 μm to 3 μm for the Au plating layer, 1 μm to 7 μm for the Ni plating layer, and 5 μm or more for the Cu plating layer.
[0101]
Next, as shown in FIG. 14C, the resist mask 2 is removed from the substrate 1, leaving a plating layer having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 on the substrate 1. The electrode 5 has a three-layer structure of Au / Ni / Cu.
[0102]
Next, as shown in FIG. 14D, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole 7a reaching the electrode 5 is formed in the insulating layer 6.
[0103]
Next, as shown in FIG. 14E, a conductor layer is formed on the insulating layer 6 so as to fill the via hole 7a, and the conductor layer is patterned to form a wiring layer 8.
[0104]
Finally, as shown in FIG. 14 (f), a predetermined region of the substrate 1 is removed from the lower surface by etching to expose the electrode 5, and at the same time a support 16 is formed.
[0105]
In the present embodiment having the Au / Ni / Cu three-layered electrode 5, there is sufficient adhesion at the interface between the substrate 1 made of stainless steel and the Au plating layer, so that peeling does not easily occur. Further, the Au plating layer hardly diffuses into the substrate 1 or the Ni plating layer depending on the heat history at the time of manufacturing such as the formation of the insulating layer 6. For this reason, the Au plating layer can fulfill a sufficient function as a barrier metal at the time of etching the substrate 1, and the etching conditions can be selected widely. Therefore, the production yield, productivity, and handleability can be improved. Further, when a solder ball is mounted on the electrode 5 and electrically connected to an external board or device, the Ni plating layer functions as a solder diffusion preventing layer, so that mounting reliability can be improved.
[0106]
As a method of manufacturing a wiring substrate having another stacked electrode, a Cu plate or a Cu alloy plate (for example, Kobe Steel; KFC) is used as the substrate 1, and a Ni plating layer, an Au plating layer, An electrode having a four-layer structure in which a Ni plating layer and a Cu plating layer are stacked in this order can be formed. This structure can be formed in the same manner as described above except that the electrode structure is different from that of the substrate 1.
[0107]
The thickness of the substrate 1 is preferably 0.1 mm to 1.0 mm as in the above method, the thickness of the Ni plating layer is 1 μm or more from the substrate 1 side, the thickness of the Au plating layer is 0.3 μm to 3 μm, It is preferable that the thickness of the plating layer is 1 to 7 μm, and the thickness of the Cu plating layer is 5 μm or more.
[0108]
The substrate 1 made of Cu or a Cu alloy (hereinafter appropriately referred to as “Cu substrate”) can be easily etched with a copper chloride or iron chloride-based etchant, and thus has the advantage of further improving productivity.
[0109]
According to the inventor's studies, the Cu substrate has a characteristic different from that of a substrate made of stainless steel. Therefore, if an Au plating layer is directly formed on the Cu substrate, the manufacturing process of the wiring substrate is reduced. It has been found that the heat history in Example 2 causes metal diffusion between the Cu substrate and the Au plating layer, and does not function as a barrier metal during etching. Therefore, as a result of diligent studies, it has been found that this problem of metal diffusion can be solved by forming another plating layer on the Cu substrate via the Ni plating layer 52. Furthermore, since the intermediate Ni layer also functions as a solder diffusion preventing layer, it was found that the electrode 5 having a Ni / Au / Ni / Cu plated multilayer structure was most suitable as an electrode for a wiring board.
[0110]
As another embodiment, a Cu / Ag / Cu electrode can be formed in the same manner as described above, and the substrate in this case is not particularly limited, but for example, a Cu substrate or a stainless steel plate can be used.
[0111]
[Manufacturing method of wiring substrate having concave electrode structure]
As shown in FIG. 2A, the electrodes of the wiring board of the present invention may have a structure that is exposed from the bottom surface of the concave portion 41 provided on the lower surface of the insulating layer 6. This structure can be obtained by, for example, removing the electrode 5 from the lower surface side of the wiring board (insulating layer 6) by a predetermined thickness to form the concave portion 41 as shown in FIG. In the case of an electrode having a multilayer structure composed of a plurality of different material layers as shown in FIG. 15, it is possible to easily remove by a predetermined thickness a layer unit by an etching rate difference depending on the material. For example, in the electrode 5 having the Ni / Au / Ni / Cu plating multilayer structure, only the Ni plating layer is removed by etching to form a structure depressed with respect to the lower surface of the insulating layer (lower surface of the wiring board). With such a structure, the solder balls can be easily mounted even when the electrodes 5 have a narrow pitch.
[0112]
[Method of Manufacturing Wiring Board Having Protruding Electrode Structure]
The electrodes in the wiring board of the present invention may have a structure protruding from the lower surface of the insulating layer 6, as shown in FIG. This structure can be formed, for example, as follows.
[0113]
First, as shown in FIG. 16A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate, and the resist layer is patterned to form an opening 3 corresponding to a predetermined electrode pattern. Is formed.
[0114]
Next, as shown in FIG. 16B, the upper surface of the substrate 1 is etched using the resist mask 2 as an etching mask to form a concave portion 51 corresponding to the opening 3 of the resist mask 2 on the upper surface of the substrate 1.
[0115]
Next, as shown in FIG. 16C, a metal is deposited on the exposed substrate 1 by a plating method to form a plating layer 4 in the recess 51 and the opening 3. Next, as shown in FIG. 16D, the resist mask 2 is removed, and a plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 is left on the substrate 1, and this is replaced with an electrode 5 And
[0116]
Next, as shown in FIG. 16E, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole reaching the electrode 5 is formed on the insulating layer 6 by photolithography or laser processing. 7a is formed.
[0117]
Next, as shown in FIG. 16F, a conductor layer is formed on the insulating layer 6 so as to fill the via holes 7a by a sputtering method, an electroless plating method, an electrolytic plating method, or the like. The wiring layer 8 is formed by patterning by photolithography.
[0118]
Then, as shown in FIG. 2B, the substrate 1 in a predetermined region is selectively etched from the lower surface side to expose the electrode 5 for electrically connecting to the outside, and, for example, on the outer periphery of the insulating layer 6. The substrate is left as a support 16 in a frame shape.
[0119]
As described above, a convex electrode can be easily formed. Note that by adjusting the etching amount in the step shown in FIG. 16B, the size of the electrode projecting from the lower surface of the insulating layer can be adjusted.
[0120]
[Method of Manufacturing Wiring Board Having Capacitor]
As described above, the wiring board of the present invention may be configured to have a capacitor as shown in FIG. 7, for example. The configuration having a capacitor can be formed, for example, as follows.
[0121]
First, as shown in FIG. 17A, a substrate is formed according to the above-described plating method.91An electrode 92 is formed thereon.
[0122]
Next, as shown in FIG. 17B, a dielectric layer 93 is formed on some of the plurality of electrodes by, for example, a sputtering method using a metal mask.
[0123]
Next, as shown in FIG. 17C, the substrate on which the electrodes 92 and the dielectric layers 93 are formed is formed.91An insulating layer 94 is formed thereon, and a via hole 95a is formed in the insulating layer 94 by a photolithography method or a laser processing method.
[0124]
Next, as shown in FIG. 17D, a conductor layer is formed on the insulating film 94 so as to fill the via hole 95a, and the conductor layer is patterned to form a wiring layer 96.
[0125]
After that, as shown in FIG.91Is selectively etched from the lower surface side to expose an electrode 92 for electrically connecting to the outside and form a support body 97.
[0126]
Since the dielectric layer 93, the electrode 92 below the dielectric layer 93, and the via conductor layer 95 on the dielectric layer 93 have a function as a capacitor, transmission noise can be reduced. This makes it possible to obtain a wiring board that is optimal for high-speed operation.
[0127]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a high density and fine wiring of a wiring board corresponding to an increase in the number of terminals and a narrow pitch of a semiconductor device, and to cope with miniaturization and high density of a system. The pitch of the external electrodes of the wiring substrate can be reduced. Further, a wiring board having excellent mounting reliability can be provided, and a semiconductor package having high performance and excellent reliability can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of one embodiment of a wiring board for mounting a semiconductor device of the present invention.
FIG. 2 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 4 is a schematic bottom (bottom) view of one embodiment of a wiring board for mounting a semiconductor device of the present invention.
FIG. 5 is a schematic sectional view of another embodiment of a wiring board for mounting a semiconductor device according to the present invention.
FIG. 6 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 7 is a schematic cross-sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 8 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 9 is a schematic sectional view of an embodiment of a semiconductor package of the present invention.
FIG. 10 is a schematic sectional view of another embodiment of the semiconductor package of the present invention.
FIG. 11 is a sectional process view showing one embodiment of a method for manufacturing a wiring board for mounting a semiconductor device according to the present invention;
FIG. 12 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.
FIG. 13 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.
FIG. 14 is a sectional process view showing another embodiment of the method of manufacturing a wiring board for mounting a semiconductor device according to the present invention.
FIG. 15 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.
FIG. 16 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.
FIG. 17 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device according to the present invention;
FIG. 18 is a sectional process view showing a conventional method of manufacturing a wiring board for mounting a semiconductor device.
[Explanation of symbols]
1 substrate
2 Resist mask
3 opening
4 Plating layer
5 electrodes
6 Insulation layer
7 Via
7a Via Hall
8 Wiring layer
9 Wiring structure
10 Cover coat
11 Pad section
12 Insulating layer
13 Wiring layer
16 Support
17 Solder resist
18 Semiconductor chip
19 pads
20 Metal bump
21 Underfill resin
22 Mold resin
24 Adhesion area
25 laminated board
26 Wiring board
31 Solder BowLe
33 heat sink
41 recess
51 recess
91 substrate
92 electrodes
93 dielectric layer
94 Insulation layer
95 Via conductor
96 wiring
97 Support
101 metal plate
102 insulating layer
103 Via Hall
104 Wiring pattern
105 Flip chip pad
106 insulating layer
107 substrate reinforcement
108 External electrode terminal

Claims (42)

And a single layer in which the insulating layer made of and the resin having a recess in a lower surface, said insulating layer and a wiring provided on the upper surface of the lower surface of the electrode an electrode provided on the lower surface side of the insulating layer And an electrode provided so as to form the bottom surface of the concave portion and not contact with the insulating layer, and provided on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring. And a support provided on the surface of the insulating layer. 2. The wiring board for mounting a semiconductor device according to claim 1, wherein the electrode has a laminated structure in which a Cu layer is disposed at an upper end thereof and at least one different conductive layer is disposed at a lower end thereof. 3. According to claim 1 or 2 having a multilayer wiring structure in which wiring and is provided at least one set sequentially alternating the wiring is formed on the upper surface of the further insulating layer on the upper surface of the formed the insulating layer the insulating layer Wiring board for mounting semiconductor devices. 4. The semiconductor device mounting according to claim 1 , further comprising an insulating layer made of an insulating material having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less. Wiring board. 4. The wiring board for mounting a semiconductor device according to claim 1 , further comprising an insulating layer made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more. The wiring board for mounting a semiconductor device according to claim 4 or 5 , further comprising an insulating layer made of a resin formed from an acrylate-based compound having a fluorene skeleton at both ends. An electrode provided on the lower surface side in the insulating layer , wherein the entire lower surface of the electrode forms a bottom surface of the concave portion and is provided so as not to be in contact with the insulating layer ; and an electrode provided on the upper surface of the electrode. a dielectric layer which is, according to claim 1 to 6 having a capacitor composed of the conductor layer electrically connected to the wiring provided on the upper surface of the insulating layer a conductive layer provided on the upper surface of the dielectric layer The wiring board for mounting a semiconductor device according to any one of the above. The wiring board for mounting a semiconductor device according to claim 1, further comprising a solder ball on a lower surface of the electrode. The wiring board for mounting a semiconductor device according to claim 1, wherein the support is provided on a lower surface side of the insulating layer. The semiconductor device mounting wiring board according to any one of claims 1-9 wherein the support is made of metal. 11. The wiring board for mounting a semiconductor device according to any one of 1 to 10, wherein a surface on the upper surface side of the insulating layer is a surface for mounting a semiconductor device. Semiconductor package semiconductor device is mounted on the wiring board according to any one of claims 1 to 10. A semiconductor package comprising: the wiring substrate according to claim 1; and a semiconductor device mounted on a surface of the wiring substrate on the insulating layer upper surface side. The semiconductor package according to claim 12 or 13 is sealed semiconductor device by a transfer molding resin. The semiconductor package according to claim 12 or 13 heat sink is provided on the semiconductor device. And a single layer in which the insulating layer made of and the resin having a recess in a lower surface, said insulating layer and a wiring provided on the upper surface of the lower surface of the electrode an electrode provided on the lower surface side of the insulating layer And an electrode provided so as to form the bottom surface of the concave portion and not contact with the insulating layer, and provided on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring. a wiring substrate having a via that is, a semiconductor package having a semiconductor device mounted on the wiring board. 17. The semiconductor package according to claim 16, wherein the semiconductor device is mounted on a surface of the wiring board on the upper surface side of the insulating layer. The semiconductor package according to claim 16 , wherein the electrode has a stacked structure in which a Cu layer is disposed at an upper end and at least one different conductive layer is disposed at a lower end. 19. The multilayer wiring structure according to claim 16, wherein a multilayer wiring structure is further provided in which one or more sets of insulating layers and wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. The semiconductor package as described. The film according to any one of claims 16 to 19, further comprising an insulating layer made of an insulating material having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C or more, and a thermal expansion coefficient of 60 ppm or less. Semiconductor package. The semiconductor package according to claim 16 , further comprising an insulating layer made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more. 22. The semiconductor package according to claim 20, further comprising an insulating layer made of a resin formed from an acrylate compound having a fluorene skeleton at both ends. An electrode provided on the lower surface side in the insulating layer , wherein the entire lower surface of the electrode forms a bottom surface of the concave portion and is provided so as not to be in contact with the insulating layer; a dielectric layer provided, according to claim 16 having a capacitor consisting of the dielectric layer conductor layer a conductive layer formed on the upper surface electrically connected to the wiring provided on the upper surface of the insulating layer 23. The semiconductor package according to any one of 22 . The semiconductor package according to any one of claims 16 to 23 , wherein a solder ball is provided on a lower surface of the electrode. The semiconductor package according to any one of claims 16 to 24 , wherein the semiconductor device is sealed with a transfer mold resin. The semiconductor package of any one of claims 16 to 24 having a heat sink on the semiconductor device. Forming an electrode pattern on a substrate, forming an insulating layer on the substrate so as to cover the electrode pattern, forming a via hole in the insulating layer that reaches the electrode pattern, Forming a conductor layer on the insulating layer so as to bury the pattern, forming a wiring pattern by patterning the conductor layer , removing the substrate so that the electrode pattern is exposed, Selectively etching the electrode pattern and removing the electrode pattern by a predetermined thickness to form a recess on the lower surface of the insulating layer . After the electrode pattern is formed, the method further includes a step of forming a dielectric layer on a predetermined electrode pattern, wherein the dielectric layer and the electrode pattern below the dielectric layer are embedded in via holes reaching the dielectric layer. 28. The manufacturing method according to claim 27 , wherein a capacitor is formed with the conductive layer formed. In the step of removing said substrate, The method according to claim 27 or 28 comprising the step of the remaining portion of the substrate and the support to expose the electrode pattern by selectively removing the substrate. Further comprising a step of mounting the semiconductor device, after the method according to claim 27 or 28 performing the step of removing the substrate. In the step of forming an electrode pattern on the substrate, a conductive layer is used as the substrate, a resist layer having an opening pattern corresponding to the electrode pattern is formed on the substrate, and a metal is formed in the opening pattern by plating. The manufacturing method according to any one of claims 27 to 30, wherein the electrode pattern is formed by deposition. In the step of forming the electrode pattern, an electrode pattern having a multilayer structure composed of different kinds of material layers is formed, and in the step of forming the concave portions, the electrode is removed by performing layer-by-layer etching depending on a difference in an etching rate depending on a material. The manufacturing method according to any one of claims 27 to 31, wherein the pattern is selectively etched and removed by a predetermined thickness. A step of preparing a laminate obtained by bonding a first substrate and a second substrate; forming a first electrode pattern on the first substrate; and forming a second electrode pattern on the second substrate. Forming a first and a second insulating layer on the laminate so as to cover the first and second electrode patterns, respectively ; and forming the first insulating layer on the first insulating layer. Forming a via hole reaching the second electrode pattern and forming a via hole reaching the second electrode pattern in the second insulating layer; and forming the first and second insulating layers so as to fill the via hole. each forming a conductor layer thereon, said forming a first and second wiring patterns of the first and second conductor layer respectively pattern over two ring, and said first substrate first Separating the first and second substrates; Removing the first and second substrates so that the second electrode pattern is exposed; and selectively removing the exposed first and second electrode patterns by a predetermined thickness, respectively. Forming a recess on each of the lower surfaces of the first and second insulating layers . In the step of removing the first and second substrates, the first and second substrates are selectively removed to expose the first and second electrode patterns and to remove the first and second substrates. the process according to claim 33 comprising the step of remaining portions of the respective support. Further comprising a step of mounting the semiconductor device, after the method according to claim 33 for removing the first and second substrates, respectively. In the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and the first and second electrode patterns are formed on the first and second substrates, respectively. 36. The wiring board according to claim 33, 34 or 35 , wherein a resist layer having a corresponding opening pattern is formed, and a metal is deposited in the opening pattern by plating to form the first and second electrode patterns, respectively. Manufacturing method. In the step of forming the first and second electrode patterns, an electrode pattern having a multilayer structure composed of different types of material layers is formed, and in the step of forming the concave portions, etching is performed in units of layers due to a difference in etching rate depending on the material. The manufacturing method according to any one of claims 33 to 36, wherein the first and second electrode patterns are selectively etched to remove a predetermined thickness thereof by performing the removal. The wiring substrate according to claim 31, 32 , 36 or 37 , wherein in forming the electrode pattern, a multilayer structure is formed in which a Cu layer is disposed at an upper end of the electrode pattern and at least one different conductive layer is disposed at a lower end. Production method. In the formation of the electrode pattern , a laminated structure is formed in which a Cu layer is disposed at an upper end of the electrode pattern , a barrier conductive layer is disposed at a lower end side for diffusion of solder, and a barrier conductive layer is disposed at a lower end side for etching removal of the substrate. A method for manufacturing a wiring board according to claim 31, 32 , 36 or 37 . The wiring according to claim 31, 32 , 36 , or 37 , wherein the substrate is a stainless steel plate, and the electrode pattern is formed by laminating an Au plating layer, a Ni plating layer, and a Cu plating layer on the substrate in this order. Substrate manufacturing method. The substrate is a Cu plate or a Cu alloy plate, the electrode pattern is on the substrate, Ni plating layer, Au plating layer, Ni plating layer, claim 31 and 32 formed by laminating a Cu plating layer in this order , 36 or 37 . The method according to claim 31, 32 , 36, or 37 , wherein the electrode pattern is formed by laminating a Cu plating layer, an Ag plating layer, and a Cu plating layer on the substrate in this order.

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