JP2012004440A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board capable of reducing its warpage and enabling high-density packaging.SOLUTION: In a wiring board, multiple wiring layers and multiple insulation layers made of insulating resin of the same composition are alternately laminated. The wiring board comprises a first main surface and a second main surface which is the opposite side of the first surface; a first electrode pad exposed from a first insulation layer nearest to the first main surface, which is arranged at a first pitch; a second electrode pad exposed from an opening of an second insulation layer, which is provided on a third insulation layer adjacent to the second insulation layer nearest to the second main surface at a second pitch wider than the first pitch; and a through-hole provided in a third insulation layer in which a conductor for electrically connect the second electrode pad and a wiring layer coated with the third insulation layer is formed. The diameter of the through-hole on the side of the second electrode pad is larger than the diameter of the through-hole on the side of the wiring layer coated with the third insulation layer, and the second insulation layer includes a reinforcement member.

Description

  The present invention relates to a wiring board in which a wiring layer and an insulating layer are laminated.

  FIG. 1 is a cross-sectional view illustrating a conventional wiring board. Referring to FIG. 1, a conventional wiring board 100 includes a first wiring layer 110, a first insulating layer 120, a second wiring layer 130, a second insulating layer 140, a third wiring layer 150, a third insulating layer 160, A fourth wiring layer 170 and a fourth insulating layer 180 are included.

  The first wiring layer 110, the second wiring layer 130, the third wiring layer 150, and the fourth wiring layer 170 are each made of, for example, copper (Cu). The first insulating layer 120, the second insulating layer 140, the third insulating layer 160, and the fourth insulating layer 180 are each composed of, for example, an epoxy-based insulating resin.

  The first wiring layer 110 and the second wiring layer 130 are electrically connected through the first via hole 120x. The via wiring constituting the second wiring layer 130 is formed so as to cover the side wall of the first via hole 120x, and has a recess 130x in the vicinity of the center. The second wiring layer 130 and the third wiring layer 150 are electrically connected through the second via hole 140x. The third wiring layer 150 and the fourth wiring layer 170 are electrically connected through the third via hole 160x.

  The side surface and the lower surface of the first wiring layer 110 (the surface connected to the via wiring of the second wiring layer 130) are covered with the first insulating layer 120. The upper surface of the first wiring layer 110 (the surface opposite to the surface connected to the via wiring of the second wiring layer 130) is exposed from the first insulating layer 120 and is electrically connected to a mounting board (not shown) such as a motherboard. It functions as an electrode pad. A part of the fourth wiring layer 170 is exposed from an opening 180x formed in the fourth insulating layer 180, and functions as an electrode pad electrically connected to a semiconductor chip or the like (not shown). The pitch of the fourth wiring layer 170 exposed from the opening 180 x is narrower than the pitch of the first wiring layer 110 exposed from the first insulating layer 120.

  The first insulating layer 120 on the side connected to a mounting substrate (not shown) such as a mother board includes a glass fiber bundle 190a arranged in parallel in the X direction and a glass fiber bundle 190b arranged in parallel in the Y direction. A glass cloth 190 having a flat-woven form in a lattice shape is included. With such a structure, the warp of the wiring board 100 can be reduced.

The wiring board 100 can be manufactured as follows, for example. 2 to 4 are diagrams illustrating a conventional manufacturing process of a wiring board. First, in the step shown in FIG. 2, the first wiring layer 110 is formed on the support 210, and the first insulating layer 120 including the glass cloth 190 is formed on the support 210 so as to cover the first wiring layer 110. Form. Then, a first via hole 120x that penetrates the first insulating layer 120 and exposes the upper surface of the first wiring layer 110 is formed in the first insulating layer 120 by a laser processing method using, for example, a CO ₂ laser. At this time, the end of the glass cloth 190 cut by the laser protrudes from the side wall of the opening 120x.

  Next, in the step shown in FIG. 3, the second wiring layer 130 is formed on the first insulating layer 120. The second wiring layer 130 includes a via wiring formed in a part of the first via hole 120 x and a wiring pattern formed on the first insulating layer 120. The via wiring constituting the second wiring layer 130 is formed so as to cover the side wall of the first via hole 120x, and a recess 130x is formed near the center. The second wiring layer 130 is electrically connected to the first wiring layer 110 exposed at the bottom of the first via hole 120x.

  Next, in the process illustrated in FIG. 4, the second insulating layer 140, the third wiring layer 150, the third insulating layer 160, the fourth wiring layer 170, and the fourth insulating layer 180 are stacked on the first insulating layer 120. . Then, an opening 180 x exposing a part of the fourth wiring layer 170 is formed in the fourth insulating layer 180. As a result, a predetermined buildup wiring layer is formed on one surface of the support 210. Further, by removing the support 210, the wiring board 100 shown in FIG. 1 is completed. 1 is drawn upside down from FIGS. 2 to 4.

JP 2009-224739 A JP 2009-077655 International Publication No. 03/039219 Pamphlet

  By the way, in the wiring board 100, the thickness of the 1st insulating layer 120 containing the glass cloth 190 becomes thicker than the thickness of the other insulating layer which does not contain a glass cloth. Accordingly, the first via hole 120x formed in the first insulating layer 120 is deeper than the second via hole 140x formed in the second insulating layer 140 and the third via hole 160x formed in the third insulating layer 160. In addition, the diameter at the opening end (the diameter on the second insulating layer 140 side) is also increased. That is, it is difficult to reduce the diameter and the volume of the first via hole 120x increases.

  It is technically and costly difficult to completely fill the entire first via hole 120x having such a large volume with the via wiring. Therefore, the via wiring of the second wiring layer 130 is formed on the side wall of the first via hole 120 x, but the first via hole 120 x is not completely filled, and the vicinity of the central portion of the via wiring constituting the second wiring layer 130. A recess 130x is formed in the.

  If another via hole is formed immediately above the first via hole 120x in which the recess 130x is formed in the vicinity of the central portion of the via wiring, the via wiring of the other via hole is formed on the recess 130x. Connection reliability between wirings decreases. Therefore, as shown in FIG. 4, the second via hole 140x is not formed immediately above the first via hole 120x, but is formed on the wiring pattern of the second wiring layer 130 extending laterally from within the first via hole 120x. is doing.

  Thus, from the viewpoint of connection reliability, no other via hole can be formed immediately above the first via hole 120x, and a plurality of via holes are stacked in the vertical direction and interconnected in the first via hole 120x. A so-called stacked via structure cannot be adopted.

  That is, as shown in FIGS. 2 to 4, the first insulating layer 120 including the glass cloth 190 is formed on the support 210 so as to cover the first wiring layer 110, and the wiring layer and the insulating layer are formed thereon. The wiring substrate 100 manufactured by this method is advantageous in that it can reduce warpage, but the first via hole 120x formed in the first insulating layer 120 has a large volume and cannot completely fill the via wiring. In other words, the so-called stacked via structure cannot be adopted, and there is a problem that the high density of the wiring substrate 100 is hindered.

  This invention is made | formed in view of said point, and makes it a subject to provide the wiring board which can respond to densification while being able to reduce curvature.

  In one form of the present wiring board, a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately stacked, and the second main surface is the first main surface and the opposite surface. A wiring board having a surface, the first electrode pads disposed at a first pitch exposed from the first insulating layer closest to the first main surface, and closest to the second main surface A second insulating layer provided on a third insulating layer adjacent to the second insulating layer and exposed from an opening of the second insulating layer and disposed at a second pitch wider than the first pitch; An electrode pad; and a through hole provided with a conductor provided in the third insulating layer and electrically connecting the second electrode pad and the wiring layer covered by the third insulating layer. The diameter of the through hole on the second electrode pad side is the wiring layer side covered by the third insulating layer of the through hole. Greater than the diameter, the second insulating layer is a requirement that it comprises a reinforcing member.

  In another embodiment of the present wiring board, a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately stacked, and the second main surface and the opposite surface are the second main surface. A wiring board having a main surface, the first electrode pads disposed at a first pitch exposed from the first insulating layer closest to the first main surface, and the second electrode main surface A second insulating layer disposed on a third insulating layer adjacent to the second insulating layer and disposed at a second pitch that is wider than the first pitch and is exposed from the opening of the second insulating layer; And a through-hole in which a conductor provided in the third insulating layer and electrically connecting the second electrode pad and the wiring layer covered by the third insulating layer is formed. And the diameter of the through hole on the second electrode pad side is a wiring layer covered by the third insulating layer of the through hole Greater than the diameter, the third insulating layer is a requirement that it comprises a reinforcing member.

  Still another embodiment of the present wiring board is a wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked and have a first main surface and a second main surface opposite to the first main surface. A first electrode pad disposed at a first pitch exposed from the first insulating layer closest to the first main surface, and a second insulating layer closest to the second main surface. A second electrode pad provided on a third insulating layer and exposed from an opening of the second insulating layer and disposed at a second pitch wider than the first pitch; and A through hole provided in an insulating layer and formed with a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer; 2 is larger than the diameter of the wiring layer side covered by the third insulating layer of the through-hole, The edge layer is composed of a photosensitive insulating resin, the other insulating layers are composed of a non-photosensitive insulating resin having the same composition, and the third insulating layer is provided with a reinforcing member. To do.

  According to the disclosed technology, it is possible to provide a wiring board that can reduce warpage and can cope with higher density.

It is sectional drawing which illustrates the conventional wiring board. It is FIG. (1) which illustrates the manufacturing process of the conventional wiring board. It is FIG. (2) which illustrates the manufacturing process of the conventional wiring board. It is FIG. (The 3) which illustrates the manufacturing process of the conventional wiring board. It is sectional drawing which illustrates the wiring board which concerns on 1st Embodiment. It is sectional drawing which illustrates a glass cloth. It is a figure which illustrates a stack via structure. It is a figure which shows the example which forms an external connection terminal in a wiring board. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 9 is a diagram (No. 4) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 14 is a view (No. 7) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 8) for exemplifying the manufacturing process for the wiring board according to the first embodiment; It is sectional drawing which illustrates the wiring board which concerns on 2nd Embodiment. It is sectional drawing which expands and exemplifies the opening part vicinity of FIG. It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. FIG. 9 is a second diagram illustrating a manufacturing process of a wiring board according to the second embodiment; It is FIG. (The 3) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. 10 is a cross-sectional view illustrating a semiconductor package according to a third embodiment; FIG. It is the figure which showed the simulation result of the wiring board A typically. It is the figure which showed the simulation result of the wiring board B typically.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

<First Embodiment>
In the first embodiment, an example is shown in which the present invention is applied to a wiring board that becomes a semiconductor package by mounting a semiconductor chip.

[Structure of Wiring Board According to First Embodiment]
First, the structure of the wiring board according to the first embodiment will be described. FIG. 5 is a cross-sectional view illustrating the wiring board according to the first embodiment. Referring to FIG. 5, the wiring board 10 according to the first embodiment includes a first wiring layer 11, a first insulating layer 12, a second wiring layer 13, a second insulating layer 14, a third wiring layer 15, The third insulating layer 16, the fourth wiring layer 17, and the fourth insulating layer 18 are sequentially stacked.

  In the wiring substrate 10, the lower surface of the first insulating layer 12 (the surface opposite to the surface in contact with the second insulating layer 14) and the upper surface of the fourth insulating layer 18 (the surface opposite to the surface in contact with the third insulating layer 16). Any one of the surfaces) may be referred to as a first main surface and the other as a second main surface. For example, if the lower surface of the first insulating layer 12 is the first main surface of the wiring substrate 10, the insulating layer closest to the first main surface is the first insulating layer 12. For example, if the upper surface of the fourth insulating layer 18 is the second main surface of the wiring substrate 10, the insulating layer closest to the second main surface is the fourth insulating layer 18.

  In the wiring substrate 10, the first wiring layer 11 is formed in the lowest layer. The first wiring layer 11 includes a first layer 11a and a second layer 11b. As the first layer 11 a, for example, a gold (Au) film, a palladium (Pd) film, and a nickel (Ni) film are sequentially stacked in this order so that the gold (Au) film is exposed to the outside of the wiring substrate 10. A conductive layer can be used. As the first layer 11a, for example, a conductive layer in which a gold (Au) film and a nickel (Ni) film are sequentially laminated in this order so that the gold (Au) film is exposed to the outside of the wiring substrate 10 may be used. . As the second layer 11b, for example, a conductive layer including a copper (Cu) layer can be used. The thickness of the 1st wiring layer 11 can be about 10-20 micrometers, for example.

  A part of the first wiring layer 11 (first layer 11a) is exposed from the first insulating layer 12, and functions as an electrode pad electrically connected to a semiconductor chip or the like (not shown). Hereinafter, the first wiring layer 11 exposed from the first insulating layer 12 may be referred to as a first electrode pad 11, and the first electrode pad 11 side may be referred to as a semiconductor chip mounting side. The planar shape of the first electrode pad 11 is, for example, a circle, and the diameter thereof can be, for example, about 40 to 120 μm. The pitch of the 1st electrode pad 11 can be about 100-200 micrometers, for example.

  The first insulating layer 12 covers the upper surface (surface connected to the via wiring of the second wiring layer 13) and the side surface of the first wiring layer 11, and the lower surface (surface connected to the via wiring of the second wiring layer 13). It is formed so as to expose the opposite surface). As a material of the first insulating layer 12, for example, a non-photosensitive insulating resin mainly containing an epoxy resin can be used. As the non-photosensitive insulating resin that is the material of the first insulating layer 12, for example, a thermosetting resin can be used. The thickness of the 1st insulating layer 12 can be about 15-35 micrometers, for example.

The first insulating layer 12 contains a filler such as silica (SiO ₂ ). The filler content can be, for example, about 20 to 70 vol%. The filler preferably has a minimum particle size of 0.1 μm, a maximum particle size of 5 μm, and an average particle size of about 0.5 to 2 μm. By adjusting the filler content, the thermal expansion coefficient of the first insulating layer 12 can be adjusted (the thermal expansion coefficient decreases as the filler content increases). By adjusting the filler content and bringing the thermal expansion coefficient of the first insulating layer 12 closer to the thermal expansion coefficient (about 17 ppm / ° C.) of copper (Cu) constituting the second wiring layer 13 and the like, the wiring board 10 Can reduce the warpage. Unless otherwise specified, the thermal expansion coefficient in this specification indicates a value in the range of 25 to 150 ° C. Incidentally, the filler containing the first insulating layer 12, silica not limited to (SiO _2), it may be used such as alumina (hereinafter, also applies to other insulating layer).

  The second wiring layer 13 is formed on the first insulating layer 12. The second wiring layer 13 includes a via wiring filled in the first via hole 12x penetrating the first insulating layer 12 and exposing the upper surface of the first wiring layer 11, and a wiring pattern formed on the first insulating layer 12. It is comprised including. The first via hole 12x is opened to the second insulating layer 14 side, and the bottom surface is formed by the upper surface of the first wiring layer 11, and the opening area is larger than the area of the bottom surface. It is a recess. A via wiring is formed in the recess.

  The second wiring layer 13 is electrically connected to the first wiring layer 11 exposed at the bottom of the first via hole 12x. As a material of the second wiring layer 13, for example, copper (Cu) or the like can be used. The thickness of the wiring pattern constituting the second wiring layer 13 can be set to about 10 to 20 μm, for example.

  The second insulating layer 14 is formed on the first insulating layer 12 so as to cover the second wiring layer 13. As a material for the second insulating layer 14, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12. The second insulating layer 14 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12. This is for reducing the warpage generated in the wiring board 10. The thickness of the second insulating layer 14 can be about 15 to 35 μm, for example.

  The third wiring layer 15 is formed on the second insulating layer 14. The third wiring layer 15 includes a via wiring filled in the second via hole 14x penetrating the second insulating layer 14 and exposing the upper surface of the second wiring layer 13, and a wiring pattern formed on the second insulating layer 14 It is comprised including. The second via hole 14x is opened to the third insulating layer 16 side, and the bottom surface is formed by the upper surface of the second wiring layer 13, and has a truncated cone shape in which the area of the opening is larger than the area of the bottom surface. It is a recess. A via wiring is formed in the recess.

  The third wiring layer 15 is electrically connected to the second wiring layer 13 exposed at the bottom of the second via hole 14x. As a material of the third wiring layer 15, for example, copper (Cu) can be used. The thickness of the wiring pattern constituting the third wiring layer 15 can be about 10 to 20 μm, for example.

  The third insulating layer 16 is formed on the second insulating layer 14 so as to cover the third wiring layer 15. The third insulating layer 16 is obtained by impregnating a glass cloth 19 with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin. As the non-photosensitive insulating resin contained in the third insulating layer 16, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12 and the second insulating layer 14. The third insulating layer 16 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12 and the second insulating layer 14. This is for reducing the warpage generated in the wiring board 10. The thickness of the third insulating layer 16 can be about 25 to 75 μm, for example.

  As shown in FIG. 6, the glass cloth 19 has a form in which glass fiber bundles 19 a arranged in parallel in the X direction and glass fiber bundles 19 b arranged in parallel in the Y direction are plain woven in a lattice shape. The glass cloth 19 is a typical example of a reinforcing member according to the present invention. The glass fiber bundles 19a and 19b are formed by bundling a plurality of glass fibers each having a thickness of, for example, about several μm to have a width of, for example, about several hundred μm. The glass fiber bundles 19a and 19b can each have a thickness of about 10 to 15 μm.

  The fiber bundle constituting the reinforcing member such as the glass cloth 19 is not limited to the glass fiber bundle, and a carbon fiber bundle, a polyester fiber bundle, a tetron fiber bundle, a nylon fiber bundle, an aramid fiber bundle, or the like may be used. Absent. Further, the weaving method of the fiber bundle is not limited to plain weave, and may be satin weave or twill weave. Moreover, you may use a nonwoven fabric other than a woven fabric.

  The reason why the glass cloth 19 is provided only on the third insulating layer 16 is as follows. That is, generally, the wiring layer used as an electrode pad (in this embodiment, the fourth wiring layer 17) has a lower copper ratio than other wiring layers. Therefore, the wiring board is likely to warp due to the difference in the remaining copper ratio. Therefore, by providing the glass cloth 19 in the third insulating layer 16 adjacent to the fourth wiring layer 17, the same effect as when the remaining copper ratio of the fourth wiring layer 17 is increased can be obtained. This is because the generated warp can be reduced. Here, the remaining copper ratio is the ratio of the area of the metal layer forming the wiring layer to the area on a certain insulating layer. In the case of this embodiment, copper is assumed as the metal layer and referred to as the remaining copper ratio, but the metal layer may be other than copper.

  Since the design rule of the wiring layer is stricter on the semiconductor chip mounting side than on the external connection terminal side, it is not preferable to provide the glass cloth 19 on the insulating layer near the semiconductor chip mounting side. This is because the via hole in the insulating layer provided with the glass cloth 19 has a large volume, which hinders higher density of the wiring pattern and narrower pitch of the electrode pads.

  The fourth wiring layer 17 is formed on the third insulating layer 16. The fourth wiring layer 17 includes a via wiring formed in the third via hole 16x that penetrates the third insulating layer 16 and exposes the upper surface of the third wiring layer 15, and a wiring pattern formed on the third insulating layer 16. It is comprised including. The third via hole 16x is opened to the fourth insulating layer 18 side, and the bottom surface is formed by the upper surface of the third wiring layer 15, and the opening area is larger than the area of the bottom surface. It is a recess. A via wiring is formed in the recess.

  The via wiring configuring the fourth wiring layer 17 is formed so as to cover the side wall of the third via hole 16x, and the concave portion 17x may be formed near the center. That is, the via wiring constituting the fourth wiring layer 17 may not completely fill the third via hole 16x.

  The fourth wiring layer 17 is electrically connected to the third wiring layer 15 exposed at the bottom of the third via hole 16x. As a material of the fourth wiring layer 17, for example, copper (Cu) or the like can be used. The thickness of the wiring pattern constituting the fourth wiring layer 17 can be set to, for example, about 10 to 20 μm.

  The reason why the recess 17x may be formed in the via wiring of the fourth wiring layer 17 will be described below. That is, the thickness of the third insulating layer 16 including the glass cloth 19 is thicker than the thickness of the other insulating layers not including the glass cloth. Thereby, the third via hole 16x formed in the third insulating layer 16 becomes deeper than the first via hole 12x formed in the first insulating layer 12 and the second via hole 14x formed in the second insulating layer 14, In addition, the diameter at the opening end (the diameter on the fourth insulating layer 18 side) also increases. That is, it is difficult to reduce the diameter of the third via hole 16x, and the volume is increased.

  It is technically or costly difficult to completely fill the entire third via hole 16x having such a large volume with the via wiring. Therefore, as shown in FIG. 5, the via wiring of the fourth wiring layer 17 is formed on the side wall of the third via hole 16x, but the third via hole 16x is not completely filled, and the fourth wiring layer 17 is formed. In some cases, a recess 17x is formed near the center of the via wiring.

  The fourth insulating layer 18 is formed on the third insulating layer 16 so as to cover the fourth wiring layer 17. As a material of the fourth insulating layer 18, a photosensitive insulating resin including an epoxy resin, an imide resin, or the like can be used. As the material of the fourth insulating layer 18, a non-photosensitive insulating resin mainly composed of an epoxy resin may be used as in the first insulating layer 12 and the like. The thickness of the fourth insulating layer 18 can be about 15 to 35 μm, for example.

  The fourth insulating layer 18 has an opening 18x, and a part of the fourth wiring layer 17 including the recess 17x is exposed at the bottom of the opening 18x. The fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x functions as an electrode pad that is electrically connected to a mounting substrate (not shown) such as a motherboard. If necessary, a metal layer or the like may be formed on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer).

  Further, when a metal layer or the like is formed on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x (on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x). Alternatively, an external connection terminal such as a solder ball or a lead pin may be formed on a metal layer or the like. The external connection terminal is a terminal for electrically connecting to a mounting board (not shown) such as a mother board. However, the fourth wiring layer 17 including the concave portion 17x exposed at the bottom of the opening 18x (the metal layer or the like in the case where a metal layer or the like is formed on the fourth wiring layer 17 including the concave portion 17x) itself, It may be an external connection terminal.

  Hereinafter, the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x may be referred to as the second electrode pad 17, and the second electrode pad 17 side may be referred to as the external connection terminal side. is there. The planar shape of the second electrode pad 17 is, for example, a circle, and the diameter can be, for example, about 200 to 1000 μm. The pitch of the second electrode pads 17 is wider than the pitch of the first electrode pads 11 (for example, about 100 to 200 μm), and can be set to, for example, about 500 to 1200 μm.

  In the wiring substrate 10, the wiring pattern constituting the fourth wiring layer 17 is formed by being drawn out on the third insulating layer 16, and the wiring pattern drawn out on the third insulating layer 16 is opened in the fourth insulating layer 18. The second electrode pad 17 may be exposed through the portion 18x. That is, a portion other than the concave portion 17 x of the fourth wiring layer 17 may be used as the second electrode pad 17.

  FIG. 7 is a diagram illustrating a stacked via structure. FIG. 7A is a conventional wiring substrate 100 shown for comparison, and FIG. 7B is a diagram illustrating a wiring substrate 10A in which a stacked via structure is adopted for the wiring substrate 10. FIG.

  In the conventional wiring substrate 100 shown in FIG. 7A, no other via hole can be formed on the first via hole 120x (on the second insulating layer 140 side) in which the concave portion 130x is formed in the vicinity of the center portion. The degree of freedom in designing the three wiring layers 150 is limited, and the wiring density cannot be improved.

  On the other hand, in the wiring board 10A shown in FIG. 7B, another via hole is formed on the third via hole 16x (the fourth insulating layer 18 side) in which the recess 17x is formed in the vicinity of the center portion of the via wiring. For example, a stacked via structure can be adopted for the region B. Thereby, as compared with the case of FIG. 7A, the restriction on the via hole formation position is relaxed, and the degree of freedom in designing the third wiring layer 15 in the region C is improved. As a result, the wiring can be formed at a high density in the region D. Further, since it is not necessary to route the wiring in the region E, the wiring board can be reduced in size.

  Thus, in the wiring board according to the first embodiment, the third insulating layer 16 including the glass cloth 19 has a larger thickness than the other insulating layers. As a result, since the third via hole 16x formed in the third insulating layer 16 has a large volume, the via wiring constituting the fourth wiring layer 17 cannot completely fill the third via hole 16x, and is near the center portion. A recess 17x may be formed. However, since no other via hole is formed on the third via hole 16x (on the fourth insulating layer 18 side), the presence of the recess 17x does not hinder the so-called stacked via structure, and FIG. A stacked via structure such as the wiring board 10A shown in FIG. This makes it possible to increase the density and size of the wiring board.

  In other words, the wiring board 10 has a structure including the glass cloth 19 in the third insulating layer 16 so that the rigidity can be increased and the warpage can be reduced. Can also be supported. Further, even when the wiring substrate 10 becomes high temperature and exceeds the glass transition temperature of the insulating resin constituting each insulating layer, the occurrence of warpage is suppressed by the rigidity of the glass cloth 19 and the behavior in a high temperature environment is stabilized. .

  FIG. 8 is a diagram illustrating an example in which external connection terminals are formed on a wiring board. FIG. 8A is a view when solder balls 27 are formed on the second electrode pads 17 of the wiring board 10. FIG. 8B is a view when lead pins 29 are formed on the second electrode pads 17 of the wiring board 10 using solder 28. As shown in FIGS. 8A and 8B, even if the second electrode pad 17 has a recess 17x, the recess 17x is filled with solder, so that solder balls and lead pins can be joined. There will be no hindrance.

  As described above, even when an external connection terminal such as a solder ball or a lead pin is formed on the second electrode pad 17 (the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x), Therefore, the connection reliability between the second electrode pad 17 and the external connection terminal is not impaired.

[Method for Manufacturing Wiring Board According to First Embodiment]
Next, a method for manufacturing a wiring board according to the first embodiment will be described. 7 to 14 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

  First, in the step shown in FIG. 7, a support 21 is prepared. As the support 21, a silicon plate, a glass plate, a metal foil, or the like can be used. In the present embodiment, a copper foil is used as the support 21. This is because it can be used as a power feeding layer when performing electrolytic plating in the process shown in FIG. 9 to be described later, and can be easily removed by etching after the process shown in FIG. 14 to be described later. The thickness of the support body 21 can be about 35-100 micrometers, for example.

  Next, in a step shown in FIG. 8, a resist layer 22 having an opening 22 x corresponding to the first wiring layer 11 is formed on one surface of the support 21. Specifically, a liquid or paste resist made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is applied to one surface of the support 21. Alternatively, a film-like resist (for example, a dry film resist) made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is laminated on one surface of the support 21. Then, the opening 22x is formed by exposing and developing the coated or laminated resist. Thereby, the resist layer 22 having the opening 22x is formed. Note that a film-like resist in which the opening 22x is formed in advance may be laminated on one surface of the support 21.

  The opening 22x is formed at a position corresponding to the first wiring layer 11 formed in the process shown in FIG. 9 to be described later, and the arrangement pitch can be, for example, about 100 to 200 μm. The planar shape of the opening 22x is, for example, a circle, and the diameter can be, for example, about 40 to 120 μm.

  Next, in the process shown in FIG. 9, the first layer 11 a and the second layer 11 b are formed in the opening 22 x on one surface of the support 21 by an electrolytic plating method using the support 21 as a plating power feeding layer. The first wiring layer 11 to be formed is formed.

  The first layer 11a has a structure in which, for example, a gold (Au) film, a palladium (Pd) film, and a nickel (Ni) film are sequentially stacked in this order. Therefore, to form the first wiring layer 11, first, a gold (Au) film, a palladium (Pd) film, and a nickel (Ni) film are sequentially formed by an electrolytic plating method using the support 21 as a plating power feeding layer. The first layer 11a is formed by plating, and then the second layer 11b made of copper (Cu) or the like is formed on the first layer 11a by an electrolytic plating method using the support 21 as a plating power feeding layer. It ’s fine.

Next, in the step shown in FIG. 10, after removing the resist layer 22 shown in FIG. 9, the first insulating layer 12 is formed on one surface of the support 21 so as to cover the first wiring layer 11. As a material of the first insulating layer 12, for example, a non-photosensitive insulating resin mainly containing an epoxy resin can be used. The thickness of the 1st insulating layer 12 can be about 15-35 micrometers, for example. The first insulating layer 12 contains a filler such as silica (SiO ₂ ). The content and purpose of the filler are as described above.

  As a material of the first insulating layer 12, for example, when a non-photosensitive insulating resin mainly composed of a thermosetting film-like epoxy resin is used, the first wiring layer 11 is covered. A film-like first insulating layer 12 is laminated on one surface of the support 21. Then, while pressing the laminated first insulating layer 12, the first insulating layer 12 is heated to a curing temperature or higher and cured. In addition, by laminating the first insulating layer 12 in a vacuum atmosphere, voids can be prevented from being caught.

  When the material of the first insulating layer 12 is, for example, a non-photosensitive insulating resin mainly composed of a thermosetting liquid or pasty epoxy resin, the first wiring layer 11 is covered. Thus, the liquid or paste-like first insulating layer 12 is applied to one surface of the support 21 by, for example, a spin coating method. Then, the applied first insulating layer 12 is heated to the curing temperature or higher to be cured.

Next, in the step shown in FIG. 11, a first via hole 12 x that penetrates the first insulating layer 12 and exposes the upper surface of the first wiring layer 11 is formed in the first insulating layer 12. The first via hole 12x can be formed by a laser processing method using, for example, a CO ₂ laser. The first via hole 12x formed by the laser processing method is opened on the side where the second insulating layer 14 is formed, and the bottom surface is formed by the top surface of the first wiring layer 11, and the area of the opening is the bottom surface. It becomes a truncated-cone-shaped recessed part which becomes larger than an area. Other via holes are formed in the same shape when formed by laser processing. When the first via hole 12x is formed by a laser processing method, a desmear process is performed to remove the resin residue of the first insulating layer 12 attached to the upper surface of the first wiring layer 11 exposed at the bottom of the first via hole 12x. .

  Next, in the step shown in FIG. 12, the second wiring layer 13 is formed on the first insulating layer 12. The second wiring layer 13 includes a via wiring filled in the first via hole 12 x and a wiring pattern formed on the first insulating layer 12. The second wiring layer 13 is electrically connected to the first wiring layer 11 exposed at the bottom of the first via hole 12x. As a material of the second wiring layer 13, for example, copper (Cu) or the like can be used.

  Although the 2nd wiring layer 13 can be formed using various wiring formation methods, such as a semi-additive method and a subtractive method, the method of forming the 2nd wiring layer 13 using a semi-additive method as an example is shown below.

  First, copper (Cu) or the like is formed on the upper surface of the first wiring layer 11 exposed at the bottom of the first via hole 12x and the first insulating layer 12 including the side wall of the first via hole 12x by electroless plating or sputtering. A seed layer (not shown) is formed. Further, a resist layer (not shown) having an opening corresponding to the second wiring layer 13 is formed on the seed layer. Then, a wiring layer (not shown) made of copper (Cu) or the like is formed in the opening of the resist layer by an electrolytic plating method using the seed layer as a power feeding layer. Subsequently, after removing the resist layer, the seed layer not covered with the wiring layer is removed by etching using the wiring layer as a mask. As a result, the second wiring layer 13 including the via wiring filled in the first via hole 12 x and the wiring pattern formed on the first insulating layer 12 is formed on the first insulating layer 12. .

  Next, in the process shown in FIG. 13, by repeating the same process as described above, the second insulating layer 14, the third wiring layer 15, the third insulating layer 16, and the fourth wiring layer are formed on the first insulating layer 12. 17 is laminated. That is, after forming the second insulating layer 14 covering the second wiring layer 13 on the first insulating layer 12, the second via hole 14 x penetrating the second insulating layer 14 and exposing the upper surface of the second wiring layer 13 is formed. Form. The second via hole 14x may have a so-called stacked via structure in which the first via holes 12x are stacked and interconnected in the vertical direction as necessary. As a material for the second insulating layer 14, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12. The second insulating layer 14 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12. This is for reducing the warpage generated in the wiring board 10. The thickness of the second insulating layer 14 can be about 15 to 35 μm, for example.

  Further, a third wiring layer 15 connected to the second wiring layer 13 through the second via hole 14 x is formed on the second insulating layer 14. The third wiring layer 15 includes a via wiring that fills the second via hole 14 x and a wiring pattern formed on the second insulating layer 14. The third wiring layer 15 is electrically connected to the second wiring layer 13 exposed at the bottom of the second via hole 14x. As a material of the third wiring layer 15, for example, copper (Cu) can be used. The third wiring layer 15 is formed by, for example, a semi-additive method. The thickness of the wiring pattern constituting the third wiring layer 15 can be about 10 to 20 μm, for example.

  Further, a third wiring layer 15 is formed by laminating a resin film (prepreg) in which a glass cloth 19 is impregnated with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin, on the second insulating layer 14. A third insulating layer 16 to be covered is formed. Then, a third via hole 16x that penetrates the third insulating layer 16 and exposes the upper surface of the third wiring layer 15 is formed. If necessary, the third via hole 16x may have a so-called stacked via structure in which the second via holes 14x are stacked in the vertical direction and interconnected. The third insulating layer 16 is obtained by impregnating a glass cloth 19 with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin. As the non-photosensitive insulating resin contained in the third insulating layer 16, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12 and the second insulating layer 14. The third insulating layer 16 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12 and the second insulating layer 14. This is for reducing the warpage generated in the wiring board 10. The thickness of the third insulating layer 16 can be about 25 to 75 μm, for example.

  Further, a fourth wiring layer 17 connected to the third wiring layer 15 is formed on the third insulating layer 16 through the third via hole 16x. The fourth wiring layer 17 includes a via wiring formed in the third via hole 16 x and a wiring pattern formed on the third insulating layer 16. Since the volume of the third via hole 16x formed in the third insulating layer 16 including the glass cloth 19 is large, the third via hole 16x is not completely filled, and the vicinity of the central portion of the via wiring constituting the fourth wiring layer 17 In some cases, a recess 17x is formed. The fourth wiring layer 17 is electrically connected to the third wiring layer 15 exposed at the bottom of the third via hole 16x. As a material of the fourth wiring layer 17, for example, copper (Cu) or the like can be used. The fourth wiring layer 17 is formed by, for example, a semi-additive method. The thickness of the wiring pattern constituting the fourth wiring layer 17 can be set to, for example, about 10 to 20 μm.

  In this way, a predetermined buildup wiring layer is formed on one surface of the support 21. In the present embodiment, three build-up wiring layers (second wiring layer 13, third wiring layer 15, and fourth wiring layer 17) are formed, but n layers (n is an integer of 1 or more) are built. An up wiring layer may be formed.

  Next, in a step shown in FIG. 14, a fourth insulating layer 18 having an opening 18 x is formed on the third insulating layer 16. Specifically, for example, a photosensitive insulating resin containing a liquid or paste-like epoxy resin or imide resin is applied on the third insulating layer 16 so as to cover the fourth wiring layer 17. Then, the opening 18x is formed by exposing and developing the applied photosensitive insulating resin. Thereby, a part of the fourth wiring layer 17 including the recess 17 x is exposed at the bottom of the opening 18 x of the fourth insulating layer 18. The thickness of the fourth insulating layer 18 can be about 15 to 35 μm, for example. The fourth insulating layer 18 is formed using a non-photosensitive insulating resin or the like whose main component is an epoxy resin (non-photosensitive insulating resin having the same composition as the first insulating layer 12), and an opening portion. 18x may be formed by a laser processing method or the like.

  If necessary, a metal layer or the like may be formed on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x by, for example, an electroless plating method. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer).

  Next, after the step shown in FIG. 14, the support 21 shown in FIG. 14 is removed, thereby completing the wiring board 10 shown in FIG. The support 21 made of copper foil can be removed by wet etching using, for example, a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the outermost layer of the first wiring layer 11 exposed from the first insulating layer 12 is a gold (Au) film or the like, only the support 21 made of copper foil can be selectively etched. However, when the fourth wiring layer 17 is made of copper (Cu), the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x is prevented from being etched together with the support 21. Therefore, it is necessary to mask the fourth wiring layer 17.

  After the support 21 is removed, a metal layer or the like is formed on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x (on the fourth wiring layer 17 including the recess 17x exposed at the bottom of the opening 18x). In the case where is formed, external connection terminals such as solder balls and lead pins may be formed on a metal layer or the like. The external connection terminal is a terminal for electrically connecting to a mounting board (not shown) such as a mother board. However, the fourth wiring layer 17 including the concave portion 17x exposed at the bottom of the opening 18x (the metal layer or the like in the case where a metal layer or the like is formed on the fourth wiring layer 17 including the concave portion 17x) itself, It may be an external connection terminal. In addition, external connection terminals such as solder balls and lead pins may be formed before the support 21 is removed.

  Although FIGS. 7 to 14 show an example in which one wiring board 10 is formed on the support 21, a member to be a plurality of wiring boards 10 is manufactured on the support 21, and the individual pieces are separated. It does not matter as a process of obtaining a plurality of wiring boards 10 by making them.

  Thus, according to the first embodiment, the wiring layer and the insulating layer are sequentially stacked on the support from the semiconductor chip mounting side. At this time, a reinforcing member such as a glass cloth is provided on the insulating layer (third insulating layer) adjacent to the lower side of the uppermost insulating layer (fourth insulating layer) on the external connection terminal side. And a support body is removed and a wiring board is obtained. As a result, the rigidity of the third insulating layer provided with the reinforcing member can be increased, and the warping of the wiring board can be reduced.

  At this time, the third insulating layer including the reinforcing member is thicker than the other insulating layers. As a result, since the via hole formed in the third insulating layer has a large volume, the via wiring cannot completely fill the via hole, and a recess may be formed near the center. However, in the first embodiment, a wiring substrate is manufactured by sequentially laminating a wiring layer and an insulating layer from the semiconductor chip mounting side. As a result, no other via hole is formed on the via hole of the third insulating layer adjacent to the lower side of the uppermost insulating layer (fourth insulating layer) on the external connection terminal side. This does not hinder the adoption of the circuit board, and does not hinder the high density of the wiring board.

  That is, the wiring board according to the first embodiment can increase rigidity and reduce warpage by providing a reinforcing member such as a glass cloth in the third insulating layer, and adopts a so-called stacked via structure in a necessary portion. It can cope with high density.

  In addition, even when the wiring board becomes hot and exceeds the glass transition temperature of the insulating resin constituting each insulating layer, the occurrence of warpage is suppressed by the rigidity of the glass cloth, and the behavior in a high temperature environment is stabilized.

  Further, each insulating layer composed of a non-photosensitive insulating resin having the same composition contains substantially the same amount of filler having the same composition, thereby adjusting the thermal expansion coefficient of these insulating layers to substantially the same value. Therefore, the warp generated in the wiring board can be reduced. Furthermore, by making the thermal expansion coefficient of each insulating layer composed of the non-photosensitive insulating resin of the same composition close to the thermal expansion coefficient of the wiring layer, it is possible to further reduce the warp generated in the wiring board.

<Second Embodiment>
In the first embodiment, an example in which a reinforcing member such as a glass cloth is provided on an insulating layer (third insulating layer) adjacent to the lower side of the uppermost insulating layer (fourth insulating layer) on the external connection terminal side is shown. It was. The second embodiment shows an example in which a glass cloth is provided on the uppermost insulating layer (fourth insulating layer) on the external connection terminal side. Hereinafter, the description of the same components as those in the first embodiment will be omitted as much as possible, and the description will focus on the parts that are different from those in the first embodiment.

[Structure of Wiring Board According to Second Embodiment]
First, the structure of the wiring board according to the second embodiment will be described. FIG. 15 is a cross-sectional view illustrating a wiring board according to the second embodiment. Referring to FIG. 15, the wiring substrate 50 according to the second embodiment includes a third insulating layer 16, a fourth wiring layer 17, and a fourth insulating layer 18, and a third insulating layer 56 and a fourth wiring, respectively. The point that the layer 57 and the fourth insulating layer 58 are replaced is different from the wiring board 10 (see FIG. 5) according to the first embodiment.

  In the wiring board 50, unlike the third insulating layer 16 of the first embodiment, the third insulating layer 56 is not provided with a glass cloth. As a material for the third insulating layer 56, it is preferable to use a non-photosensitive insulating resin having the same composition as the first insulating layer 12 and the second insulating layer 14. The third insulating layer 56 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12 and the second insulating layer 14. This is for reducing the warpage generated in the wiring board 50. The thickness of the third insulating layer 56 is about the same as the thickness of the first insulating layer 12 and the second insulating layer 14, and can be about 15 to 35 μm, for example.

  The fourth wiring layer 57 is formed on the third insulating layer 56. The fourth wiring layer 57 penetrates the third insulating layer 56 and fills the third via hole 56x that exposes the upper surface of the third wiring layer 15, and a wiring pattern formed on the third insulating layer 56. It is comprised including. The third via hole 56x is opened to the fourth insulating layer 58 side, and the bottom surface is formed by the top surface of the third wiring layer 15, and the opening area is larger than the bottom surface area. It is a recess. A via wiring is formed in the recess.

  The fourth wiring layer 57 is electrically connected to the third wiring layer 15 exposed at the bottom of the third via hole 56x. As a material of the fourth wiring layer 57, for example, copper (Cu) or the like can be used. The thickness of the wiring pattern constituting the fourth wiring layer 57 can be set to, for example, about 10 to 20 μm. In addition, since the thickness of the 3rd insulating layer 56 in which the glass cloth is not provided is not specially thick (for example, about 15-35 micrometers), the recessed part 17x like 1st Embodiment is not formed but a 3rd via hole 56x can be completely filled (filled vias can be provided).

  “Completely filling” not only means that the surface of the via wiring filling the via hole is flat, but the cross section of the surface of the via wiring is recessed into a gentle circular arc having a depth of about several μm, for example, It also includes the case of protruding into a gentle arc of about several μm. In other words, “completely filling” includes a case where irregularities that do not hinder the formation of stacked vias are formed.

  The fourth insulating layer 58, which is the uppermost insulating layer on the external connection terminal side, is obtained by impregnating a glass cloth 19 with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin. As in the first embodiment, the fiber bundle constituting the reinforcing member such as the glass cloth 19 is not limited to the glass fiber bundle, and the carbon fiber bundle, the polyester fiber bundle, the tetron fiber bundle, and the nylon fiber bundle. An aramid fiber bundle or the like may be used. Further, the weaving method of the fiber bundle is not limited to plain weave, and may be satin weave or twill weave. Moreover, you may use a nonwoven fabric other than a woven fabric.

  As the non-photosensitive insulating resin contained in the fourth insulating layer 58, a non-photosensitive insulating resin having the same composition as the first insulating layer 12, the second insulating layer 14, and the third insulating layer 56 is used. Is preferred. The fourth insulating layer 58 preferably contains substantially the same amount of filler having the same composition as the filler contained in the first insulating layer 12, the second insulating layer 14, and the third insulating layer 56. This is for reducing the warpage generated in the wiring board 50. The thickness of the fourth insulating layer 58 can be, for example, about 25 to 75 μm.

  The fourth insulating layer 58 has an opening 58x, and the recess 57x of the fourth wiring layer 57 is exposed at the bottom of the opening 58x. The recess 57x functions as an electrode pad that is electrically connected to a mounting substrate (not shown) such as a mother board. A metal layer or the like may be formed on the recess 57x as necessary. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer). Note that, unlike the recess 17x of the first embodiment, the recess 57x is intentionally provided by blasting as described later.

  Furthermore, an external connection terminal such as a solder ball or a lead pin may be formed on the recess 57x (on the metal layer or the like when a metal layer or the like is formed on the recess 57x). The external connection terminal is a terminal for electrically connecting to a mounting board (not shown) such as a mother board. However, the recess 57x exposed at the bottom of the opening 58x (or a metal layer or the like when a metal layer or the like is formed on the recess 57x) itself may be used as the external connection terminal. Hereinafter, the recess 57x exposed at the bottom of the opening 58x may be referred to as a second electrode pad 57x, and the second electrode pad 57x side may be referred to as an external connection terminal side.

  16 is an enlarged cross-sectional view illustrating the vicinity of the opening in FIG. Referring to FIG. 16, the opening 58x extends from the fourth wiring layer 57 side toward the opening end, and the side wall has a concave R shape. In other words, the opening 58x has a curved side wall that protrudes or curves in the outer peripheral direction of the second electrode pad 57x, and the area of the portion that opens to the outer surface of the fourth insulating layer 58 is a portion of the bottom portion. Greater than area. The opening 58x can be formed in a hemispherical shape, for example. The planar shape of the opening 58x is, for example, a circle, and the diameter (diameter of the opening end) can be, for example, about 220 to 1100 μm.

  The concave portion 57x is widened from the bottom surface side toward the opening end, and the cross section of the side wall has a concave R shape. The outer edge of the recess 57x does not enter the lower part of the fourth insulating layer 58, and the outermost edge of the sidewall of the recess 57x coincides with the innermost edge of the sidewall of the opening 58x. The planar shape of the recess 57x is, for example, a circle, and the diameter thereof can be, for example, about 200 to 1000 μm. The pitch of the recesses 57x can be set to, for example, about 500 to 1200 μm. The depth of the deepest portion of the recess 57x with reference to the upper surface of the fourth wiring layer 57 can be set to, for example, about 0.5 to 4 μm.

  The planar shape of the recess 57x (second electrode pad) and the opening 58x (opening for the second electrode pad) is not limited to a substantially circular shape, and may be various shapes such as a substantially rectangular shape. For example, if the recess 57x and the opening 58x have a substantially rectangular planar shape, when a pin (socket pin) is inserted into the opening 58x, depending on the shape of the inserted pin (socket pin), By inserting the opening 58x in such a manner that the longitudinal direction of the pin corresponds to the longitudinal direction of the opening 58x, effects such as improved workability during insertion can be obtained.

  The reason why the cross section of the side wall of the opening 58x has a concave R shape is that, in the present embodiment, the opening 58x is formed by blasting, as will be described later. Further, when the opening 58x is formed, the upper surface of the fourth wiring layer 57 is continuously polished by blasting, so that a recess 57x continuous with the opening 58x is formed.

  Although the opening 58x can be formed by a laser processing method, it is not preferable in the following points. First, since it is necessary to form a relatively large opening in the uppermost insulating layer that is thicker than the other insulating layers, using the laser processing method requires several shots of irradiation, which increases the processing time. It is. Second, the end of the glass cloth cut by the laser protrudes from the side wall of the opening formed by the laser processing method. For example, an Au layer is formed on the wiring layer exposed at the bottom of the opening by an electroless plating method or the like. This is because, when a metal layer such as a metal layer is formed, there is a problem that the plating thickness of the metal layer below the protruding portion is reduced. Third, when the opening is formed by a laser processing method, a resin residue remains on the surface of the wiring layer exposed at the bottom of the opening. For this reason, the desmear process is performed, but the etching solution used for the desmear process dissolves a part of the wiring layer, and so-called haloing occurs. Further, the resin constituting the insulating layer is etched by the desmear treatment, and the end portion of the glass cloth protrudes more into the opening.

[Manufacturing Method of Wiring Board According to Second Embodiment]
Then, the manufacturing method of the wiring board based on 2nd Embodiment is demonstrated. 17 to 19 are diagrams illustrating a manufacturing process of the wiring board according to the second embodiment.

  First, in the step shown in FIG. 17, the same steps as in FIGS. 7 to 13 are performed, and the second insulating layer 14, the third wiring layer 15, the third insulating layer 56, and the like are formed on the first insulating layer 12. A fourth wiring layer 57 is laminated. Then, a fourth insulating layer 58 obtained by impregnating the glass cloth 19 with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin so as to cover the fourth wiring layer 57 on the third insulating layer 56. Form. The fourth insulating layer 58 is formed by laminating a resin film (prepreg) in which a glass cloth 19 is impregnated with, for example, a non-photosensitive insulating resin mainly composed of an epoxy resin on the third insulating layer 56, and pressurizing. And it can form by heating and hardening resin.

  In this way, a predetermined buildup wiring layer is formed on one surface of the support 21. In the present embodiment, the three build-up wiring layers (second wiring layer 13, third wiring layer 15, and fourth wiring layer 57) are formed, but the build of n layers (n is an integer of 1 or more) An up wiring layer may be formed.

  Next, in a step shown in FIG. 18, a resist layer 23 having an opening 23 x is formed on the fourth insulating layer 58. Specifically, a liquid or paste resist made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is applied on the fourth insulating layer 58. Alternatively, a film resist (eg, a dry film resist) made of a photosensitive resin composition containing, for example, an epoxy resin or an imide resin is laminated on the fourth insulating layer 58. Then, the opening 23x is formed by exposing and developing the coated or laminated resist. Thereby, the resist layer 23 having the opening 23x is formed. Note that a film-like resist in which the opening 23x is formed in advance may be laminated on the fourth insulating layer 58.

  The openings 23x are formed at positions corresponding to the openings 58x formed in the process shown in FIG. 19 described later, and the arrangement pitch can be set to, for example, about 500 to 1200 μm. The planar shape of the opening 23x is, for example, a circle, and the diameter can be, for example, about 220 to 1100 μm.

  The resist layer 23 functions as a mask for blasting in a process shown in FIG. 19 to be described later, but part of the surface of the resist layer 23 is also removed by blasting. Therefore, the resist layer 23 needs to be formed to a thickness that can maintain the function as a mask even if a part of the surface is shaved by blasting. The thickness of the resist layer 23 can be about 50 μm, for example.

  Next, in the step shown in FIG. 19, blasting is performed from the direction of the arrow using the resist layer 23 as a mask to form an opening 58 x in the fourth insulating layer 58 to expose the upper surface of the fourth wiring layer 57. Then, the blasting process is further continued to form a recess 57x in a portion exposed at the bottom of the opening 58x of the fourth wiring layer 57. As described above, after the upper surface of the fourth wiring layer 57 is exposed, the blast process is continued to form the recess 57x so that the residue of the material of the fourth insulating layer 58 does not remain in the opening 58x. it can.

  Note that if a pad having a diameter larger than the diameter of the bottom of the opening 58x (a receiving pad of the opening 58x) is formed on the fourth wiring layer 57 where the opening 58x is to be formed, this pad is blasted. Since the abrasive is received when the opening 58x is formed, the third insulating layer 56 can be prevented from being polished by the blast treatment, which is preferable.

  The opening 58x and the recess 57x formed by the blasting process have the shapes described with reference to FIG. As a result, a fourth insulating layer 58 having an opening 58x is formed, and the recess 57x of the fourth wiring layer 57 exposed at the bottom of the opening 58x is electrically connected to a mounting substrate (not shown) such as a motherboard. It functions as an electrode pad.

  Here, the blasting process is a process of mechanically adjusting the surface roughness of the object to be processed by spraying an abrasive on the object to be processed at a high pressure. The blast treatment includes air blast treatment, shot blast treatment, wet blast treatment, etc., but in particular, a polishing agent such as alumina abrasive grains and spherical silica abrasive grains is dispersed in a solvent such as water on the surface of the object to be treated. It is preferable to use a wet blast process in which collision is performed and a fine region is polished.

  This is because when wet blasting is used, polishing can be performed with extremely high density and less damage to an object to be processed compared to air blasting or shot blasting. Further, in the wet blasting process, the abrasive is dispersed in a solvent such as water, so that the abrasive is not scattered in the air as dust like the air blasting process or the shot blasting process.

  The particle size of an abrasive such as alumina abrasive grains or spherical silica abrasive grains used for wet blasting can be set to about 5 to 20 μm, for example. The concentration of the abrasive such as alumina abrasive grains and spherical silica abrasive grains dispersed in a solvent such as water can be set to about 14 vol%, for example. Moreover, the spraying pressure at the time of spraying the abrasive | polishing agent disperse | distributed to solvents, such as water, to the surface of a to-be-processed object can be about 0.25 MPa, for example.

  The surface roughness of the side wall of the opening 58x can be, for example, about Ra 150 to 600 nm. The surface roughness of the upper surface of the fourth insulating layer 58 excluding the opening 58x can be, for example, about Ra 150 nm or less. This is because the upper surface of the fourth insulating layer 58 is masked by the resist layer 23 during the blasting process, and the abrasive does not collide. Thus, only the side wall of the opening 58x is roughened by the blasting process, and the upper surface of the fourth insulating layer 58 excluding the opening 58x is not roughened. In the case where the opening 58x is formed by a laser processing method, the sidewall of the opening 58x and the upper surface of the fourth insulating layer 58 are etched by desmear processing, both of which are about Ra 500 nm.

  If necessary, a metal layer or the like may be formed on the recess 57x of the fourth wiring layer 57 exposed at the bottom of the opening 58x by, for example, an electroless plating method. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer). However, this metal layer or the like may be formed after the resist layer 23 is removed.

  In addition, when the surface roughness of the upper surface of the fourth insulating layer 58 is large (for example, about Ra 500 nm) as in the case where the opening 58x is formed by a laser processing method and desmear treatment is performed, a metal is used during electroless plating. There arises a problem that the layer easily adheres to the upper surface of the fourth insulating layer 58 (abnormal precipitation). When the opening 58x is formed by blasting, desmearing is not necessary, so that the surface roughness of the upper surface of the fourth insulating layer 58 can be reduced (for example, about Ra 150 nm or less), and such a problem is avoided. it can.

  Further, since the surface roughness of the side wall of the opening 58x is large (for example, about Ra 150 to 600 nm), for example, solder (solder balls, solder bumps, etc.) electrically connected to the fourth wiring layer 57 is formed in the opening 58x. In this case, the adhesion between the side wall of the opening 58x and the solder can be improved.

  Next, after the step shown in FIG. 19, the resist layer 23 shown in FIG. 19 is removed, and the support 21 shown in FIG. 19 is further removed, whereby the wiring substrate 50 shown in FIGS. 15 and 16 is completed. The support 21 made of copper foil can be removed by wet etching using, for example, a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the outermost layer of the first wiring layer 11 exposed from the first insulating layer 12 is a gold (Au) film or the like, only the support 21 made of copper foil can be selectively etched. However, when the fourth wiring layer 57 is made of copper (Cu), the recess 57x is masked to prevent the recess 57x exposed at the bottom of the opening 58x from being etched together with the support 21. There is a need.

  Although FIGS. 17 to 19 show an example in which one wiring board 50 is formed on the support body 21, a member to be a plurality of wiring boards 50 is manufactured on the support body 21, and the pieces are separated into individual pieces. It may be a process of obtaining a plurality of wiring boards 50. Also, external connection terminals such as solder balls and lead pins may be formed before or after the support 21 is removed.

  Thus, according to the second embodiment, the wiring substrate is manufactured by sequentially laminating the wiring layer and the insulating layer from the semiconductor chip mounting side. A reinforcing member such as a glass cloth is provided on the uppermost insulating layer (fourth insulating layer) on the external connection terminal side. Thereby, the rigidity of the fourth insulating layer provided with the reinforcing member can be increased, and the warp of the wiring board can be reduced.

  At this time, the thickness of the fourth insulating layer including the reinforcing member is thicker than the thickness of the other insulating layers, but no via hole is formed in the fourth insulating layer functioning as the solder resist layer. It is not a factor that hinders higher density.

  That is, the wiring board according to the second embodiment can increase rigidity and reduce warpage by providing a reinforcing member such as a glass cloth in the fourth insulating layer, and adopts a so-called stacked via structure in a necessary portion. It can cope with high density. A reinforcing member such as a glass cloth is provided in an insulating layer other than the uppermost insulating layer (fourth insulating layer) on the external connection terminal side or an insulating layer (third insulating layer) adjacent to the lower layer. However, the warpage of the wiring board can be reduced to some extent. However, when the wiring substrate is warped, the uppermost insulating layer (fourth insulating layer) on the external connection terminal side on the concave side or the insulating layer adjacent to the lower side (third insulating layer) is made of glass cloth. By providing such a reinforcing member, it is possible to most effectively counter the stress that warps the wiring board, and the effect of reducing the warping of the wiring board is increased. If a reinforcing member such as a glass cloth is provided in the insulating layer other than the uppermost insulating layer (fourth insulating layer) on the external connection terminal side or the insulating layer adjacent to the lower side (third insulating layer), the reinforcing member Since a recess is formed in the vicinity of the central portion of the via wiring formed in the via hole of the insulating layer provided with the member, a so-called stacked via structure cannot be adopted in that portion, and the high density of the wiring layer cannot be dealt with.

  In other words, in order to achieve both reduction of the warping and high density of the wiring board, a reinforcing member such as a glass cloth is used as the uppermost insulating layer (fourth insulating layer) on the external connection terminal side or the lower side thereof. Must be provided in an insulating layer (third insulating layer) adjacent to the first layer.

  In addition, even when the wiring board becomes hot and exceeds the glass transition temperature of the insulating resin constituting each insulating layer, the occurrence of warpage is suppressed by the rigidity of the glass cloth, and the behavior in a high temperature environment is stabilized.

  Also, a non-photosensitive insulating resin having the same composition is used as the material of all insulating layers constituting the wiring board including the uppermost insulating layer (fourth insulating layer), and all insulating layers have the same composition. By containing substantially the same amount, it is possible to adjust the thermal expansion coefficients of all the insulating layers to substantially the same value, and to reduce the warpage generated in the wiring board. Furthermore, by making the thermal expansion coefficients of all the insulating layers close to the thermal expansion coefficients of the wiring layers, it is possible to further reduce the warpage generated in the wiring board.

  In addition, since the opening of the uppermost insulating layer is formed by blasting, the opening widens from the wiring layer side covered with the insulating layer toward the opening end (upper surface of the insulating layer), and the cross section of the side wall has a concave R shape. It becomes. Therefore, if the area of the upper surface of the wiring layer exposed at the bottom of the opening is equal, the area of the opening on the upper surface of the insulating layer is a conventional wiring in which the cross section of the side wall has a linear shape close to perpendicular to the upper surface of the wiring layer. It becomes wider than the area of the opening of the substrate. As a result, compared to a conventional wiring board, it becomes easier to insert a so-called LGA socket pin into the opening, and the occurrence of poor insertion and poor contact can be reduced.

  Further, since the opening of the insulating layer is formed by blasting, desmearing is not required and haloing does not occur. As a result, it is possible to prevent the wiring layer in the vicinity of the opening and the insulating layer covering the wiring layer from being in a poor contact state.

  In addition, since the recess is formed by blasting in the uppermost wiring layer exposed at the bottom of the opening of the uppermost insulating layer, the bottom surface of the recess is the interface between the wiring layer near the opening and the insulating layer covering it. Are not in the same plane and are one step down. For this reason, it is difficult to apply a force directly from the pins of the so-called LGA socket to the interface between the wiring layer in the vicinity of the opening and the insulating layer covering it, so that the possibility of the interface peeling off can be reduced.

  In addition, since only the side wall of the opening can be roughened by blasting through a predetermined mask, for example, when solder or the like (solder ball or solder bump) is formed in the opening, the side wall of the opening due to the anchor effect. And the adhesion between the solder and the like. In addition, since the upper surface of the uppermost insulating layer covered with the mask during blasting is not roughened, for example, a metal layer or the like is formed on the wiring layer exposed at the bottom of the opening of the uppermost insulating layer by an electroless plating method or the like. When forming the metal layer, it is possible to prevent the metal layer from adhering (abnormally precipitated) to the upper surface (portion other than the opening) of the uppermost insulating layer.

<Third Embodiment>
The third embodiment shows an example of a semiconductor package in which a semiconductor chip is mounted on the wiring board 10 (see FIG. 5) according to the first embodiment. Hereinafter, the description of the same components as those in the first embodiment will be omitted as much as possible, and the description will focus on the parts that are different from those in the first embodiment.

  FIG. 20 is a cross-sectional view illustrating a semiconductor package according to the third embodiment. Referring to FIG. 20, the semiconductor package 70 includes the wiring substrate 10 shown in FIG. 5, a semiconductor chip 71, bumps 74, and underfill resin 75. In FIG. 20, the wiring board 10 is drawn upside down from FIG.

  The semiconductor chip 71 has a main body 72 and electrode pads 73. The main body 72 is obtained by forming a semiconductor integrated circuit (not shown) or the like on a thin semiconductor substrate (not shown) made of silicon or the like. An electrode pad 73 is formed on the main body 72. The electrode pad 73 is electrically connected to a semiconductor integrated circuit (not shown). As a material of the electrode pad 73, for example, Al or the like can be used.

  The bump 74 electrically connects the electrode pad 73 of the semiconductor chip 71 and the first wiring layer 11 (first layer 11 a) exposed from the first insulating layer 12 of the wiring substrate 10. The bump 74 is, for example, a solder bump. As a material for the solder bump, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The underfill resin 75 is filled between the semiconductor chip 71 and one surface of the wiring substrate 10.

  Thus, according to the third embodiment, it is possible to realize a semiconductor package in which a semiconductor chip is mounted on the wiring board according to the first embodiment. In other words, it is possible to realize a semiconductor package that is less warped and can cope with higher density. It goes without saying that a similar semiconductor package can be realized even if the wiring substrate (see FIG. 15) according to the second embodiment is used.

<Curve simulation>
In FIG. 5, a wiring board (wiring board) having a total of nine insulating layers and wiring layers, in which five insulating layers and five wiring layers are alternately stacked between the first insulating layer 12 and the second insulating layer 14. A warping simulation was performed on the substrate A). Further, a warping simulation was performed on a wiring board (referred to as wiring board B) having a configuration in which the glass cloth 19 is not provided on the third insulating layer 16 in the wiring board A.

  In wiring boards A and B, only the thermal expansion coefficient of the fourth insulating layer 18 is set to 60 ppm / ° C. to 65 ppm / ° C. (assuming a photosensitive insulating resin), and the thermal expansion coefficients of the other eight insulating layers are respectively set. 20 ppm / ° C. to 25 ppm / ° C. (assuming a non-photosensitive insulating resin with adjusted filler content). The planar shapes of the wiring boards A and B were each 45 mm × 45 mm rectangular, and the total thickness of the wiring boards A and B was 270 μm.

FIG. 21 is a diagram schematically showing a simulation result of the wiring board A. FIG. 22 is a diagram schematically showing a simulation result of the wiring board B. As shown in FIG. As shown in FIGS. 21 and 22, the wiring boards A and B both have a shape in which the first wiring layer 11 side serving as a semiconductor chip mounting surface is warped in a convex shape. Wiring board entire warp _{T 1} and _{T 3,} shown in Table 1 the warp _{T 2} and _{T 4} of the semiconductor chip mounting area.

表１に示すように、第３絶縁層１６にガラスクロス１９を設けた配線基板Ａは、第３絶縁層１６にガラスクロス１９を設けていない配線基板Ｂに比べて、配線基板全体の反り及び半導体チップ搭載領域の反りが大幅に低減されることが確認された。

As shown in Table 1, the wiring board A in which the glass cloth 19 is provided on the third insulating layer 16 is warped and the entire wiring board is compared with the wiring board B in which the glass cloth 19 is not provided on the third insulating layer 16. It was confirmed that the warpage of the semiconductor chip mounting area was greatly reduced.

  That is, the coreless substrate formed by sequentially laminating the wiring layer and the insulating layer on the support from the semiconductor chip mounting side is prone to warp so that the semiconductor chip mounting side is convex, but the third insulation By providing the glass cloth 19 on the layer 16, it was possible to increase the rigidity, and it was confirmed that the warpage of the entire wiring board and the warp of the semiconductor chip mounting region were significantly reduced.

  In the description of each of the above embodiments and simulations, “the uppermost insulating layer” and “the uppermost wiring layer” are referred to as “the outermost insulating layer” and “the outermost wiring layer”, respectively. Also good. That is, one of the outermost wiring layers in the wiring board is the uppermost wiring layer, and one of the outermost insulating layers is the uppermost insulating layer.

  The preferred embodiment has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and replacements are made to the above-described embodiment without departing from the scope described in the claims. Can be added.

  For example, each embodiment shows an example in which a coreless wiring substrate is manufactured by laminating a wiring layer and an insulating layer on one side (on one side) of a support by a build-up method, and finally removing the support. It was. However, a coreless wiring board may be manufactured by laminating a wiring layer and an insulating layer on both sides (one side and the other side) of the support by a build-up method, and finally removing the support. In this case, a wiring layer and an insulating layer are sequentially laminated on the one surface and the other surface of the support from the semiconductor chip mounting side, and finally the support is removed.

DESCRIPTION OF SYMBOLS 10, 50 Wiring board 11 1st wiring layer 11a 1st layer 11b 2nd layer 12 1st insulating layer 12x 1st via hole 13 2nd wiring layer 14 2nd insulating layer 14x 2nd via hole 15 3rd wiring layer 16, 56 1st 3 Insulating layer 16x, 56x Third via hole 17, 57 Fourth wiring layer 17x, 57x Recessed part 18, 58 Fourth insulating layer 18x, 22x, 23x, 58x Opening 19 Glass cloth 19a, 19b Glass fiber bundle 21 Support body 22, 23 Resist Layer 27 Solder Ball 28 Solder 29 Lead Pin 70 Semiconductor Package 71 Semiconductor Chip 72 Body 73 Electrode Pad 74 Bump 75 Underfill Resin

Claims (10)

A wiring board having a first main surface and a second main surface opposite to the first main surface, wherein a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately laminated. ,
A first electrode pad disposed at a first pitch exposed from a first insulating layer closest to the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer closest to the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The wiring board, wherein the second insulating layer includes a reinforcing member. A wiring board having a first main surface and a second main surface opposite to the first main surface, wherein a plurality of wiring layers and a plurality of insulating layers made of an insulating resin having the same composition are alternately laminated. ,
A first electrode pad disposed at a first pitch exposed from a first insulating layer closest to the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer closest to the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The wiring board, wherein the third insulating layer includes a reinforcing member. A wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked, and has a first main surface and a second main surface which is the opposite surface.
A first electrode pad disposed at a first pitch exposed from a first insulating layer closest to the first main surface;
A second width wider than the first pitch is provided on a third insulating layer adjacent to the second insulating layer closest to the second main surface and exposed from the opening of the second insulating layer. Second electrode pads arranged at a pitch of
A through hole provided in the third insulating layer, in which a conductor that electrically connects the second electrode pad and the wiring layer covered by the third insulating layer is formed;
The diameter of the through hole on the second electrode pad side is larger than the diameter of the through hole on the wiring layer side covered by the third insulating layer,
The second insulating layer is made of a photosensitive insulating resin, and the other insulating layers are made of a non-photosensitive insulating resin having the same composition,
The wiring board, wherein the third insulating layer includes a reinforcing member.   The through-hole in which the conductor which penetrates an insulating layer and electrically connects the wiring layers adjacent up and down was formed has the structure where it piled up and was mutually connected in the perpendicular direction. Wiring board.   The wiring board according to claim 4, wherein the through hole is filled with the conductor.   The wiring board according to claim 1, wherein the reinforcing member has a structure in which fiber bundles are woven in a lattice shape.   The wiring board according to any one of claims 1 to 6, wherein the insulating layer made of the insulating resin having the same composition contains a filler having the same composition. The cross section of the side wall of the opening is a concave R shape,
The wiring substrate according to claim 1, wherein a recess is provided in the second electrode pad portion exposed at the bottom of the opening. The cross section of the side wall of the recess is a concave R shape,
The wiring board according to claim 8, wherein an outermost edge portion of the side wall of the recess coincides with an innermost edge portion of the side wall of the opening.   The wiring board according to claim 8 or 9, wherein the surface roughness of the side wall of the opening is larger than the surface roughness of the upper surface of the uppermost insulating layer.

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