JP2008300482A - Printed wiring board and manufacturing method thereof, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a solder resist peel defect by reducing curvature of a thin-plate-thickness printed wiring board for semiconductor element mounting. <P>SOLUTION: The printed wiring board is manufactured through: a first stage of repeating a build-up process of overlaying a support substrate with a first insulating resin layer, forming a first conductor layer on the surface thereof, overlaying the first conductor layer with a second insulating resin layer, boring a via hole in the insulating resin layer, and forming a second conductor layer on the surface thereof, and thus forming an inner layer substrate having the outermost layer coated with a second insulating resin layer; a second stage of removing the support substrate to make the inner layer substrate independent; a third stage of repeating a build-up process of forming via holes in insulating resin layers of outer layers on both the surfaces of the inner layer substrate and forming a conductor layer on the surface, and thus forming an insulating resin layer and the conductor layer, and increasing the number of layers of the inner layer substrate; and a fourth stage of forming solder resist of the outer layers of the inner layer substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a printed wiring board having a thin plate thickness for mounting a semiconductor element, a manufacturing method thereof, and a semiconductor device in which a semiconductor element is installed on the printed wiring board.

  As a conventional method for manufacturing a thin printed wiring board for mounting semiconductor elements, in Patent Document 1, first, an external electrode pad such as nickel is formed on a metal support substrate, and then the support substrate and the external A first insulating resin layer covering the electrode pad is overlaid, then a first via hole pilot hole reaching the external electrode pad is formed in the first insulating resin layer, and then electrolysis using a metal support substrate as an electrode By copper plating, the first via hole pilot hole is filled with copper to form a via hole, and a first wiring pattern of a copper conductor layer is formed on the surface of the first insulating resin layer. Second, the first insulating resin layer and the second insulating resin layer covering the first wiring pattern are overlapped, and then a second via hole pilot hole reaching the external electrode pad is formed in the second insulating resin layer. Next, by electrolytic copper plating using a metal support substrate as an electrode, the second via hole pilot hole is filled with copper to form a via hole, and a second copper conductor layer is formed on the surface of the second insulating resin layer. A wiring pattern is formed. Third, the second insulating resin layer and the third insulating resin layer covering the second wiring pattern are overlapped, and then a third via hole pilot hole reaching the external electrode pad is formed in the third insulating resin layer. Next, by electrolytic copper plating using a metal support substrate as an electrode, the third via hole pilot hole is filled with copper to form a via hole, and a third copper conductor layer is formed on the surface of the third insulating resin layer. A wiring pattern is formed. Fourth, a solder resist that covers the third insulating resin layer and the third wiring pattern is formed. Fifth, a printed wiring board having a very thin total interlayer thickness is manufactured by removing the metal support substrate by etching.

The known literature is described below.
JP 2001-177010 A

  However, in the printed wiring board manufacturing method of Patent Document 1, since the entire conductor layer of the wiring pattern is electrically connected to the supporting substrate until the supporting substrate is removed at the end of the manufacturing process, the wiring pattern and the via hole There was a problem that the disconnection or short circuit could not be found by electrical inspection. That is, since the circuit of the wiring pattern becomes independent from the supporting substrate for the first time when the supporting substrate is removed, the defect of the wiring pattern and the via hole was next discovered by the electric inspection apparatus. Thus, the wiring pattern or via hole disconnection or short-circuit defect that occurred in the initial stage of the manufacturing process is discovered in the last process, and there has been a problem that the manufacturing yield of the printed wiring board is poor. Further, when a printed wiring board having a large number of layers is produced by this production method, since all the layers of the printed wiring board are formed on one side of the support substrate, there is a disadvantage that the production period is long.

  Further, in the printed wiring board manufacturing method of Patent Document 1, when printing a solder resist on both surfaces, after forming the solder resist on one side of the substrate, removing the support substrate, and forming the solder resist on the exposed surface, There was a problem that the printed wiring board warps due to unbalanced stress that forms a solder resist on one side. On the other hand, even when the solder resist is formed on both surfaces of the substrate after the metal support substrate is removed by etching, there is a problem that the printed wiring board is warped by the heat treatment applied when the solder resist is cured. As a result of diligent research, the cause of this problem is that the printed wiring board that is formed on one side has stress that is biased on one side, so unbalanced stress appears on the top and bottom surfaces due to heat treatment. Obtained warping knowledge.

  Furthermore, in the manufacturing method of Patent Document 1, when the external electrode pad that is in contact with the support substrate is exposed to the etching solution when the metal support substrate is removed by etching, the gap is formed between the insulating resin layers of the external electrode pad. There has been a problem that the etching liquid may invade to the position of the conductor layer electrically connected to the external electrode pad and the conductor surface may be corroded. Further, when the external electrode pad is formed by gold plating, if a solder resist is formed on the gold plating, there is a problem that the adhesion between the gold plating and the solder resist is deteriorated and the solder resist is peeled off.

  An object of the present invention is to solve these problems in a thin printed wiring board for mounting a semiconductor element, that is, to reduce the warpage of the thin printed wiring board, and to reduce the solder resist of the printed wiring board. It is an object to reduce peeling defects.

  In order to solve this problem, according to the present invention, a first insulating resin layer is stacked on a support substrate, a first conductor layer is formed on the surface of the first insulating resin layer, and the first conductor is formed. Build in which the insulating resin layer and the conductor layer are alternately stacked by the process of stacking the second insulating resin layer on the layer and the process of forming the via hole in the second insulating resin layer and forming the second conductor layer on the surface The first step of forming an inner layer substrate in which the outermost layer is coated with the second insulating resin layer on the surface of the support substrate is repeated, and then the support substrate is removed to remove the inner layer substrate. A second step of making the substrate independent, and then forming a via hole in the insulating resin layer of the outer layer on both sides of the inner layer substrate, forming a third conductor layer on the surface, and forming the third conductor layer on the surface Build-up process to overlap the third insulating resin layer and further form a conductor layer A method of manufacturing a printed wiring board comprising a third step of increasing the number of layers of the inner layer substrate repeatedly, and then a fourth step of forming a solder resist on the outer layer of the inner layer substrate. is there.

  Further, the present invention is a process of forming a first conductor layer on a surface on a support substrate having a release layer formed on the surface, and then superimposing a first insulating resin layer on the first conductor layer; A build-up process in which an insulating resin layer and a conductor layer are alternately stacked by repeatedly forming a via hole in the first insulating resin layer and forming a second conductor layer on the surface is repeated on the surface of the support substrate. A first step of forming an inner layer substrate having the second conductor layer, and then a second step of removing the support substrate and making the inner layer substrate independent, and then the inner layer. A process of superimposing a third insulating resin layer on the first conductor layer and the second conductor layer on the outer layers on both sides of the substrate, and then via holes in the third insulating resin layers on both sides of the inner layer substrate. And a third conductor layer is formed on the surface, and an insulating resin is formed on the third conductor layer. A third step of repeating the build-up process for forming a conductor layer and increasing the number of layers of the inner layer substrate, and then a fourth step of forming a solder resist on the outer layer of the inner layer substrate. A printed wiring board manufacturing method characterized by the above.

  The present invention is also the above-described printed wiring board manufacturing method, wherein the first insulating resin layer is formed using a prepreg resin containing a reinforcing material.

  The present invention is also a printed wiring board having a multi-layered conductor layer, having a reinforcing insulating resin layer in a first insulating resin layer as an inner layer, and a second layer above the first insulating resin layer. A third insulating resin layer having the same number of layers on both surfaces of the lower layer of the first insulating resin layer and the upper layer of the second insulating resin layer. A solder resist is provided on both sides of the outer layer of the insulating resin layer, and the via hole in the insulating resin layer equal to or higher than the second insulating resin layer is a frustoconical via hole having an upper diameter larger than the lower diameter. The via holes of the insulating resin layer below the first insulating resin layer are frustoconical via holes whose upper diameter is smaller than the lower diameter, and the thickness of each insulating resin layer between the conductor layers is equal. It is the printed wiring board characterized.

The present invention also includes an external electrode pad formed on the conductor layer in the opening of the solder resist, and a part of the external electrode pad is precoated with a first solder having a solid phase point of 235 ° C. or less. The above-mentioned printed wiring board, wherein the external connection terminal is soldered to the external electrode pad of a part with a second solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower.

  According to another aspect of the present invention, there is provided a semiconductor device in which a semiconductor element is bonded to an external electrode pad on a surface layer of a printed wiring board having a multi-layered conductor layer, wherein the printed wiring board includes an insulating resin layer containing a reinforcing material as a first inner layer. The insulating resin layer has a second insulating resin layer above the first insulating resin layer, and the same layer on both sides of the lower layer of the first insulating resin layer and the upper layer of the second insulating resin layer A plurality of third insulating resin layers, solder resists on both sides of the outer layers of the third insulating resin layers on both sides, and a via hole in the insulating resin layer that is higher than the second insulating resin layer on the upper side A reverse frustoconical via hole having a larger diameter than the lower diameter, and the via hole of the insulating resin layer below the first insulating resin layer is a frustoconical via hole whose upper diameter is smaller than the lower diameter. The thickness of each insulating resin layer between the conductor layers is equal. Which is a semiconductor device to be.

  Further, the present invention has a structure in which the external electrode pad is bonded to the semiconductor element with a first solder, and an external connection terminal is bonded to the second external electrode pad on the surface layer of the printed wiring board with a second solder. The solid-state point of the first solder is 235 ° C. or lower, and the solid-state point of the second solder is 240 ° C. or higher and 250 ° C. or lower.

  In the present invention, even when the thickness of each insulating resin layer of the inner layer substrate is thin, the support substrate is removed after forming the inner layer substrate having an appropriate thickness by stacking a plurality of those insulating resin layers, and thereafter, Since the inner layer substrate without the supporting substrate is handled, the inner layer substrate is easy to handle because the thickness is appropriate. Therefore, the inner layer substrate can be inspected with an electric inspection device, whereby defects in the wiring pattern and the via hole can be inspected, and defective products can be excluded at an early stage, thereby improving the yield of the printed wiring board. In addition, after forming an appropriate number of wiring patterns on the inner layer substrate and removing the support substrate, the insulating resin layer and the wiring pattern are built up on both sides to form two layers, so the subsequent steps Compared to the conventional method of building up on one side of the support substrate, there is an effect that the number of build-up steps can be halved and the manufacturing period can be shortened.

  The printed wiring board according to the present invention is vertically symmetrical with respect to the top and bottom of the substrate by forming a via hole and a fourth wiring pattern on the insulating resin layers on both sides of the substrate by overlapping the fourth insulating resin layer on both sides of the inner layer substrate. An insulating resin layer and a wiring pattern can be built up in a simple layer configuration. Thereby, although the printed wiring board is extremely thin, there is an effect that a printed wiring board of good quality can be obtained with few problems of warping of the printed wiring board even if the printed wiring board is heat-treated. In particular, there is an effect that the warp of the printed wiring board due to the heat treatment when printing the solder resist on both surfaces of the conventional substrate can be improved.

  Furthermore, since the present invention removes the support substrate from the inner substrate where the wiring pattern is covered with the insulating resin layers on both sides and the wiring pattern is not exposed, the conductor layer may be damaged by the treatment with the chemical solution when removing the support substrate. In addition, since the conductor layer of the inner substrate is not damaged in the subsequent manufacturing process, the manufacturing yield of the printed wiring board can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, as shown in FIGS. 1 to 4, the first insulating resin layer 2 is overlaid on the support substrate 1, and the first conductor including the wiring pattern on the surface of the first insulating resin layer 2. A layer 6 is formed, a second insulating resin layer 2-2 is superimposed on the first conductive layer 6, and a via hole 7- connected to the first conductive layer 6 in the second insulating resin layer 2-2. 2 and the process of forming the second conductor layer 6-2 by metal plating on the surface of the second insulating resin layer 2-2 is repeated on the support substrate 1 to form the second insulating resin layer 2-2. And the second conductor layer 6-2 are alternately manufactured, and then the substrate is supported on the supporting substrate 1 from the substrate.
A second step of manufacturing the inner layer substrate 8 from which the inner layer substrate 8 is removed, the third conductor layer 6-4 is formed by metal plating on both surfaces of the inner layer substrate 8, and the third insulating resin is formed on both surfaces of the inner layer substrate 8. Printed wiring having a third step of forming buildup layers on both surfaces of the inner substrate 8 by repeating the buildup process of layer 2-5 and a fourth step of forming solder resist 9 on the outermost layer. It is a manufacturing method of a board. Hereinafter, the manufacturing method of this embodiment is demonstrated in detail based on FIGS.

<First Embodiment>
(Process 1)
As shown in FIG. 1A, a metal plate is used as the support substrate 1, for example, a 250 μm copper plate is used as the support substrate 1, and the support substrate 1 is roughened by CZ processing or the like. The roughening treatment may be a sand blast treatment with an abrasive or a blackening treatment by oxidation-reduction treatment or a perhydrosulfuric acid based soft etching treatment.
(Process 2)
Next, as shown in FIG. 1B, the insulating resin layer 2 is thermocompression bonded to the support substrate 1 by roll lamination or lamination press. For example, an epoxy resin having a thickness of 30 μm is roll laminated.

(Modification 1)
As a modified example of the step 2, as the first insulating resin layer 2, a prepreg resin containing a reinforcing material such as glass fiber, glass flake, or filler is stacked on the support substrate 1, and a copper foil having a thickness of 12 μm is stacked thereon. The insulating resin layer 2 with a copper foil is bonded to the support substrate 1 by thermocompression bonding with a lamination press. As a material of the insulating resin layer 2, an epoxy resin material containing glass fiber, a bismaleimide-triazine resin (hereinafter referred to as BT resin) material containing glass fiber, a polyimide resin material containing glass fiber, and a PPE resin material containing glass fiber can be used. . By using the prepreg resin containing glass fiber for the insulating resin layer 2, it is possible to prevent the insulating resin layer 2 from being cracked and growing. In particular, since the thermal stress due to the subsequent process is applied to the insulating resin layer 2 many times, and the crack failure is likely to occur inside due to the thermal stress, the crack failure may be enlarged. By using it, there is an effect that the insulating resin layer 2 is strengthened and crack defects are prevented. And there exists an effect which can improve the reliability of the printed wiring board manufactured by reinforcing the insulating resin layer 2 which is easy to generate | occur | produce a defect in this way. Further, as the reinforcing material for the prepreg resin, an aramid nonwoven fabric, an aramid fiber, and a polyester fiber can be used in addition to the glass fiber. Further, as the reinforcing material of the insulating resin layer 2, a prepreg resin containing a reinforcing material reinforced with a flake-like reinforcing material or a filler, for example, a filler such as ceramics or barium sulfate, in addition to the fibrous reinforcing material can be used. .

  As the resin material of the insulating resin layer 2, an organic resin such as epoxy resin, BT resin, polyimide, PPE, phenol resin, PTFE resin, silicon resin, polybutadiene resin, polyester resin, melamine resin, urea resin, PPS resin, PPO resin, etc. Can be used. In addition, these resins can be used alone, or a combination of resins such as mixing a plurality of resins or preparing a compound can be used. Thus, when the insulating resin layer 2 is formed by laminating the prepreg and the copper foil on the support substrate 1, the entire surface of the insulating resin layer 2 is exposed by etching the copper foil with an etching solution such as ferric chloride aqueous solution. Let

(Process 3)
Next, the surface of the insulating resin layer 2 is roughened as necessary. In general, wet processes such as surface roughening with an oxidizing agent such as an aqueous solution of chromic acid or permanganate, and dry processes such as plasma treatment or ashing treatment are effective. Next, as shown in FIG. 1C, a plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm is formed on the entire surface of the insulating resin layer 2 by electroless copper plating.
(Process 4)
Next, as shown in FIG. 1D, for example, a dry film photosensitive resist is applied as a plating resist 4 to the substrate by roll lamination, and then exposed and developed as shown in FIG. The part 5 is opened, and a pattern of the plating resist 4 in which the plating base conductive layer 3 is exposed at the part is formed.
(Process 5)
Next, as shown in FIG. 1 (f), copper plating is applied to the surface of the plating base conductive layer 3 exposed at the wiring pattern portion 5 by electrolytic copper plating using the plating base conductive layer 3 as an electrode to a thickness of 15 μm. A first conductor layer on which the thick wiring pattern 6 is formed is formed.
(Step 6)
Next, the plating resist 4 is peeled off. Next, as shown in FIG. 2G, the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm remaining in the first conductor layer on the insulating resin layer 2 by a perhydrosulfuric acid-based flash etching process. Then, a first conductor layer in which the wiring pattern 6 is left on the insulating resin layer 2 is formed.

(Modification 2)
The method of forming the wiring pattern 6 in the above steps 3 to 6 is a semi-additive method, but the wiring pattern 6 of the first conductor layer can be similarly formed by the following manufacturing method in addition to this. That is, first, after the surface of the insulating resin layer 2 is roughened, the plating base conductive layer 3 is formed by electroless copper plating, and second, electrolytic copper plating is applied to the entire surface of the plating base conductive layer 3 by 12 μm. The first conductor layer added with the thickness of the first conductor layer is formed, and thirdly, an etching resist pattern is formed on the surface of the first conductor layer to etch the first conductor layer to form the wiring pattern 6. . Fourth, the etching resist is removed. The wiring pattern 6 can be formed also by the above subtractive construction method, and the structure of FIG.2 (g) can be manufactured.
(Step 7)
Next, the surface of the wiring pattern 6 of the first conductor layer is roughened to prepare for forming the second insulating resin layer 2-2. As the roughening treatment, blackening treatment by CZ treatment or oxidation-reduction treatment and perhydrosulfuric acid based soft etching treatment are performed.

  Next, as shown in FIG. 2 (h), the second insulating resin layer 2-2, which is thicker than the thickness of the insulating resin layer 2 by the thickness of the wiring pattern 6, is applied to the wiring pattern 6 and the insulating film by roll lamination or lamination press. Thermocompression bonding is performed on the surface of the resin layer 2. For example, a 45 μm thick epoxy resin is roll laminated. As a result, the thickness of the wiring pattern 6, that is, the second insulating resin layer 2-2 on the first conductor layer is made the same as that of the insulating resin layer 2.

  Here, in order to form the second insulating resin layer 2-2, a copper foil having a thickness of 12 μm is superposed on a prepreg resin containing a reinforcing material such as glass fiber, glass flake, or filler, and thermocompression-bonded by a lamination press. Thus, it is desirable to form the second insulating resin layer 2-2 with the copper foil. As the material of the second insulating resin layer 2-2, glass fiber-containing epoxy resin material, glass fiber-containing bismaleimide-triazine resin (hereinafter referred to as BT resin) material, glass fiber-containing polyimide resin material, glass fiber-containing PPE Resin material can be used. By using the prepreg resin with glass fiber, there is an effect that it is possible to prevent cracks from occurring in the insulating resin layer 2-2 and to prevent the cracks from growing in the insulating resin layer 2-2. In this way, when the second insulating resin layer 2-2 is formed by thermocompression bonding of the prepreg and the copper foil, the entire surface of the copper foil is etched. An aqueous ferric chloride solution or the like can be used as an etching solution.

(Process 8)
Next, as shown in FIG. 2I, a via hole prepared hole 7 is formed. The via hole prepared hole 7 is formed by a laser method or a photo etching method. When the via hole pilot hole 7 is formed in the second insulating resin layer 2-2 by the photoetching method, when a photo-curing type photosensitive resin is used for the insulating resin layer 2-2, the predetermined via hole pilot hole 7 is formed. A mask formed with a pattern for shielding the part is brought into close contact with the second insulating resin layer 2-2, exposed to ultraviolet rays, and unexposed portions are developed and removed. Alternatively, in the case of using a photodegradable photosensitive resin for the second insulating resin layer 2-2, a mask formed with a pattern that shields light other than the predetermined via hole pilot hole 7 portion is used as the second insulating resin layer 2-2. The via hole prepared hole 7 is formed by a photo-etching method in which the exposed portion is exposed to ultraviolet light and exposed to ultraviolet light, and the exposed portion is developed and removed.

  When the via hole pilot hole 7 is formed in the second insulating resin layer 2-2 with a laser beam, an ultraviolet laser beam such as a harmonic YAG laser or an excimer laser is used as the laser beam, or an infrared ray such as a carbon dioxide laser is used. Laser light is used. As described above, the wavelength range of the laser light is from the infrared light region to the ultraviolet light region. When the second insulating resin layer 2-2 is made of a thermosetting resin, it is desirable to form the via hole prepared hole 7 with a laser beam. Here, when the via hole pilot hole 7 is formed by laser light, the via hole pilot hole 7 becomes a funnel-shaped hole in which the diameter of the opening portion of the hole is larger than the diameter of the hole at the bottom of the hole.

  Since a thin resin film remains at the bottom of the via hole pilot hole 7 after the via hole pilot hole 7 is formed, the thin resin film is removed by a desmear process. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent such as chromic acid or a permanganate aqueous solution. Alternatively, it may be removed by sandblasting or plasma treatment with an abrasive.

After forming the via hole prepared hole 7 in the second insulating resin layer 2-2, the surface of the second insulating resin layer 2-2 is roughened as necessary. In general, when a thermosetting resin or thermoplastic resin is used, wet processes such as surface roughening with an oxidizing agent such as an aqueous solution of chromic acid or permanganate, or dry processes such as plasma treatment or ashing treatment are performed. The process is valid.
(Step 9)
Next, in the same manner as in step 3, the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm is formed by electroless copper plating on the entire wall surface of the via hole pilot hole 7 and the surface of the second insulating resin layer 2-2. (Not shown) is formed as the second conductor layer. Next, in the same manner as in step 4, a plating resist 4 (not shown), for example, a dry film photosensitive resist is attached to the substrate by roll lamination, and then exposed and developed to form a wiring pattern portion 5 (not shown). A plating resist 4 having an opening is formed.

(Process 10)
Next, electrolytic copper plating is performed using the plating base conductive layer 3 as an electrode, and the electrolytic copper plating layer is thickened to a thickness of 15 μm on the surface of the plating base conductive layer 3 exposed to the wiring pattern portion 5. A second conductor layer on which the wiring pattern 6-2 is formed is formed, and at the same time, a via hole 7-2 in which the via hole prepared hole 7 is filled with an electrolytic copper plating layer is embedded in the second insulating resin layer 2-2. . At this time, in order to form the via hole 7-2, it is desirable to use an electrolytic copper plating bath containing a smoothing agent as the following composition as the electrolytic copper plating bath.
(Electrolytic copper plating bath composition)
Copper sulfate: 200-250g / L
Sulfuric acid: 30-50g / L
Chlorine: 30-60ppm
Polyethylene glycol (PEG): 0.5-1g / L
Bis (3-sulfopropyl) disulfide (SPS): 1 to 10 mg / L
Smoothing agent: 1-10 mg / L of Janus Green B (JGB).

(Step 11)
Next, the plating resist 4 is peeled off. Next, the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm remaining on the second conductor layer on the second insulating resin layer 2-2 is removed, and the wiring pattern 6-2 having a thickness of 15 μm is removed. Most of the remaining perhydrosulfuric acid-based flash etching is performed, and as shown in FIG. 2 (k), the second insulating resin layer 2-2 has a via hole 7-2, and the second conductor layer is formed thereon. A structure having the wiring pattern 6-2 is formed. The via hole prepared hole 7 formed by using the laser beam in this process is a funnel-shaped hole in which the diameter of the opening portion of the hole is larger than the diameter of the hole at the bottom of the hole. The diameter of the via hole 7-2 thus formed is formed in a truncated cone shape in which the diameter on the support substrate 1 side is smaller than the diameter on the side far from the support substrate 1.

(Step 12)
Next, by repeating steps 7 to 11 as described below, the conductor layer of the wiring pattern is formed in multiple layers. First, an insulating resin layer 2-3 is formed by the process of step 7, as shown in FIG. Next, as shown in FIG. 3 (n), via holes 7-3 embedded in the conductive layer of the wiring pattern 6-3 and the insulating resin layer 2-3 are formed by the processing from step 8 to step 11. In this way, the three conductor layers of the wiring patterns 6, 6-2, and 6-3 can be formed by the processing from step 3 to step 12. The diameter of the via hole 7-3 formed in the via hole pilot hole 7 formed using the laser beam in this step is formed in a truncated cone shape in which the diameter on the support substrate 1 side is smaller than the diameter on the side far from the support substrate 1. The
(Step 13)
Next, as shown in FIG. 3 (p), an insulating resin layer 2-4 is formed by the process of step 7.

(Step 14)
Next, as shown in FIG. 3 (q), the copper support substrate 1 is removed by etching to produce an inner substrate 8 having both surfaces covered with the insulating resin layer 2 and the insulating resin layer 2-4. As an etching solution used at this time, for example, an alkaline etching solution mainly containing ammonia can be used. Alternatively, a ferric chloride aqueous solution or a cupric chloride aqueous solution may be used. Since this inner layer substrate 8 has an appropriate thickness obtained by stacking a plurality of these insulating resin layers even when the thickness of each insulating resin layer 2, 2-2, 2-3, 2-4 is thin, The inner layer substrate 8 is easy to handle, and thus there is an effect that it is easy to manufacture a printed wiring board. In addition, since the conductor layers on both sides of the inner layer substrate 8 are protected by the insulating resin layers 2 and 2-4 and are not exposed to the outside, there is an effect that the conductor layer is not damaged by the handling when removing the support substrate 1 from the inner layer substrate 8. In addition, there is an effect that the conductor layer is not damaged even in handling in the subsequent manufacturing process, thereby improving the manufacturing yield of the printed wiring board.

(Modification 3)
The above manufacturing process produces the inner layer substrate 8 in which the three conductor layers of the wiring patterns 6, 6-2, 6-3 are formed on the inner layer substrate 8 and both surfaces thereof are covered with the insulating resin layers 2, 2-4. However, as the inner layer substrate 8 other than this, the two conductive layers of the wiring patterns 6 and 6-2 are formed, the three insulating resin layers 2, 2-2 and 2-3 are formed, It is also possible to manufacture the inner layer substrate 8 in which the surface layers on both surfaces of the inner layer substrate 8 are the insulating resin layers 2 and 2-3. Furthermore, it is also possible to manufacture the inner substrate 8 in which one conductor layer of the wiring pattern 6 is covered with the insulating resin layers 2 and 2-2.

(Modification 4)
Moreover, although the metal support substrate 1 was used from the process 1 to the process 14, the support substrate 1 is not limited to a metal, The insulating resin substrate containing glass fibers, such as a glass epoxy resin substrate which formed the peeling layer on the surface, is used. It is also possible to use the support substrate 1 and remove the support substrate 1 by peeling the inner layer substrate 8 from the support substrate 1 in Step 14.

(Step 15)
Next, via hole pilot holes 7 are formed in the insulating resin layer 2-4 and the insulating resin layer 2 of the inner substrate 8 by laser light in the same manner as in step 8. That is, here, via hole prepared holes 7 are formed not only on one side of the substrate but also on both sides of the substrate. In this step, a funnel shape is formed in which the inner diameter of the opening on the outer side of the inner layer substrate 8 is larger than the inner diameter of the bottom surface on the center side of the inner layer substrate 8 of the via hole pilot hole 7 formed using laser light.

(Step 16)
Next, as shown in FIG. 3 (r), in the same manner as in Step 9 to Step 11, metal plating is performed not only on one side of the substrate but also on both sides of the substrate. That is, by metal plating on both surfaces, a wiring pattern 6-4 of the third conductor layer formed on the surface of the insulating resin layer 2-4 and a via hole 7-4 embedded in the insulating resin layer 2-4 are formed. In addition, a wiring pattern 6-1 overlaid on the insulating resin layer 2 and a via hole 7-1 embedded in the insulating resin layer 2 are formed. In this process, the via holes 7-4 and 7-1 in which the via hole prepared holes 7 previously formed by laser light are filled with metal plating are outside the inner layer substrate 8 with respect to the diameter of the bottom portion on the center side of the inner layer substrate 8. It is formed in a truncated cone shape with a large diameter at the bottom.

(Step 17)
The inner layer substrate 8 shown in FIG. 3 (r) has a thickness of about 200 μm and an appropriate thickness for inspecting with an electric inspection apparatus, so that there is an effect that handling at the time of electric inspection is easy. Therefore, this inner layer substrate 8 is installed in an electrical inspection device, and the continuity between the wiring patterns exposed in the via hole pilot holes 7 on both surfaces of the inner layer substrate 8 is inspected. Thereby, the defect of the via hole connecting all the wiring patterns of the inner layer substrate 8 and the conductor layer is detected, and the defective inner layer substrate 8 is excluded, and the subsequent manufacturing process proceeds. Thus, it is possible to proceed with the manufacturing process while sufficiently inspecting the defects in the electrical connection of the wiring pattern and excluding the defects, and the production yield of the printed wiring board can be improved.

(Modification 5)
The processes so far can be modified as follows. That is, in step 1, an insulating resin substrate containing glass fibers such as a glass epoxy resin substrate to which a release layer is bonded is used as the support substrate 1, and then the support substrate is processed in the same manner as in steps 3 to 6. An electrode pad for electrical inspection and a wiring pattern 6 are formed on the surface of 1. Next, an insulating resin layer 2-2 is formed on the support substrate 1 in the same manner as in step 7. In this modified example 5, it is particularly desirable that the insulating resin layer 2-2 be formed of a prepreg containing a reinforcing material such as glass fiber, flakes, or filler. Since the insulating resin layer 2-2 is an insulating resin layer that is first laminated on the surface of the support substrate 1 in the modified example 5, the insulating resin layer 2-2 is formed by a prepreg with a reinforcing material so that the insulating resin layer 2-2 is formed in a later process. There is an effect that it can be strengthened so as not to deteriorate due to heat treatment applied by the manufacturing process. Next, Step 8 to Step 12 are performed to form the wiring pattern 6-3. Next, it is possible to manufacture the inner substrate 8 with the support substrate 1 peeled off and removed in step 14 to expose the electrode pads and the wiring pattern for electrical inspection on the lower surface and the wiring pattern 6-3 on the upper surface. It is. Next, in step 17, an electrical inspection of the inner layer substrate is performed.

(Step 18)
Next, as shown in FIG. 3S, third insulating resin layers 2-5 (upper surface) and 2-6 (lower surface) are formed on both surfaces of the substrate in the same manner as in step 7. At this time, the thickness of the third insulating resin layer on the conductor layer is formed to be the same as the thickness of the first insulating resin layer 2.

(Step 19)
Thereafter, until the required number of layers is obtained, the process 15 to the process 16 are repeated following the process 18 to insulate the via hole 7-5 embedded in the insulating resin layer 2-5 as shown in FIG. Conductor layer wiring pattern 6-5 formed on the surface of resin layer 2-5, and via hole 7-6 embedded in insulating resin layer 2-6 and conductor formed on the surface of insulating resin layer 2-6 A layer wiring pattern 6-6 is formed. In the via holes 7-5 and 7-6 formed in the via hole pilot hole 7 formed by using laser light in this step, the diameter of the bottom portion outside the inner layer substrate 8 is larger than the diameter of the bottom portion on the center side of the inner layer substrate 8. It is formed in a large truncated cone shape. The outermost insulating resin layers 2-5 and 2-6 of this substrate are preferably formed of a prepreg containing a reinforcing material. Insulating resin layers 2-5 and 2-6 are susceptible to thermal mechanical stress at the junction with the mother substrate when the printed wiring board manufactured by this manufacturing method is mounted on the mother substrate. Forming the insulating resin layer with a prepreg containing a reinforcing material has an effect of extending the durability and life of the printed wiring board after the printed wiring board is mounted on the mother board. In addition, after performing the build-up process which forms a wiring pattern on both surfaces of the board | substrate by the previous process 15 to the process 17, you may progress to the process of the following process 20 immediately without passing through the process 18 and the process 19.

(Step 20)
Next, as shown in FIG. 4 (u), solder resists 9 are formed on both sides of the substrate. The solder resist 9 is formed by performing, for example, a CZ process on the roughening process of the wiring pattern 6-4 and the wiring pattern 6-5 as a pre-process. Next, the photosensitive liquid solder resist 9 is applied to a thickness of about 20 μm by spray coating, roll coating, curtain coating, or screen method and dried, or the photosensitive dry film / solder resist 9 is applied by roll lamination. Next, as shown in FIG. 4 (v), the solder resist 9 is exposed and developed to form pad openings 10 in the solder resist 9 for forming external electrodes. Next, the solder resist 9 is cured by heating.

(Step 21)
Next, an electroless nickel plating layer is formed to 3 μm or more on the wiring patterns 6-5 and 6-6 exposed in the pad opening 10 of the solder resist 9, and an electroless gold plating layer is formed to 0.03 μm or more thereon. Then, external electrode pads 10-1 and 10-2 are formed. The electroless gold plating layers of the external electrode pads 10-1 and 10-2 may be 1 μm or more. Further, the external electrode pad 10-1 has a solid phase point such as Sn—Ag—Cu solder having a solid phase point of about 217 to 227 ° C., Sn—Bi—Ag solder or SnPb solder having a solid phase point of about 213 ° C. Is pre-coated with solder at 235 ° C. or lower. As this precoat solder, it is desirable to select and use a solder having a solid phase point of 230 ° C. or lower. Further, the external electrode pads 10-1 and 10-2 are formed by forming an electrolytic nickel plating layer of 3 μm or more instead of electroless nickel plating, and forming an external electrode pad of 0.5 μm or more on the electrolytic gold plating layer thereon. It may be formed. Alternatively, instead of the metal plating layer, an aqueous organic rust preventive film made of a water-soluble preflux made of an imidazole compound or a benzimidazole compound can be formed on the external electrode pads 10-1 and 10-2.
(Step 22)
Next, by processing this substrate with a dicer or the like, a plurality of printed wiring boards separated into individual pieces are obtained from one substrate.

  By the above manufacturing method, a printed wiring board in which the insulating resin layers between the conductor layers are formed to the same thickness can be obtained. Here, since the gold plating or the like of the external electrode pads 10-1 and 10-2 is formed after the solder resist is formed, printing with good quality with no peeling of the solder resist at the portions of the external electrode pads 10-1 and 10-2. There is an effect that a wiring board is obtained. Moreover, as the best embodiment, each insulating resin layer 2, 2-2, 2-3, 2-4, 2-5, and 2-6 are formed of an insulating resin layer containing glass fibers. And this printed wiring board builds up the insulating resin layer and the wiring pattern in a vertically symmetrical layer configuration by forming via holes and wiring patterns in the insulating resin layers on both sides of the inner layer substrate 8, There is an effect that stress is not biased and left on one side of the substrate. Therefore, even though the printed wiring board is very thin, heat stress such as heat treatment when solder resist is printed on this printed wiring board or heat treatment such as heat treatment when soldering in the subsequent process is applied. Also, there is an effect that a printed wiring board of good quality can be obtained with few problems of warping the printed wiring board.

Further, before the step 14 of removing the supporting substrate 1, the insulating resin layers 2-2 and 2-
The via hole formed by being embedded in 3 is formed in a truncated conical shape with the upper base diameter larger than the lower base diameter. The via hole formed in the insulating resin layer 2 after the support substrate 1 is removed is formed in a vertically symmetric orientation with respect to the center of the printed wiring board, and the lower bottom facing the center side of the frustoconical printed wiring board of the via hole The diameter of the upper base facing the outside of the printed wiring board is formed larger than the diameter of the printed wiring board. Therefore, the via hole embedded in the insulating resin layers 2-2, 2-3, 2-4, and 2-5 on the printed wiring board has the upper diameter opposite to the lower diameter. The via hole embedded in the two insulating layers of the insulating resin layers 2 and 2-6 is formed in a truncated cone shape whose upper diameter is smaller than the lower diameter. As described above, the printed wiring board manufactured in the present embodiment has a via hole having an inverted frustoconical shape in which the upper insulating resin layer has a larger upper diameter than the lower diameter. The via hole included in the insulating resin layer is a via hole having a truncated cone shape that is upside down, and the number of layers of the upper insulating resin layer is larger than the number of lower insulating resin layers. Is manufactured. This printed wiring board is a part of the inner layer substrate formed by building up on the support substrate 1 by observing the cross section and confirming the vertical direction of the via hole in each layer when analyzing the defect of the printed wiring board. And an outer layer formed by building up on both sides of the outer surface can be easily distinguished, and there is an effect that defects caused by different manufacturing processes can be easily distinguished and analyzed.

(Step 23)
Next, as shown in FIG. 5 (w), a flip chip connection process is performed in which the precoat solder of the external electrode pad 10-1 is heated and remelted and soldered to the bumps 12 of the semiconductor element 11. Next, the sealing resin 13 is poured into the space between the semiconductor element 11 and the insulating resin layer 2-5 and cured to mount the semiconductor element 11 on the insulating resin layer 2-5 and the solder resist 9 on the upper surface thereof. .
(Step 24)
Next, as shown in FIG. 5 (x), a solder ball external connection terminal 14 is mounted on the external electrode pad 10-2 to manufacture a semiconductor device having a ball grid array structure.

(Modification 6)
As a modification of the semiconductor device, a metal pin terminal is used as the external connection terminal 14 to be attached to the external electrode pad 10-2, and the pin terminal is attached to the external electrode pad 10-2 to form a pin grid array structure. You can also. As the pin terminal used for the external connection terminal 14, for example, a pin terminal having a structure in which the surface of a copper alloy base material of the pin terminal is nickel-plated and gold-plated thereon is used. In addition, a pin terminal having a structure in which a portion of the pin terminal attached to the external electrode pad 10-2 is a planar terminal and a pin is raised on the planar terminal is used. The soldering of the pin terminal is performed in step 23, before the semiconductor element 11 is placed on the insulating resin layer 2-5, the planar terminal of the pin terminal has a solidus point of 240 ° C. or higher and 250 ° C. or lower. The external electrode pad 10-2 is soldered with solder. Examples of solder that satisfies this condition include Sn-5Sb solder (solid phase point is 240 ° C.), Sn—Sb—Pb solder, and the like. When the solid phase point of the solder for soldering the pin terminal exceeds 250 ° C., there is a problem that the soldering temperature deteriorates the insulating resin layer. When the eleven bumps 12 are soldered to the external electrode pads 10-1 of the printed wiring board, there arises a problem that the joint portion of the pin terminal is detached or deteriorated. As described above, the external connection terminal 14 is soldered to the external electrode pad 10-2 with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower, so that the semiconductor element 11 and other electrons are connected to the external electrode pad 10-1. There is an effect that the joint portion of the external connection terminal can withstand the heat treatment of the printed wiring board when soldering the component.

Further, when the bumps 12 of the semiconductor element 11 are soldered to the external electrode pads 10-1, the solder having a solid phase point of 235 ° C. or lower is remelted with the solder pre-coated in step 21. That is, in the previous step 21, the external electrode pad 10-1 and the external electrode pad 10-2 are pre-coated with solder corresponding to the components to be soldered to each other in advance. That is, in step 21, the external electrode pad 10-1 of the printed wiring board is pre-coated with a solder having a solid phase point of 235 ° C. or less, and the external electrode pad 10-2 has a solid phase point of 240 ° C. or more and 250 ° C. or less. Precoat with solder. In step 23, the external connection terminals 14 of the pin terminals are soldered to the external electrode pads 10-2 to form a pin grid array structure, and then the semiconductor is applied to the external electrode pads 10-1 at a temperature of 235 ° C. or lower. A bump 12 of the element 11 is soldered to manufacture a semiconductor device.

  Note that the external connection terminals 14 to be joined to the printed wiring board before the semiconductor element 11 or the like is soldered are not limited to pin terminals. For example, before soldering the electronic component to the printed wiring board, the printed wiring board in which the external connection terminals 14 of the metal bumps are soldered to the external electrode pads 10-2, or the metal stiffener is soldered to a part of the surface conductor layer. Similarly, when the attached printed wiring board is formed, it is desirable that the external connection terminals 14 and the like are joined to a part of the conductor layer with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower.

  In the semiconductor device manufactured by the above steps, the semiconductor element 11 and the external connection terminal 14 can be installed upside down with respect to the printed wiring board as shown in FIG. Furthermore, the semiconductor element 11 and the external connection terminal 14 can be installed on the lower surface of the printed wiring board, and the external connection terminal 14 and the semiconductor element 11 can be installed on the same lower surface of the printed wiring board.

  In the semiconductor device manufactured by the above steps, the printed wiring board on which the semiconductor element 11 is mounted has a second insulating resin layer above the first insulating resin layer, and the lower layer of the first insulating resin layer and the above A second insulating resin layer having the same number of third insulating resin layers on both surfaces; and a solder resist on both surfaces of the outer surfaces of the third insulating resin layers on both surfaces; The via hole in the insulating resin layer above the resin layer is a frustoconical via hole whose upper diameter is larger than the lower diameter, and the via hole of the insulating resin layer below the first insulating resin layer has an upper diameter. Is a frustoconical via hole smaller than the lower diameter. As such, the direction of the frustoconical shape of the via hole of the printed wiring board on which the semiconductor element 11 is mounted is arranged in an asymmetric direction with respect to the central layer of the layer structure of the printed wiring board. Therefore, when thermal stress is applied to the semiconductor device mounted on the mother board, the printed wiring board of the semiconductor device reflects an asymmetric structure with respect to the central layer of the layer structure, and is on one side of the printed wiring board. Tend to warp. Thereby, there is an effect that the countermeasure and correction of the warp and the management of the warp become easy.

<Second Embodiment>
(Process 1)
In the second embodiment, the support substrate 1 used in the first embodiment is not a single substrate but is used by bonding two 125 μm copper plates, for example. Alternatively, instead of a copper plate, two copper foil supporting substrates 1 formed to a thickness of 125 μm can be adhered and used. As a pretreatment for bonding the support substrate 1, the copper surface on one side of the two support substrates 1 is roughened by CZ treatment or the like. The roughening treatment may be a blackening treatment by oxidation-reduction treatment or a perhydrosulfuric acid based soft etching treatment. Next, the roughened surfaces are opposed to each other, and the end portions of the support substrate 1 of the two copper plates are bonded with a width of 15 mm. As the adhesive, a material obtained by punching the center of the insulating resin layer 2 by pressing or the like is used, and thermocompression bonding is performed by a laminating press or roll lamination depending on the material of the adhesive. Alternatively, as the adhesive, a liquid thermosetting adhesive can be applied to the support substrate 1 by a dispenser or screen printing, and the support substrate 1 can be attached.

(Process 2)
A set of two copper plates obtained in this way is used for the support substrate 1, and the insulating resin layers 2 are formed on both surfaces of the support substrate 1 of the set of two copper plates.
(Step 3 to Step 13)
In the same manner as Step 3 to Step 14 of the first embodiment, however, a conductor layer and an insulating resin layer are built up on both surfaces of a set of two support substrates 1.
(Step 14)
After obtaining the necessary number of build-up layers of conductive layers and insulating resin layers on both sides of the two sets of support substrates 1, next, the end 15mm of the bonding portion of the two sets of support substrates 1 is connected to the router. It cut | disconnects by process etc. and the support substrate 1 of 2 sheets 1 set is isolate | separated into 2 sheets. Then, in the same manner as in step 14 of the first embodiment, the support substrate 1 is removed to form the inner layer substrate 8.
(Step 15 to Step 22)
A printed wiring board is manufactured by forming build-up layers on both surfaces of the inner layer substrate 8 by performing the same processes as in steps 15 to 22 of the first embodiment.

(Modification 7)
As a modification of the second embodiment, in step 1, instead of the copper plate, a support substrate 1 in which release layers are formed on both surfaces of an insulating resin substrate containing glass fibers such as a glass epoxy resin substrate is used. In Step 13, the insulating resin layer and the conductor layer are built up on both surfaces thereof, and in Step 14, the inner layer substrate 8 is peeled off by the peeling layer. In subsequent steps 15 to 22, processing is performed in the same manner as in the first embodiment to manufacture a printed wiring board.
(Modification 8)
As a modification of the second embodiment, in step 1, the support substrate 1 is bonded by heating and pressurizing with a laminating press with a thermally foamable sheet sandwiched between two copper support substrates 1, and step 3 From Step 13 to Step 13, the insulating resin layer and the conductor layer are built up on both surfaces. In Step 14, heat equal to or higher than the lamination temperature, for example, 220 ° C. is applied, and the support substrate 1 is separated by treatment for 5 minutes. By applying this heat history in an oven or the like, the two support substrates 1 are separated without any residue of the thermally foamed sheet. In subsequent steps 15 to 22, processing is performed in the same manner as in the first embodiment to manufacture a printed wiring board.

It is sectional drawing which shows the manufacturing process of 1st Embodiment of the printed wiring board of this invention. It is sectional drawing which shows the manufacturing process of 1st Embodiment of the printed wiring board of this invention. It is sectional drawing which shows the manufacturing process of 1st Embodiment of the printed wiring board of this invention. It is sectional drawing which shows the manufacturing process of 1st Embodiment of the printed wiring board of this invention. It is sectional drawing which shows the manufacturing process of 1st Embodiment of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2, 2-2, 2-3, 2-4, 2-5, 2-6 ... Insulating resin layer 3 ... Plating ground conductive layer 4 ... Plating resist 5 ... -Wiring pattern portions 6, 6-1, 6-2, 6-3, 6-4, 6-5, 6-6 ... wiring pattern 7 ... via hole pilot holes 7-1, 7-2, 7 -3, 7-4, 7-5, 7-6 ... via hole 8 ... inner substrate 9 ... solder resist 10 ... pad opening 10-1, 10-2 ... external electrode Pad 11 ... Semiconductor element 12 ... Bump 13 ... Sealing resin 14 ... External connection terminal

Claims (7)

  A process of stacking a first insulating resin layer on a support substrate, forming a first conductor layer on a surface of the first insulating resin layer, and stacking a second insulating resin layer on the first conductor layer; Then, a build-up process in which an insulating resin layer and a conductor layer are alternately overlapped by a process of forming a via hole in the second insulating resin layer and forming a second conductor layer on the surface is repeated on the surface of the support substrate. A first step of forming an inner layer substrate whose outer layer is covered with the second insulating resin layer, and then a second step of removing the support substrate and making the inner layer substrate independent, Forming a via hole in the insulating resin layer on the outer layer on both sides of the inner layer substrate, forming a third conductive layer on the surface, superimposing the third insulating resin layer on the third conductive layer, and further forming a conductive layer A third build-up process is repeated to increase the number of layers of the inner layer substrate. And a step, then, a method of manufacturing a printed wiring board and having a fourth step of forming a solder resist on the outer layer of the inner layer substrate.   Forming a first conductor layer on a surface of a support substrate having a release layer formed on the surface, and then superimposing a first insulating resin layer on the first conductor layer; and the first insulating resin. A build-up process in which an insulating resin layer and a conductor layer are alternately stacked by forming a via hole in the layer and forming a second conductor layer on the surface is repeated, and the second conductor is formed on the outermost layer on the surface of the support substrate. A first step of forming an inner layer substrate having a layer, and then a second step of removing the support substrate and making the inner layer substrate independent, and then forming outer layers on both sides of the inner layer substrate. A process of superimposing a third insulating resin layer on the first conductor layer and the second conductor layer, and then forming a via hole in the third insulating resin layer on both surfaces of the inner substrate and forming a surface on the surface A third conductor layer is formed, an insulating resin layer is overlaid on the third conductor layer, and further a conductor A third step of increasing the number of layers of the inner layer substrate by repeating the build-up process for forming the inner layer, and then a fourth step of forming a solder resist on the outer layer of the inner layer substrate. A method for manufacturing a wiring board.   The method for manufacturing a printed wiring board according to claim 1, wherein the first insulating resin layer is formed using a prepreg resin containing a reinforcing material.   A printed wiring board having a multi-layered conductor layer, having an insulating resin layer with a reinforcing material in an inner first insulating resin layer and an upper layer of the first insulating resin layer having a second insulating resin layer. And having the same number of third insulating resin layers on both sides of the lower layer of the first insulating resin layer and the upper layer of the second insulating resin layer, and the outer layers of the third insulating resin layers on both sides. Solder resist is provided on both sides, and the via hole in the insulating resin layer equal to or higher than the second insulating resin layer is a frustoconical-shaped via hole having an upper diameter larger than the lower diameter, and the first insulating A printed wiring board, wherein a via hole in an insulating resin layer below the resin layer is a frustoconical via hole whose upper diameter is smaller than the lower diameter, and the thickness of each insulating resin layer between the conductor layers is equal .   An external electrode pad formed on a conductor layer in an opening of the solder resist, and a part of the external electrode pad is precoated with a first solder having a solid phase point of 235 ° C. or less; The printed wiring board according to claim 4, wherein the external connection terminals are soldered with a second solder having a solid point of 240 ° C. or higher and 250 ° C. or lower. A semiconductor device in which a semiconductor element is bonded to an external electrode pad on a surface layer of a printed wiring board having a multi-layered conductor layer, wherein the printed wiring board has an insulating resin layer with a reinforcing material in an inner first insulating resin layer A third insulating resin layer having a second insulating resin layer above the first insulating resin layer and having the same number of layers on both sides of the lower layer of the first insulating resin layer and the upper layer of the second insulating resin layer. A resin layer, a solder resist on both sides of the outer layer of the third insulating resin layer on both sides, and a via hole in the insulating resin layer equal to or higher than the second insulating resin layer having a lower diameter on the upper side A larger frustoconical via hole in the reverse direction, and the via hole in the insulating resin layer below the first insulating resin layer is a frustoconical via hole in which the upper diameter is smaller than the lower diameter; A thickness of each insulating resin layer is equal. .   The external electrode pad is joined to the semiconductor element with a first solder, and the external connection terminal is joined to the second external electrode pad on the surface layer of the printed wiring board with a second solder, 7. The semiconductor device according to claim 6, wherein a solid phase point of the solder is 235 ° C. or lower, and a solid phase point of the second solder is 240 ° C. or higher and 250 ° C. or lower.