JP2002353394A - Wiring board with pin and electronic device using it - Google Patents

Wiring board with pin and electronic device using it

Info

Publication number
JP2002353394A
JP2002353394A JP2001138881A JP2001138881A JP2002353394A JP 2002353394 A JP2002353394 A JP 2002353394A JP 2001138881 A JP2001138881 A JP 2001138881A JP 2001138881 A JP2001138881 A JP 2001138881A JP 2002353394 A JP2002353394 A JP 2002353394A
Authority
JP
Japan
Prior art keywords
solder
weight
lead
pins
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001138881A
Other languages
Japanese (ja)
Inventor
Hideki Ito
英樹 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001138881A priority Critical patent/JP2002353394A/en
Publication of JP2002353394A publication Critical patent/JP2002353394A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with pins and an electronic device capable of excellently connecting lead pins through a socket and soldering to the wiring conductor of an outside electric circuit board without any displacement and unnecessary adhesion of a solder on the lead pins. SOLUTION: In the wiring board with the pins providing a solder bump 8 connected to the wiring conductor 2 on the upper face of an organic material- based insulation substrate 1 having the wiring conductor 2 and bonding the lead pins 3 connected to the wiring conductor 2 on the lower face of an insulation board 1 through the solder 9, the solder bump 8 consisting of alloy of lead of 67-82 wt.%, tin of 5-20 wt.%, antimony of 5-15 wt.% and bismuth of 8-20 wt.%, and the solder 9 consists of lead of 70-85 wt.%, tin of 5-20 wt.% and antimony of 5-15 wt.%.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子等の電
子部品を搭載するために用いられるピン付き配線基板お
よびこのピン付き配線基板上に半導体素子等の電子部品
を搭載して成る電子装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board with pins used for mounting electronic components such as semiconductor elements, and an electronic device having electronic components such as semiconductor elements mounted on the wiring board with pins. Things.

【0002】[0002]

【従来の技術】近時、半導体素子等の電子部品を搭載す
るために用いられるピン付き配線基板として、例えばガ
ラス−エポキシ板等から成る絶縁板やエポキシ樹脂等か
ら成る絶縁層を複数層積層して成る絶縁基板の上面から
下面にかけて銅箔から成る複数の配線導体を設けるとと
もにこれらの配線導体のうち、絶縁基体の上面に導出し
た部位に電子部品の電極が半田バンプを介して接続され
る電子部品接続パッドを、絶縁基体の下面に導出した部
位に複数のピン付けパッドを形成し、これらの電子部品
接続パッドに鉛−錫合金から成る半田バンプを接合させ
るとともにピン付けパッドに鉄系合金や銅系合金から成
る略円柱状のリードピンを鉛−錫合金から成る半田を介
して接合して成る有機材料系のピン付き配線基板が採用
されるようになってきている。このような有機材料系の
ピン付き配線基板は、セラミック材料系のピン付き配線
基板と比較して軽量であり、かつ配線導体の電気抵抗が
小さいという有利な面を有している。そして、このよう
な有機材料系のピン付き配線基板においては絶縁基板の
上面に電子部品をその電極と半田バンプとが接触するよ
うにして搭載するとともに半田バンプを加熱溶融させる
ことにより電子部品の電極と半田バンプとを接合し、し
かる後、電子部品を金属やセラミックから成る蓋体やポ
ッティング樹脂等から成る封止部材により封止すること
によって製品としての電子装置となり、この電子装置に
おいては、絶縁基板下面のリードピンを外部電気回路基
板の配線導体にソケットや半田等を介して接続すること
により外部電気回路基板上に実装されるとともに搭載す
る電子部品が外部電気回路に電気的に接続されることと
なる。
2. Description of the Related Art Recently, as a wiring board with pins used for mounting electronic parts such as semiconductor elements, for example, an insulating plate made of a glass-epoxy plate or a plurality of insulating layers made of an epoxy resin are laminated. A plurality of wiring conductors made of copper foil are provided from the upper surface to the lower surface of the insulating substrate, and an electrode of an electronic component is connected via solder bumps to a portion of the wiring conductors led to the upper surface of the insulating base. A plurality of pinning pads are formed at parts where the component connection pads are led out to the lower surface of the insulating base, and a solder bump made of a lead-tin alloy is joined to these electronic component connection pads, and an iron-based alloy or the like is attached to the pinning pads. A wiring board with pins made of an organic material, which is obtained by joining substantially cylindrical lead pins made of a copper-based alloy via solder made of a lead-tin alloy, has been adopted. It has come. Such an organic material-based wiring board with pins is advantageous in that it is lighter in weight and has a smaller electric resistance of a wiring conductor than a wiring board with pins made of a ceramic material. In such an organic material-based wiring board with pins, the electronic component is mounted on the upper surface of the insulating substrate so that the electrode and the solder bump are in contact with each other, and the solder bump is heated and melted to form the electrode of the electronic component. And a solder bump, and thereafter, the electronic component is sealed with a lid made of metal or ceramic or a sealing member made of a potting resin, etc., thereby forming an electronic device as a product. The lead pins on the bottom surface of the board are connected to the wiring conductors of the external electric circuit board via sockets, solder, etc., so that they are mounted on the external electric circuit board and the mounted electronic components are electrically connected to the external electric circuit. Becomes

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この従
来のピン付き配線基板およびこれを用いた電子装置にお
いては、電子部品の電極が接合される半田バンプやリー
ドピンを接合するために用いられる半田として通常は鉛
−錫共晶合金から成る半田が使用されており、鉛−錫共
晶合金から成る半田は鉄系合金や銅合金から成るリード
ピンとの濡れ性が良好であることからピン付けパッドに
リードピンを鉛−錫共晶合金から成る半田を介して接合
する際に、鉛−錫共晶合金から成る半田の一部がリード
ピンの下端部にまで濡れ広がり、その結果、リードピン
の下端部に不要な半田が多量に付着してしまうことがあ
り、そのように半田がリードピンの下端部に多量に付着
した場合、リードピンを外部電気回路基板の配線導体に
ソケットや半田を介して良好に接続することが困難とな
ってしまうという問題点を有していた。また、電子部品
の電極が接合される半田バンプやリードピンを接合する
半田が共に鉛−錫共晶合金から成る場合、電子部品の電
極と半田バンプとを接合する際、半田バンプを溶融させ
るための熱によりリードピンをピン付けパッドに接合し
ている半田も同時に溶融軟化してリードピンにずれが発
生してしまい、その場合にもリードピンを外部電気回路
基板の配線導体に良好に接続することができなくなって
しまうという問題点を有していた。
However, in this conventional wiring board with pins and an electronic device using the same, the solder used for bonding the solder bumps or the lead pins to which the electrodes of the electronic parts are bonded is usually used. Are made of lead-tin eutectic solder, and solder made of lead-tin eutectic alloy has good wettability with lead pins made of iron-based alloy or copper alloy. Is joined via a lead-tin eutectic alloy solder, a part of the lead-tin eutectic solder wets and spreads to the lower end of the lead pin. A large amount of solder may adhere, and if such a large amount of solder adheres to the lower end of the lead pin, place the lead pin on the wiring conductor of the external electric circuit board using a socket or solder. It has been a problem that it becomes difficult to satisfactorily connect. Further, when the solder for joining the electrodes of the electronic component and the solder for joining the lead pins are both made of a lead-tin eutectic alloy, when joining the electrodes of the electronic component and the solder bump, the solder bump is melted. The solder that joins the lead pin to the pinning pad due to heat also melts and softens at the same time, causing a shift in the lead pin. In this case, the lead pin cannot be connected well to the wiring conductor of the external electric circuit board. Had the problem that

【0004】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、リードピンの下端部に
半田の付着がないとともに、電子部品の電極と半田バン
プとを接合する際等にリードピンにずれが発生すること
がなく、それによりリードピンを外部電気回路基板の配
線導体にソケットや半田を介して良好に接続することが
可能なピン付き配線基板およびそれを用いた電子装置を
提供することにある。
The present invention has been devised in view of the conventional problems, and has as its object to prevent solder from adhering to a lower end portion of a lead pin and to join an electrode of an electronic component to a solder bump. And the like, and an electronic device using the same can be connected to a wiring conductor of an external electric circuit board through a socket or solder without causing a shift in the lead pin. To provide.

【0005】[0005]

【課題を解決するための手段】本発明のピン付き配線基
板は、配線導体を有する有機材料系の絶縁基板の上面に
配線導体に接続された半田バンプを設けるとともに、絶
縁基板の下面に配線導体に接続されたリードピンを半田
を介して接合して成るピン付き配線基板であって、半田
バンプが67〜82重量%の鉛と5〜20重量%の錫と5〜15
重量%のアンチモンと8〜20重量%のビスマスとの合金
から成り、リードピンを接合する半田が70〜85重量%の
鉛と5〜20重量%の錫と5〜15重量%のアンチモンとか
ら成ることを特徴とするものである。
According to the present invention, there is provided a wiring board with pins according to the present invention, wherein solder bumps connected to wiring conductors are provided on an upper surface of an organic material-based insulating substrate having wiring conductors, and wiring conductors are provided on a lower surface of the insulating substrate. A wiring board with pins formed by joining lead pins connected to a solder via solder, wherein the solder bumps are composed of 67 to 82% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight.
% Of antimony and 8 to 20% by weight of bismuth, and the solder for joining the lead pins consists of 70 to 85% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight of antimony. It is characterized by the following.

【0006】また、本発明の電子装置は、配線導体を有
する有機材料系の絶縁基板の上面に配線導体に接続され
た半田バンプを設けるとともに、絶縁基板の下面に配線
導体に接続されたリードピンを半田を介して接合して成
るピン付き配線基板に電子部品を搭載するとともに電子
部品の電極と半田バンプとを電気的に接続して成る電子
装置であって、半田バンプが67〜82重量%の鉛と5〜20
重量%の錫と5〜15重量%のアンチモンと8〜20重量%
のビスマスとの合金から成り、リードピンを接合する半
田が70〜85重量%の鉛と5〜20重量%の錫と5〜15重量
%のアンチモンとから成ることを特徴とするものであ
る。
In the electronic device of the present invention, a solder bump connected to a wiring conductor is provided on an upper surface of an organic material-based insulating substrate having a wiring conductor, and a lead pin connected to the wiring conductor is provided on a lower surface of the insulating substrate. An electronic device in which an electronic component is mounted on a wiring board with pins formed by bonding via solder and an electrode of the electronic component is electrically connected to a solder bump. Lead and 5-20
5% by weight of tin, 5-15% by weight of antimony and 8-20% by weight
And the solder for joining the lead pins is composed of 70 to 85% by weight of lead, 5 to 20% by weight of tin, and 5 to 15% by weight of antimony.

【0007】本発明のピン付き配線基板およびこれを用
いた電子装置によれば、リードピンを接合する半田は、
70〜85重量%の鉛と5〜20重量%の錫と5〜15重量%の
アンチモンとの合金から成ることから、このような組成
によりリードピンとの濡れ性が適度に抑制され、その結
果、リードピンを絶縁基板に接合する際にリードピンの
下端部に半田が濡れ広がることが有効に防止される。ま
た、電子部品の電極が接合される半田バンプは、67〜82
重量%の鉛と5〜20重量%の錫と5〜15重量%のアンチ
モンと8〜20重量%のビスマスとの合金から成ることか
ら、リードピンを接合する70〜85重量%の鉛と5〜20重
量%の錫と5〜15重量%のアンチモンとから成る半田よ
りその融点が低く、したがって、電子部品の電極と半田
バンプとを接合する際にリードピンを接合する半田を軟
化溶融させることなく、電子部品の電極と半田バンプと
を接合することができる。
According to the wiring board with pins and the electronic device using the same of the present invention, the solder for joining the lead pins is
Since it is composed of an alloy of 70 to 85% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight of antimony, such a composition moderately suppresses wettability with the lead pin, and as a result, When the lead pin is joined to the insulating substrate, the solder is effectively prevented from spreading to the lower end of the lead pin. Also, the solder bumps to which the electrodes of the electronic components are joined are 67 to 82
Of lead, 5 to 20% by weight of tin, 5 to 15% by weight of antimony and 8 to 20% by weight of bismuth. The melting point is lower than that of the solder composed of 20% by weight of tin and 5 to 15% by weight of antimony. Therefore, when joining the electrodes of the electronic component and the solder bumps, the solder for joining the lead pins is not softened and melted. The electrodes of the electronic component and the solder bumps can be joined.

【0008】[0008]

【発明の実施の形態】つぎに、本発明を添付の図面に基
づき詳細に説明する。図1は、本発明を半導体素子を搭
載するためのピン付き配線基板およびこれに半導体素子
を搭載した電子装置に適用した場合の実施の形態の一例
を示す断面図であり、1は絶縁基板、2は配線導体、3
はリードピンである。この絶縁基板1と配線導体2とリ
ードピン3とで本発明のピン付き配線基板が構成され、
これに電子部品としての半導体素子4を搭載することに
より本発明の電子装置が形成される。
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment in which the present invention is applied to a wiring board with pins for mounting a semiconductor element and an electronic device having the semiconductor element mounted thereon, where 1 is an insulating substrate, 2 is a wiring conductor, 3
Is a lead pin. The insulating substrate 1, the wiring conductor 2, and the lead pins 3 constitute a wiring board with pins of the present invention,
The electronic device of the present invention is formed by mounting the semiconductor element 4 as an electronic component on this.

【0009】絶縁基板1は、例えばガラス繊維を縦横に
織り込んだガラス織物にエポキシ樹脂やビスマレイミド
トリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状
の芯体1aの上下面にエポキシ樹脂やビスマレイミドト
リアジン樹脂等の熱硬化性樹脂から成る絶縁層1bをそ
れぞれ複数層ずつ積層して成る有機材料系の多層板であ
り、その上面から下面にかけては銅箔や銅めっき膜等か
ら成る複数の配線導体2が形成されている。
The insulating substrate 1 is made of a glass fabric in which glass fibers are woven vertically and horizontally, and is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. An organic material-based multilayer board formed by laminating a plurality of insulating layers 1b each made of a thermosetting resin such as a bismaleimide triazine resin, and a plurality of layers made of a copper foil, a copper plating film, or the like from the upper surface to the lower surface. The wiring conductor 2 is formed.

【0010】絶縁基板1を構成する芯体1aは、厚みが
0.3〜1.5mm程度であり、その上面から下面にかけて直
径が0.1〜1.0mm程度の複数の貫通孔5を有している。
そして、その上下面および各貫通孔5の内壁には配線導
体2の一部が被着されており、上下面の配線導体2が貫
通孔5を介して電気的に接続されている。
The core 1a constituting the insulating substrate 1 has a thickness.
It has a plurality of through-holes 5 of about 0.3 to 1.5 mm and a diameter of about 0.1 to 1.0 mm from the upper surface to the lower surface.
A part of the wiring conductor 2 is attached to the upper and lower surfaces and the inner wall of each through-hole 5, and the wiring conductors 2 on the upper and lower surfaces are electrically connected through the through-hole 5.

【0011】このような芯体1aは、ガラス織物に未硬
化の熱硬化性樹脂を含浸させたシートを熱硬化させた
後、これに上面から下面にかけてドリル加工を施すこと
により製作される。なお、芯体1a上下面の配線導体2
は、芯体1a用のシートの上下全面に厚みが3〜50μm
程度の銅箔を貼着しておくとともにこの銅箔をシートの
硬化後にエッチング加工することにより所定のパターン
に形成される。また、貫通孔5内壁の配線導体2は、芯
体1aに貫通孔5を設けた後に、この貫通孔5内壁に無
電解めっき法および電解めっき法により厚みが3〜50μ
m程度の銅めっき膜を析出させることにより形成され
る。
Such a core body 1a is manufactured by thermally curing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then performing drilling from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the core 1a
Has a thickness of 3 to 50 μm on the entire upper and lower surfaces of the sheet for the core 1a.
A predetermined pattern is formed by attaching a copper foil of a degree and etching the copper foil after curing the sheet. The wiring conductor 2 on the inner wall of the through-hole 5 has a thickness of 3 to 50 μm after the through-hole 5 is formed in the core 1a and the inner wall of the through-hole 5 is formed by electroless plating and electrolytic plating.
It is formed by depositing a copper plating film of about m.

【0012】さらに、芯体1aは、その貫通孔5の内部
にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱
硬化性樹脂から成る樹脂柱6が充填されている。樹脂柱
6は、貫通孔5を塞ぐことにより貫通孔5の直上および
直下に絶縁層1bを形成可能とするためのものであり、
未硬化のペースト状の熱硬化性樹脂を貫通孔5内にスク
リーン印刷法により充填し、これを熱硬化させた後、そ
の上下面を略平坦に研磨することにより形成される。そ
して、この樹脂柱6を含む芯体1aの上下面に絶縁層1
bが積層されている。
Further, the core 1a is filled with a resin column 6 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin in the inside of the through hole 5. The resin pillar 6 is for enabling the insulating layer 1b to be formed directly above and directly below the through hole 5 by closing the through hole 5.
An uncured paste-like thermosetting resin is filled in the through-holes 5 by screen printing, and after thermosetting, the upper and lower surfaces are polished to be substantially flat. The insulating layer 1 is formed on the upper and lower surfaces of the core body 1a including the resin column 6.
b is laminated.

【0013】芯体1aの上下面に積層された絶縁層1b
は、それぞれの厚みが20〜60μm程度であり、各層の上
面から下面にかけて直径が30〜100μm程度の複数の貫
通孔7を有している。これらの絶縁層1bは、配線導体
2を高密度に配線するための絶縁間隔を提供するための
ものである。そして、上層の配線導体2と下層の配線導
体2とを貫通孔7を介して電気的に接続することにより
高密度配線を立体的に形成可能としている。このような
絶縁層1bは、厚みが20〜60μm程度の未硬化の熱硬化
性樹脂のフィルムを芯体1a上下面に貼着し、これを熱
硬化させるとともにレーザー加工により貫通孔7を穿孔
し、さらにその上に同様にして次の絶縁層1bを順次積
み重ねることによって形成される。なお、各絶縁層1b
表面および貫通孔7内に被着された配線導体2は、各絶
縁層1bを形成する毎に各絶縁層1bの表面および貫通
孔7内に5〜50μm程度の厚みの銅めっき膜を公知のセ
ミアディティブ法やサブトラクティブ法等のパターン形
成法により所定のパターンに被着させることによって形
成される。
An insulating layer 1b laminated on the upper and lower surfaces of the core 1a
Has a plurality of through holes 7 each having a thickness of about 20 to 60 μm and a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. These insulating layers 1b are for providing an insulating interval for wiring the wiring conductors 2 at high density. By electrically connecting the upper layer wiring conductor 2 and the lower layer wiring conductor 2 through the through-hole 7, high-density wiring can be formed three-dimensionally. Such an insulating layer 1b is formed by attaching a film of an uncured thermosetting resin having a thickness of about 20 to 60 μm to the upper and lower surfaces of the core 1a, thermally curing the same, and forming the through holes 7 by laser processing. The insulating layer 1b is formed by successively stacking the next insulating layers 1b in a similar manner. In addition, each insulating layer 1b
The wiring conductor 2 attached on the surface and in the through hole 7 is formed by forming a copper plating film having a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and in the through hole 7 every time the insulating layer 1b is formed. It is formed by applying a predetermined pattern by a pattern forming method such as a semi-additive method or a subtractive method.

【0014】絶縁基板1の上面から下面にかけて形成さ
れた配線導体2は、半導体素子4の各電極を外部電気回
路基板に接続するための導電路として機能し、絶縁基板
1の上面に設けられた部位の一部が半導体素子4の各電
極に半田バンプ8を介して接続される電子部品接続パッ
ド2aを、絶縁基板1の下面に露出した部位の一部が外
部接続端子としてのリードピン3を接合するためのピン
付けパッド2bを形成している。そして、電子部品接続
パッド2aには半田バンプ8が接合されており、ピン付
けパッド2bにはリードピン3が半田9を介して接合さ
れている。このような電子部品接続パッド2aおよびピ
ン付けパッド2bは、図2に要部拡大平面図で示すよう
に、配線導体2に接続された略円形のパターンの外周部
をソルダーレジストと呼ばれる最外層の絶縁層1bによ
り15〜150μm程度の幅で被覆してその外周縁を画定す
ることによりその直径φが、電子部品接続パッド2aで
あれば略70〜200μm程度に、ピン付けパッド2bであ
れば略0.5〜2.5mm程度になるように形成されている。
なお、このようなソルダーレジスト1bにより電子部品
接続パッド2a同士あるいはピン付けパッド2b同士の
半田8や9による電気的な短絡が有効に防止されるとと
もに電子部品接続パッド2aおよびピン付けパッド2b
の絶縁基板1に対する接合強度が高いものとなってい
る。
The wiring conductor 2 formed from the upper surface to the lower surface of the insulating substrate 1 functions as a conductive path for connecting each electrode of the semiconductor element 4 to an external electric circuit board, and is provided on the upper surface of the insulating substrate 1. Part of the part is connected to the electronic component connection pad 2a connected to each electrode of the semiconductor element 4 via the solder bump 8, and part of the part exposed on the lower surface of the insulating substrate 1 is connected to the lead pin 3 as an external connection terminal. To form a pinning pad 2b. The solder bumps 8 are joined to the electronic component connection pads 2a, and the lead pins 3 are joined to the pinning pads 2b via the solder 9. As shown in the enlarged plan view of the main part of FIG. 2, the electronic component connection pad 2a and the pinning pad 2b are formed by forming the outer peripheral portion of the substantially circular pattern connected to the wiring conductor 2 on the outermost layer called solder resist. By covering the insulating layer 1b with a width of about 15 to 150 μm and defining the outer periphery thereof, the diameter φ is about 70 to 200 μm for the electronic component connection pad 2a, and substantially for the pinning pad 2b. It is formed to be about 0.5 to 2.5 mm.
The solder resist 1b effectively prevents an electrical short circuit between the electronic component connection pads 2a or the pinning pads 2b due to the solder 8 or 9, and also prevents the electronic component connection pads 2a and the pinning pads 2b.
Has a high bonding strength to the insulating substrate 1.

【0015】電子部品接続パッド2aに接合された半田
バンプ8は、67〜82重量%の鉛と5〜20重量%の錫と5
〜15重量%のアンチモンと8〜20重量%のビスマスとの
合金から成り、半導体素子4の各電極を配線導体2に電
気的に接続するための接続部材として機能するととも
に、半導体素子4を絶縁基板1上に固定するための固定
部材として機能する。そして、絶縁基板1上に半導体素
子4をその各電極と各半田バンプ8とが接触するように
して搭載するとともに、これらをはんだバンプ8の溶融
温度以上の温度に加熱して半田バンプ8を溶融させるこ
とにより半導体素子4の各電極と半田バンプ8とが接合
され、それにより半導体素子4の各電極と配線導体2と
が半田バンプ8を介して電気的に接続されるとともに半
導体素子4が絶縁基板1上に半田バンプ8を介して固定
される。
The solder bumps 8 bonded to the electronic component connection pads 2a are composed of 67-82% by weight of lead, 5-20% by weight of tin and 5% by weight of tin.
-15% by weight of an alloy of antimony and 8-20% by weight of bismuth, which functions as a connecting member for electrically connecting each electrode of the semiconductor element 4 to the wiring conductor 2 and insulates the semiconductor element 4 It functions as a fixing member for fixing on the substrate 1. Then, the semiconductor element 4 is mounted on the insulating substrate 1 such that each electrode and each solder bump 8 are in contact with each other, and these are heated to a temperature equal to or higher than the melting temperature of the solder bump 8 to melt the solder bump 8. Thereby, each electrode of the semiconductor element 4 and the solder bump 8 are joined, whereby each electrode of the semiconductor element 4 and the wiring conductor 2 are electrically connected via the solder bump 8 and the semiconductor element 4 is insulated. It is fixed on the substrate 1 via solder bumps 8.

【0016】また、ピン付けパッド2bに接合されたリ
ードピン3は、図3に要部拡大断面図で示すように、例
えば鉄−ニッケル−コバルト合金・鉄−ニッケル合金等
の鉄系合金や銅−鉄−亜鉛−リン合金等の銅系合金から
成り、直径Aが0.25〜0.5mm程度で長さが1〜3.5mm
程度の略円柱状の軸部3aの上端に直径Bが0.45〜1.25
mmで厚みTが0.05〜0.3mm程度のネールヘッドと呼
ばれる略円板状の径大部3bを形成して成る。そして、
この径大部3bをピン付けパッド2bに70〜85重量%の
鉛と5〜20重量%の錫と5〜15重量%のアンチモンとの
合金から成る半田9で接合することによりリードピン3
がピン付けパッド2bに立設されているそして、この配
線基板においては、電子部品接続パッド2aに半導体素
子4の各電極を半田バンプ8を介して接合して半導体素
子4を搭載するとともにこの半導体素子4を図示しない
蓋体やポッティング樹脂により封止することによって電
子装置となり、この電子装置におけるリードピン3をソ
ケットや半田を介して外部電気回路基板の配線導体に接
続することにより本発明の電子装置が外部電気回路基板
に実装されることとなる。
The lead pins 3 joined to the pinning pads 2b are, as shown in an enlarged sectional view of a main part in FIG. 3, for example, an iron-based alloy such as an iron-nickel-cobalt alloy or an iron-nickel alloy, or a copper alloy. It is made of a copper alloy such as an iron-zinc-phosphorus alloy and has a diameter A of about 0.25 to 0.5 mm and a length of 1 to 3.5 mm.
The diameter B is 0.45 to 1.25 at the upper end of the substantially cylindrical shaft portion 3a of about
It is formed by forming a substantially disk-shaped large-diameter portion 3b called a nail head having a thickness T of about 0.05 to 0.3 mm. And
The large diameter portion 3b is joined to the pinning pad 2b with a solder 9 made of an alloy of 70 to 85% by weight of lead, 5 to 20% by weight of tin, and 5 to 15% by weight of antimony.
In this wiring board, the electrodes of the semiconductor element 4 are joined to the electronic component connection pads 2a via the solder bumps 8 to mount the semiconductor element 4 and the semiconductor element 4 is mounted on the wiring board. An electronic device is obtained by sealing the element 4 with a lid or a potting resin (not shown). The electronic device of the present invention is obtained by connecting the lead pins 3 in this electronic device to the wiring conductors of the external electric circuit board via a socket or solder. Is mounted on the external electric circuit board.

【0017】なお、本発明においては、半導体素子4の
電極と接合される半田バンプ8が67〜82重量%の鉛と5
〜20重量%の錫と5〜15重量%のアンチモンと8〜20重
量%のビスマスとの合金から形成されており、リードピ
ン3を接合する半田9が70〜85重量%の鉛と5〜20重量
%の錫と5〜15重量%のアンチモンとの合金から成るこ
とが重要である。
In the present invention, the solder bumps 8 to be joined to the electrodes of the semiconductor element 4 are composed of 67 to 82% by weight of lead and 5%.
The solder 9 for joining the lead pins 3 is made of an alloy of about 20% by weight of tin, 5% to 15% by weight of antimony, and 8% to 20% by weight of bismuth. It is important that it consist of an alloy of 5% by weight of tin and 5 to 15% by weight of antimony.

【0018】半導体素子4の電極が接合される半田バン
プ8は、67〜82重量%の鉛と5〜20重量%の錫と5〜15
重量%のアンチモンと8〜20重量%のビスマスとの合金
から形成されており、リードピン3を接合する70〜85重
量%の鉛と5〜20重量%の錫と5〜15重量%のアンチモ
ンとの合金から成る半田9よりもその融点が10〜20℃程
度低いものとなっている。したがって、半導体素子4の
各電極と半田バンプ8とを接合する際に、半田バンプ8
の溶融温度以上でかつ半田9の溶融温度以下の温度で加
熱して半田バンプ8を溶融させることによりリードピン
3にずれを発生させることなく、半導体素子4の各電極
と半田バンプ8とを接合させることができる。
The solder bumps 8 to which the electrodes of the semiconductor element 4 are bonded are composed of 67 to 82% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight.
% Of antimony and 8 to 20% by weight of bismuth. The lead pin 3 is joined with 70 to 85% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight of antimony. The melting point of the solder 9 is lower by about 10 to 20 ° C. Therefore, when joining each electrode of the semiconductor element 4 and the solder bump 8, the solder bump 8
By melting the solder bumps 8 by heating at a temperature not lower than the melting temperature of the solder 9 and not higher than the melting temperature of the solder 9, each electrode of the semiconductor element 4 and the solder bumps 8 are joined without causing a shift in the lead pins 3. be able to.

【0019】なお、半田バンプ8に含有させる鉛は、そ
の含有量が67重量%未満であると、半田バンプ8の融点
が低くなりすぎてしまい、例えばリードピン3を外部電
気回路基板の配線導体に鉛−錫共晶合金から成る半田を
介して接合する場合等に約230℃程度の温度が印加され
ると、半田バンプ8が溶融して半導体素子4の電極と半
田バンプ8との間にずれや断線が発生してしまう危険性
が大きくなり、82重量%を超えると、有機材料系の配線
基板に用いる半田としては、融点が高くなりすぎてしま
い、半田バンプ8を形成する際や半導体素子4と半田バ
ンプ8とを接合する際などに半田バンプ8を溶融させる
ための熱により絶縁基板1に悪影響を与えてしまう危険
性が高くなる。したがって、半田バンプ8に含有される
鉛の含有量は、670〜82重量%の範囲に特定される。
If the content of lead contained in the solder bumps 8 is less than 67% by weight, the melting point of the solder bumps 8 becomes too low. For example, the lead pins 3 may be used as wiring conductors of an external electric circuit board. When a temperature of about 230 ° C. is applied, for example, when bonding is performed via solder made of a lead-tin eutectic alloy, the solder bump 8 melts and shifts between the electrode of the semiconductor element 4 and the solder bump 8. If the content exceeds 82% by weight, the melting point of the solder used for an organic material-based wiring board becomes too high, so that the solder bump 8 may be formed when the solder bump 8 is formed. When joining the solder bumps 4 with the solder bumps 8, there is a high risk that the heat for melting the solder bumps 8 may adversely affect the insulating substrate 1. Therefore, the content of lead contained in the solder bump 8 is specified in the range of 670 to 82% by weight.

【0020】また、半田バンプ8に含有される錫は、そ
の含有量が5重量%未満であると、半田バンプ8の融点
が高くなりすぎる傾向にあり、20重量%を超えると、半
導体素子4の電極に対する濡れ性が良好となりすぎて、
半導体素子4の電極との間に不要な金属間化合物が多量
に形成されてしまう危険性が高くなる。したがって、半
田バンプ8中に含有される錫の含有量は、5〜20重量%
の範囲に特定される。
If the content of tin contained in the solder bumps 8 is less than 5% by weight, the melting point of the solder bumps 8 tends to be too high. The wettability of the electrode becomes too good,
There is a high danger that a large amount of unnecessary intermetallic compounds will be formed between the electrodes of the semiconductor element 4. Therefore, the content of tin contained in the solder bump 8 is 5 to 20% by weight.
Specified in the range.

【0021】さらに、半田バンプ8に含有されるアンチ
モンは、半田バンプ8の固相温度を高めるとともに半田
バンプ8に適度な濡れ性を付与し、その含有量が5重量
%未満であれば、半導体素子4の電極に対する半田バン
プ8の濡れ性が良好なものとなりすぎてしまう傾向にあ
り、15重量%を超えると、半田バンプ8の融点が高くな
りすぎるとともに機械的強度が低下してしまう傾向にあ
る。したがって、半田バンプ8に含有されるアンチモン
の含有量は、5〜15重量%の範囲に特定される。
Further, antimony contained in the solder bumps 8 increases the solid phase temperature of the solder bumps 8 and imparts appropriate wettability to the solder bumps 8. If the content is less than 5% by weight, the semiconductor The wettability of the solder bumps 8 to the electrodes of the element 4 tends to be too good, and if it exceeds 15% by weight, the melting point of the solder bumps 8 tends to be too high and the mechanical strength tends to decrease. is there. Therefore, the content of antimony contained in the solder bump 8 is specified in the range of 5 to 15% by weight.

【0022】またさらに、半田バンプ8に含有されるビ
スマスは、半田バンプ8の融点を下げる作用をなし、そ
の含有量が8重量%未満では、半田バンプ8の融点が高
いものとなってしまう傾向にあり、20重量%を超える
と、半田バンプ8の機械的強度が低下してしまう傾向に
ある。したがって、半田バンプ8に含有されるビスマス
の含有量は、8〜20重量%の範囲に特定される。
Further, bismuth contained in the solder bump 8 has an effect of lowering the melting point of the solder bump 8, and if the content is less than 8% by weight, the melting point of the solder bump 8 tends to be high. If it exceeds 20% by weight, the mechanical strength of the solder bump 8 tends to decrease. Therefore, the content of bismuth contained in the solder bump 8 is specified in the range of 8 to 20% by weight.

【0023】また、リードピン3を接合している半田9
は、70〜85重量%の鉛と5〜20重量%の錫と5〜15重量
%のアンチモンとの合金から成ることから、鉄系合金や
銅系合金から成るリードピン3との濡れ性がそれほど良
好ではない。したがって、リードピン3とピン付けパッ
ド2bとを半田9を介して接合する際に半田9がリード
ピン3の軸部3aに濡れ広がることが有効に防止され、
その結果、リードピン3の軸部3aに半田9の付着がな
く、リードピン3を外部電気回路基板の配線導体にソケ
ットや半田を介して良好に接続することが可能となる。
また、その融点が260〜270℃程度と低いのでリードピン
3とピン付けパッド2bとを有機材料系の絶縁基板1に
悪影響を与えることなく接合することができる。
The solder 9 joining the lead pins 3
Is made of an alloy of 70 to 85% by weight of lead, 5 to 20% by weight of tin and 5 to 15% by weight of antimony, so that the wettability with the lead pin 3 made of an iron-based alloy or a copper-based alloy is not so high. Not good. Therefore, when joining the lead pin 3 and the pinning pad 2b via the solder 9, the solder 9 is effectively prevented from spreading on the shaft portion 3a of the lead pin 3,
As a result, the solder 9 does not adhere to the shaft portion 3a of the lead pin 3, and the lead pin 3 can be satisfactorily connected to the wiring conductor of the external electric circuit board via the socket or the solder.
Further, since the melting point is as low as about 260 to 270 ° C., the lead pin 3 and the pinning pad 2 b can be joined without adversely affecting the organic material-based insulating substrate 1.

【0024】なお、半田9に含有される鉛は、その含有
量が70重量%未満であると、半田9の融点が低くなりす
ぎてしまい、例えば半導体素子4の各電極を半田8を介
して電子部品接続パッド2aに電気的に接続する際等に
230℃程度の熱が印加されると半田9も同時に溶融して
リードピン3にずれが発生してしまう危険性が高くな
り、85重量%を超えると、有機材料系の配線基板に用い
る半田としては融点が高くなりすぎてしまい、リードピ
ン3をピン付けパッド2bに半田9を介して接合する際
に、半田9を溶融させるための熱で絶縁基板1に悪影響
を与えてしまう危険性が高くなる。したがって、半田9
に含有される鉛の含有率は、70〜85重量%の範囲に特定
される。
If the content of lead contained in the solder 9 is less than 70% by weight, the melting point of the solder 9 becomes too low. When electrically connecting to the electronic component connection pad 2a
When the heat of about 230 ° C. is applied, the risk that the solder 9 is melted at the same time and the lead pin 3 is displaced increases, and if the heat exceeds 85% by weight, the solder used for the wiring board of the organic material is The melting point becomes too high, and when joining the lead pin 3 to the pinning pad 2b via the solder 9, there is a high danger that the heat for melting the solder 9 may adversely affect the insulating substrate 1. Therefore, the solder 9
Is specified in the range of 70 to 85% by weight.

【0025】また、半田9に含有される錫は、その含有
量が5重量%未満であると、半田9の融点が高くなりす
ぎる傾向にあり、20重量%を超えると、半田9のリード
ピン3に対する濡れ性が良好となりすぎて、リードピン
3をピン付けパッド2bに半田9を介して接合する際に
半田9の一部がリードピン3の軸部3aまで流出してし
まう危険性が高くなる。したがって、半田9中に含有さ
れる錫の含有量は、5〜20重量%の範囲に特定される。
When the content of tin contained in the solder 9 is less than 5% by weight, the melting point of the solder 9 tends to be too high. When the lead pin 3 is joined to the pinning pad 2b via the solder 9, the danger of part of the solder 9 flowing out to the shaft 3a of the lead pin 3 increases. Therefore, the content of tin contained in the solder 9 is specified in the range of 5 to 20% by weight.

【0026】さらに、半田9に含有されるアンチモン
は、半田9の固相温度を高めるとともに半田9に適度な
濡れ性を付与し、その含有量が5重量%未満であれば、
半田9のリードピン3に対する濡れ性が良好なものとな
りすぎてしまう傾向にあり、15重量%を超えると、半田
9の融点が高くなりすぎるとともに機械的強度が低下し
てしまう傾向にある。したがって、半田9に含有される
アンチモンの含有量は、5〜15重量%の範囲に特定され
る。
Further, the antimony contained in the solder 9 increases the solid phase temperature of the solder 9 and imparts an appropriate wettability to the solder 9, and if the content is less than 5% by weight,
There is a tendency that the wettability of the solder 9 to the lead pins 3 tends to be too good, and if it exceeds 15% by weight, the melting point of the solder 9 tends to be too high and the mechanical strength tends to decrease. Therefore, the content of antimony contained in the solder 9 is specified in the range of 5 to 15% by weight.

【0027】なお、リードピン3をピン付けパッド2b
に半田9を介して接合するには、ピン付けパッド2bに
半田9用の半田ペーストを例えばメタルマスクを用いた
スクリーン印刷法により所定量印刷塗布するとともにそ
の上にリードピン3の径大部3b上端面を突き当てて当
接させ、これらを260〜270℃程度の温度で1〜2分間加
熱して半田を溶融させた後、常温に冷却する方法が採用
される。
The lead pin 3 is connected to the pin pad 2b.
In order to join the lead pins 3 via the solder 9, a predetermined amount of a solder paste for the solder 9 is applied to the pinning pad 2 b by screen printing using a metal mask, for example, and the large diameter portion 3 b of the lead pin 3 is formed thereon. A method is adopted in which the end faces are brought into contact with each other, heated at a temperature of about 260 to 270 ° C. for 1 to 2 minutes to melt the solder, and then cooled to room temperature.

【0028】かくして、本発明のピン付き配線基板およ
びこれを用いた電子装置によれば、リードピン3にずれ
の発生がないとともにリードピン3の軸部3aに半田9
の付着がなく、それによりリードピン3を外部電気回路
基板の配線導体にソケットや半田を介して良好に接続可
能なピン付き配線基板およびそれを用いた電子装置を提
供することができる。
Thus, according to the wiring board with pins of the present invention and the electronic device using the same, the lead pins 3 are not displaced and the solder 9 is attached to the shaft 3a of the lead pins 3.
The present invention can provide a wiring board with pins capable of satisfactorily connecting lead pins 3 to wiring conductors of an external electric circuit board via a socket or solder, and an electronic device using the same.

【0029】なお、本発明は、上述の実施の形態の一例
に限定されるものではなく、本発明の要旨を逸脱しない
範囲であれば種々の変更が可能であることはいうまでも
ない。
The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the scope of the present invention.

【0030】[0030]

【発明の効果】本発明のピン付き配線基板およびこれを
用いた電子装置によれば、リードピンを接合する半田
は、70〜85重量%の鉛と5〜20重量%の錫と5〜15重量
%のアンチモンとの合金から成ることから、このような
組成によりリードピンとの濡れ性が適度に抑制され、そ
の結果、リードピンを絶縁基板に接合する際にリードピ
ンの下端部に半田が濡れ広がることが有効に防止され
る。また、電子部品の電極が接合される半田バンプは、
67〜82重量%の鉛と5〜20重量%の錫と5〜15重量%の
アンチモンと8〜20重量%のビスマスとの合金から成る
ことから、リードピンを接合する70〜85重量%の鉛と5
〜20重量%の錫と5〜15重量%のアンチモンとから成る
半田よりその融点が低く、したがって、電子部品の電極
と半田バンプとを接合する際にリードピンにずれが発生
することがなく、その結果、リードピンを外部電気回路
基板の配線導体にソケットや半田を介して良好に接続可
能なピン付き配線基板およびそれを用いた電子装置を提
供することができる。
According to the wiring board with pins of the present invention and the electronic device using the same, the solder for joining the lead pins is composed of 70 to 85% by weight of lead, 5 to 20% by weight of tin, and 5 to 15% by weight. % Of the alloy with antimony, the wettability with the lead pin is appropriately suppressed by such a composition, and as a result, when the lead pin is joined to the insulating substrate, the solder spreads at the lower end of the lead pin. Effectively prevented. Also, the solder bumps to which the electrodes of the electronic components are joined are:
70-85 wt% lead joining the lead pins, consisting of an alloy of 67-82 wt% lead, 5-20 wt% tin, 5-15 wt% antimony and 8-20 wt% bismuth And 5
The melting point is lower than that of a solder composed of -20% by weight of tin and 5-15% by weight of antimony. Therefore, when joining an electrode of an electronic component and a solder bump, no deviation occurs in a lead pin. As a result, it is possible to provide a wiring board with pins capable of satisfactorily connecting lead pins to a wiring conductor of an external electric circuit board via a socket or solder, and an electronic device using the same.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のピン付き配線基板および電子装置の実
施形態例の断面図である。
FIG. 1 is a cross-sectional view of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【図2】本発明のピン付き配線基板および電子装置の実
施形態例の要部拡大平面図である。
FIG. 2 is an enlarged plan view of a main part of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【図3】本発明のピン付き配線基板および電子装置の実
施形態例の要部拡大断面図である。
FIG. 3 is an enlarged sectional view of a main part of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【符号の説明】 1・・・・・絶縁基体 2・・・・・配線導体 3・・・・・リードピン 4・・・・・電子部品としての半導体素子 8・・・・・半田バンプ 9・・・・・リードピン3を接合する半田[Description of Signs] 1... Insulating base 2... Wiring conductor 3... Lead pin 4... Semiconductor element as electronic component 8. .... Solder for joining lead pins 3

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/34 505 H05K 3/34 512C 512 3/46 Q // H05K 3/46 B23K 101:40 B23K 101:40 H01L 23/12 P Fターム(参考) 5E319 AA03 AB05 AC01 AC02 AC15 AC16 AC17 AC20 BB04 BB05 CC33 CD04 CD26 GG03 GG09 GG15 5E336 AA04 BB03 BB11 CC32 CC44 DD39 EE03 GG06 GG09 5E346 AA06 AA12 AA15 AA32 AA43 AA51 BB16 CC08 EE15 FF45 GG25 HH11 HH31 5F067 AA16 AB07 BB20 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/34 505 H05K 3/34 512C 512 3/46 Q // H05K 3/46 B23K 101: 40 B23K 101 : 40 H01L 23/12 PF term (reference) 5E319 AA03 AB05 AC01 AC02 AC15 AC16 AC17 AC20 BB04 BB05 CC33 CD04 CD26 GG03 GG09 GG15 5E336 AA04 BB03 BB11 CC32 CC44 DD39 EE03 GG06 GG09 5E346 AA06 AA12 BB15 GG25 HH11 HH31 5F067 AA16 AB07 BB20

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 配線導体を有する有機材料系の絶縁基板
の上面に前記配線導体に接続された半田バンプを設ける
とともに、前記絶縁基板の下面に前記配線導体に接続さ
れたリードピンを半田を介して接合して成るピン付き配
線基板であって、前記半田バンプが67〜82重量%の
鉛と5〜20重量%の錫と5〜15重量%のアンチモン
と8〜20重量%のビスマスとの合金から成り、前記リ
ードピンを接合する半田が70〜85重量%の鉛と5〜
20重量%の錫と5〜15重量%のアンチモンとから成
ることを特徴とするピン付き配線基板。
An organic material-based insulating substrate having a wiring conductor is provided with a solder bump connected to the wiring conductor on an upper surface, and a lead pin connected to the wiring conductor is formed on a lower surface of the insulating substrate via solder. A wiring board with pins formed by bonding, wherein the solder bumps are an alloy of 67 to 82% by weight of lead, 5 to 20% by weight of tin, 5 to 15% by weight of antimony, and 8 to 20% by weight of bismuth. And the solder for joining the lead pins is 70 to 85% by weight of lead and 5 to 5% by weight.
A wiring board with pins, comprising 20% by weight of tin and 5 to 15% by weight of antimony.
【請求項2】 配線導体を有する有機材料系の絶縁基板
の上面に前記配線導体に接続された半田バンプを設ける
とともに、前記絶縁基板の下面に前記配線導体に接続さ
れたリードピンを半田を介して接合して成るピン付き配
線基板上に電子部品をその電極と前記半田バンプとを接
合することにより搭載して成る電子装置であって、前記
半田バンプが67〜82重量%の鉛と5〜20重量%の
錫と5〜15重量%のアンチモンと8〜20重量%のビ
スマスとの合金から成り、前記リードピンを接合する半
田が70〜85重量%の鉛と5〜20重量%の錫と5〜
15重量%のアンチモンとから成ることを特徴とする電
子装置。
2. An organic material-based insulating substrate having a wiring conductor is provided with a solder bump connected to the wiring conductor on an upper surface thereof, and a lead pin connected to the wiring conductor is formed on a lower surface of the insulating substrate via solder. An electronic device in which an electronic component is mounted on a bonded wiring board with pins by bonding an electrode thereof and the solder bump, wherein the solder bump has 67 to 82% by weight of lead and 5 to 20% by weight. % Of tin, 5 to 15% by weight of antimony and 8 to 20% by weight of bismuth, and the solder joining the lead pins is 70 to 85% by weight of lead, 5 to 20% by weight of tin and 5% by weight. ~
An electronic device comprising 15% by weight of antimony.
JP2001138881A 2001-03-21 2001-05-09 Wiring board with pin and electronic device using it Pending JP2002353394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001138881A JP2002353394A (en) 2001-03-21 2001-05-09 Wiring board with pin and electronic device using it

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001-80771 2001-03-21
JP2001080771 2001-03-21
JP2001138881A JP2002353394A (en) 2001-03-21 2001-05-09 Wiring board with pin and electronic device using it

Publications (1)

Publication Number Publication Date
JP2002353394A true JP2002353394A (en) 2002-12-06

Family

ID=26611674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001138881A Pending JP2002353394A (en) 2001-03-21 2001-05-09 Wiring board with pin and electronic device using it

Country Status (1)

Country Link
JP (1) JP2002353394A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300482A (en) * 2007-05-30 2008-12-11 Nec Toppan Circuit Solutions Inc Printed wiring board and manufacturing method thereof, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300482A (en) * 2007-05-30 2008-12-11 Nec Toppan Circuit Solutions Inc Printed wiring board and manufacturing method thereof, and semiconductor device

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