JP2010251688A - Component built-in printed wiring board and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in printed wiring board which has high reliability without causing a defect of electrical connection of an inner layer even when soldering an electronic component onto an outer layer. <P>SOLUTION: The component built-in printed wiring board is provided with a land wiring pattern 56b which has a land opening hole on a first insulating resin layer, a chip component is bonded on a wiring pattern with a non-conductive adhesive resin film 7, an electrode 31 of the chip component is abutted on the land, an opening prepreg on which a prepreg opening portion to avoid the chip component is formed on the insulating resin layer and wiring pattern, and a filled via-hole 55b electrically connects a part of land and an electrode on a land opening hole with metal plating from the first insulating resin layer side. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a component built-in printed wiring board having a multilayer wiring layer and a multilayer chip component installation layer, and a method for manufacturing the same.

  2. Description of the Related Art In recent years, a printed wiring board on which a semiconductor device is mounted has been required due to the development of semiconductor mounting technology, and a multilayer printed wiring board having a high-density and high-precision wiring layer is required. As one method for realizing high density, a printed wiring board incorporating an integrated circuit chip has been developed. In a conventional method for manufacturing a component-embedded printed wiring board, as disclosed in Patent Document 1, bump electrodes of an integrated circuit chip are connected to lands of a base plate by solder. Then, the component built-in printed wiring board is manufactured by laminating the component-attached inner layer substrate on which the integrated circuit chip is installed via the interlayer insulating layer.

JP 2005-142178 A

  This conventional printed wiring board with built-in components solders a plurality of built-in integrated circuit chip bump electrodes to the inner land by a solder reflow process in the soldering process of the components to the outer layer of the built-in printed wiring board. There was a problem that the solder which had been melted may be remelted, and the solders of adjacent lands may come into contact with each other to short-circuit the lands of the inner layer with the solder. In order to avoid this problem, there can be an improvement measure to solder the electrode of the electronic component to the land with high-temperature solder. In that case, since the soldering temperature of the high-temperature solder is high, the base plate to which the electronic component is soldered is damaged. There is a problem that the quality of the printed wiring board with built-in components deteriorates.

  In addition, there is a technique in which a bump electrode of an integrated circuit chip is bonded to a land of a base plate by gold-gold bonding or gold-solder bonding. However, this bonding has a problem that connection reliability is inferior to metal plating connection.

  The present invention has been devised in view of the above problems, and an object thereof is to electrically connect bump electrodes of an integrated circuit chip to lands of a base plate with high connection reliability without increasing manufacturing costs.

In order to solve the above problems, the present invention forms a wiring pattern having lands on a first insulating resin layer, and adheres a chip component to the wiring pattern with a non-conductive adhesive resin film. A first step of bringing the electrode of the chip component into contact with the land, and an opening prepreg in which a prepreg opening for avoiding the chip component is formed on the first insulating resin layer and the wiring pattern, and the opening Install an inner layer substrate with an opening to avoid the chip parts on the prepreg, install a B-stage thermosetting insulating resin film on the inner layer substrate, laminate, heat and pressurize the printed wiring board A second step of manufacturing a body, and through the land and the non-conductive adhesive resin film by laser drilling from the first insulating resin layer side of the printed wiring board intermediate body. Forming a via hole exposing a part of the electrode and a part of the electrode, and forming a via hole for electrically connecting the land to the electrode by metal plating the via hole. It is a manufacturing method of the component built-in printed wiring board characterized by having a process at least.

  According to another aspect of the present invention, there is provided a method of manufacturing a component built-in printed wiring board, wherein the chip component is an integrated circuit chip and the electrode is a bump electrode. .

  According to the present invention, in the manufacturing method of the component built-in printed wiring board, in the first step, the land is formed into a pattern having a land opening hole, and the laser drilling is performed in the third step. A method of manufacturing a printed wiring board with built-in components, wherein a via hole for exposing the electrode is formed through a land opening hole.

  According to the present invention, in the manufacturing method of the component-embedded printed wiring board, in the first step, the land is formed with a copper pattern having a thickness of 10 μm to 15 μm in the first step, In the third step, a via-hole for exposing the electrode is formed by penetrating the copper pattern of the land by the laser drilling.

  In the method for manufacturing a printed wiring board with a built-in component according to the present invention, the inner layer substrate has an inner layer through filled via hole, and the third step passes through the inner layer from both sides of the printed wiring board intermediate. A second via hole for reaching a filled via hole is formed, and the fourth step is a method of manufacturing a component built-in printed wiring board, wherein via hole plating is formed in the second via hole.

  The present invention further includes a land wiring pattern having land opening holes on the first insulating resin layer, wherein a chip component is adhered to the wiring pattern by a non-conductive adhesive resin film, and the electrode of the chip component is An opening prepreg which is in contact with the land and has an prepreg opening for avoiding the chip component on the insulating resin layer and the wiring pattern; and an inner layer substrate having an opening for avoiding the chip component; A printed wiring board with a built-in component, comprising a via hole in which a part of the land and the electrode on the land opening hole are electrically connected by metal plating from the insulating resin layer side of 1.

  According to another aspect of the invention, there is provided the printed wiring board with built-in components, wherein the chip component is an integrated circuit chip and the electrodes are bump electrodes.

  Further, the present invention provides the above-described component built-in printed wiring board, further comprising a thermosetting insulating resin layer on the inner layer substrate, the inner layer substrate having an inner layer through-filled via hole, and the first layer under the inner layer substrate. A via hole plating reaching the inner through-hole filled via hole from the lower side of one insulating resin layer and a via hole plating reaching the inner through-hole filled via hole from the upper side of the thermosetting insulating resin layer on the inner layer substrate. This is a printed wiring board with built-in components.

  In the component built-in printed wiring board of the present invention, the bump electrode of the integrated circuit chip and the land of the base plate are connected by metal plating. Therefore, when soldering this component built-in printed wiring board to another printed wiring board, Even with the heat treatment, the connection strength between the bump electrode and the land does not change, and there is an effect that a highly reliable electrical connection can be obtained.

It is sectional drawing which shows typically the manufacturing process of the baseplate of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the inner layer board | substrate with components of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the printed wiring board intermediate body of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the printed wiring board intermediate body of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention. It is sectional drawing which shows typically the manufacturing process of the component built-in printed wiring board of the 3rd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
<First Embodiment>
(Process 1)
As shown in FIG. 1A, a metal plate is used as the support substrate 1, for example, a 250 μm copper plate is used as the support substrate 1, and the support substrate 1 is roughened by CZ processing or the like. The roughening treatment may be a sand blast treatment with an abrasive or a blackening treatment by oxidation-reduction treatment or a perhydrosulfuric acid based soft etching treatment. Next, the insulating resin layer 2 is thermocompression bonded to the support substrate 1 by roll lamination or lamination press. An epoxy resin having a thickness of 20 μm to 30 μm is roll-laminated. As the insulating resin layer 2, an insulating resin layer containing a reinforcing material such as glass fiber, glass flake, or filler can be used. In particular, the insulating resin layer 2 is subjected to thermal stress due to the subsequent process many times, and the crack failure is likely to occur inside due to the thermal stress. There is an effect of strengthening the insulating resin layer 2 and preventing crack defects. In addition, it is also possible to use the film-like insulating resin layer 2 alone without using the support substrate 1.

  As a resin material of the insulating resin layer 2, epoxy resin, bismaleimide-triazine resin (hereinafter referred to as BT resin), polyimide resin, PPE resin, phenol resin, PTFE resin, silicon resin, polybutadiene resin, polyester resin, melamine resin, Organic resins such as urea resin, PPS resin, and PPO resin can be used. In addition, these resins can be used alone, or a combination of resins such as mixing a plurality of resins or preparing a compound can be used. Furthermore, the insulating resin layer 2 in which a glass fiber reinforcing material is mixed into these materials can be used. As the reinforcing material, an aramid nonwoven fabric, an aramid fiber, or a polyester fiber can be used.

(Process 2)
Next, the surface of the insulating resin layer 2 is roughened as necessary. In general, wet processes such as surface roughening with an oxidizing agent such as an aqueous solution of chromic acid or permanganate, and dry processes such as plasma treatment or ashing treatment are effective. Next, a plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm is formed on the entire surface of the insulating resin layer 2 by electroless copper plating. Next, as shown in FIG. 1B, the wiring pattern portion 5 is opened, and a pattern of the plating resist 4 in which the plating base conductive layer 3 is exposed at that portion is formed. Next, as shown in FIG. 1C, copper plating is applied to the surface of the plating base conductive layer 3 exposed at the wiring pattern portion 5 by electrolytic copper plating using the plating base conductive layer 3 as an electrode to a thickness of 15 μm. A thick wiring pattern 6 is formed. Next, the plating resist 4 is peeled off. Next, as shown in FIG. 1 (d), the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm remaining on the insulating resin layer 2 is removed by a perhydrosulfuric acid-based flash etching process, and the insulating resin is removed. The base plate 10 having the wiring pattern 6 formed on the layer 2 is manufactured. Here, in the wiring pattern 6, a wiring pattern 6 including a donut-shaped land 6 b having a land opening hole 6 a having a diameter of 30 μm to 60 μm is formed at a position where the bump electrode 31 of the integrated circuit chip 30 is installed. . The land opening 6a is formed to have a size that allows the copper surface of the land 6b to be exposed by laser drilling when laser drilling in the subsequent step 7 is performed.

(Modification 1)
Although the method for forming the wiring pattern 6 in the above step 2 is a semi-additive method, the wiring pattern 6 can be similarly formed by the following manufacturing method. That is, first, after the surface of the insulating resin layer 2 is roughened, the plating base conductive layer 3 is formed by electroless copper plating, and second, electrolytic copper plating is applied to the entire surface of the plating base conductive layer 3 by 12 μm. The conductor layer added with the thickness of is formed, and thirdly, an etching resist pattern is formed on the surface of the conductor layer to etch the conductor layer to form the wiring pattern 6. Fourth, the etching resist is removed. The wiring pattern 6 can be formed also by the above subtractive construction method, and the base plate 10 of FIG.1 (d) can be manufactured.

(Process 3)
Next, as shown in FIG. 2A, an NCF (Non Conductive Film) is pasted on the insulating resin layer 2 and the wiring pattern 6 in the installation area of the integrated circuit chip 30 of the base plate 10, or the NCP (Non Conductiveresin Paste) is applied to form a non-conductive adhesive resin film 7. Next, as shown in FIG. 2B, an integrated circuit chip 30 having a bump electrode 31 of a metal such as copper or gold is formed on the non-conductive adhesive resin film 7 with an integrated circuit chip 30 having a height of 300 μm or less. The non-conductive adhesive resin film 7 is caused to flow by intruding the metal bump electrode 31 by face-down thermocompression bonding, and the metal bump electrode 31 is brought into contact with the wiring pattern 6 under the non-conductive adhesive resin film 7. In this way, the component-attached inner layer substrate 20 on which the non-conductive adhesive resin film 7 is formed is produced.

  Next, as a roughening treatment of the surface of the copper wiring pattern 6 on the component inner layer substrate 20 of FIG. 2B, 2 mol or more of alkanolamine is contained per 1 mol of fatty acid carboxylic acid, and a copper ion source By roughening with a microetching agent containing a halogen ion source, and then contacting the surface of the wiring pattern 6 with an aqueous solution containing an azole compound and an organic acid, a thick film of the azole compound is formed on the surface of the wiring pattern 6. A treatment for improving the adhesiveness of the resin when forming an insulating resin layer to be described later is performed. Since the microetching agent in this process has low corrosivity, it can be roughened without damaging the wiring pattern 6. Alternatively, as the roughening treatment of the surface of the copper wiring pattern 6, blackening treatment by oxidation-reduction treatment or perhydrosulfuric acid based soft etching treatment may be performed.

(Process 4)
Next, as shown in FIG. 3, an opening prepreg having a prepreg opening 41 of the size of the integrated circuit chip 30 formed in a predetermined position of the prepreg having a thickness of about 40 μm by drilling, punching, laser processing or the like. 40 is formed. Next, an opening 8 a having a size of the integrated circuit chip 30 is formed in the inner layer substrate 8 having a thickness of about 60 μm. Here, since the prepreg opening 41 and the opening 8a are processed with holes according to the size of the integrated circuit chip 30, when forming the printed wiring board intermediate 50 to be described later, during heating and pressure molding There is an effect that it is possible to prevent the pressurizing pressure from being concentrated on the integrated circuit chip 30. The insulating material of the opening prepreg 40 has a small coefficient of thermal expansion in the direction of the substrate surface after curing (thermal expansion coefficient at 30 to 120 ° C. tested according to JIS-C6481) of about 8 to 12 × 10 −6 / Kelvin. A material having a high Tg with a glass transition temperature Tg value of about 160 to 170 ° C. obtained by testing under processing conditions TMA is used. By using a material having this characteristic, there is an effect that it is consistent with the characteristic of the insulating resin plate of the base plate 10, and in the subsequent manufacturing process, no stress remains in the substrate and the substrate is not warped and the manufacturing is stabilized.

(Process 5)
Then, as shown in FIG. 3, the inner layer substrate 20 with components including the support substrate 1, and the opening prepreg 40 and the inner layer substrate 8 avoiding the integrated circuit chip 30 by the prepreg opening 41 and the opening 8a are stacked thereon, On top of this, a B-stage thermosetting insulating resin film 42 is laminated and laminated. ABF (trade name, manufactured by Ajinomoto Co., Inc.) was used as the thermosetting insulating resin film 42 in the B stage state. In the ABF, a thermosetting insulating resin layer 43 (thickness: 40 μm) is formed on the surface of a PET (polyethylene terephthalate) film 44. The surface of the thermosetting insulating resin layer 43 of this thermosetting insulating resin film 42 is placed toward the inner layer substrate 8 having the opening 8a, and the degree of vacuum is 133 Pa or less, and the treatment is performed at 85 to 95 ° C. for 40 to 60 seconds. After that, laminating was performed by returning to atmospheric pressure, and the thermosetting insulating resin layer 43 was filled in the opening 8a.

  Next, after peeling the PET film 44, the printed wiring board intermediate body 50 was manufactured as shown in FIG. 4 by stacking using a vacuum press. The condition of this lamination process is that the degree of vacuum between about 30 minutes and 60 minutes from the start of lamination is reduced to 4 kPa or less, and then returned to atmospheric pressure. Pressurization of the substrate is performed at 0.5 MPa for 10 to 30 minutes from the start of lamination, and then the pressure is increased to 2 to 3 MPa. The hot press temperature of the vacuum press is raised from 80 ° C. to 130 ° C. in 1.5 to 2.5 minutes, and after returning the degree of vacuum to atmospheric pressure, the substrate temperature reaches 170 ° C. or higher. When it reaches, it is laminated while maintaining the heating holding time of 40 minutes or more (for example, 45 minutes). The degree of vacuum is returned to the atmospheric pressure before the substrate temperature reaches 170 ° C. or higher. However, if the degree of vacuum is not returned to the atmospheric pressure at this timing, there is a problem that bubbles are generated in the resin. Further, if the substrate temperature is not kept at 170 ° C. or more for 40 minutes or more, the filling property by the resin of the gap between the integrated circuit chip 30 and the opening prepreg 40 of the chip component 30a of the printed wiring board intermediate body 50 by the resin from the opening prepreg 40 is achieved. This causes a problem that makes it worse.

  During the heating and pressurization of this lamination, the resin melts from the opening prepreg 40 and has an effect of filling the gap between the integrated circuit chip 30. In this way, as shown in FIG. 4, the printed wiring board intermediate 50 in which the opening prepreg 40, the inner layer substrate 8, and the thermosetting insulating resin layer 43 are laminated on the inner layer substrate 20 on which the integrated circuit chip 30 is mounted on the base plate 10. Manufacturing.

(Modification 2)
Instead of the above process 5, the printed wiring board intermediate 50 can be formed by the following manufacturing process without using the thermosetting insulating resin film 42. That is, as shown in FIG. 3, the inner substrate 20 with components including the support substrate 1, and the opening prepreg 40 and the inner substrate 8 avoiding the integrated circuit chip 30 by the prepreg opening 41 and the opening 8a are stacked thereon, On top of that, a prepreg having a thickness of about 30 μm and a copper foil having a thickness of about 12 μm are stacked on top of each other and laminated by using a vacuum press. Resin melts from the opening prepreg 40 and fills the gap with the integrated circuit chip 30. Next, the thickness of the upper layer is about 12 μm
m copper foil is removed by quick etching. In this way, the printed wiring board intermediate body 50 having the thermosetting insulating resin layer 43 formed by curing the prepreg as shown in FIG. 4 can be manufactured.

(Step 6)
Next, as shown in FIG. 5A, the resin-coated copper foil is thermocompression bonded to the printed wiring board intermediate 50 by roll lamination or lamination press. For example, an insulating resin layer 52 such as an epoxy resin having a thickness of 20 μm to 30 μm and a copper foil with resin made of copper foil 51 are roll-laminated on the printed wiring board intermediate 50. As the insulating resin layer 52, an insulating resin layer containing a reinforcing material such as glass fiber, glass flake, or filler can be used. Next, as shown in FIG. 5B, the outer layer copper foil 51 and the copper plate support substrate 1 are removed by etching from the printed wiring board intermediate 50 laminated with the resin-coated copper foil. As a modification of this manufacturing method, the insulating resin layer 52 may be formed on the printed wiring board intermediate 50 by roll laminating only the resin film having no copper foil on the printed wiring board intermediate 50. it can.

(Step 7)
Next, as shown in FIG. 6A, a through-hole prepared hole 53 having a diameter of 0.06 mm to 2 mm is formed by drilling in the printed wiring board intermediate body 50 that has undergone the above manufacturing process. Next, a hole is drilled from below the insulating resin layer 2 with an ultraviolet laser such as a harmonic YAG laser or an excimer laser, or an infrared laser such as a carbon dioxide laser, so that the diameter of the land 6b of the wiring pattern 6 is 0. Non-conductive adhesive resin filled in the land opening hole 6a through the land opening hole 6a having a diameter of 0.03 mm to 0.06 mm while exposing the copper surface of the land 6b with a hole of 04 mm to 0.2 mm A via hole 54 is formed by making a hole in the film 7 to expose the bump electrode 31. Here, the land opening hole 6a can be formed smaller than the beam diameter of the processing laser, and only the small bump electrode 31 region is exposed from the land opening hole 6a, and the processing laser is formed in the other regions of the integrated circuit chip 30. Therefore, the load on the integrated circuit chip 30 during laser processing can be reduced. Further, there is an effect that the land opening hole 6a can be precisely aligned with the fine bump electrode 31.

(Step 8)
Next, the surface of the insulating resin layers 2 and 52 is roughened. For the roughening treatment, wet treatment such as permanganic acid treatment or dry treatment such as plasma desmear can be used. Next, plating catalyst provision and electroless copper plating are performed to form a plating underlayer (not shown). Next, a photosensitive layer is formed by applying a resist or a photosensitive dry film on the outside of the plating base layer, and a series of patterning processes such as pattern exposure and development are performed to form a plating resist pattern. Form. Next, the wiring pattern 56 is formed on the surfaces of the insulating resin layers 2 and 52 as shown in FIG. 6B by dipping in a copper sulfate plating bath and performing electrolytic copper plating using the plating base layer as a cathode. Then, a filled via hole 55 in which the via hole hole 54 is filled with copper plating is formed integrally with the wiring pattern 56, and a through hole plating 57 by copper plating is formed on the side wall surface of the through hole lower hole 53. Next, the plating resist pattern is peeled off, and the plating base layer located under the plating resist pattern is removed by flash etching to form a wiring pattern 56.

  Here, since the filled via hole 55 is formed by metal plating in the via hole hole 54 that reaches the bump electrode 31 through the land opening hole 6a formed in the land 6b, the bump electrode 31 of the integrated circuit chip 30 is formed by metal plating. Thus, there is an effect that the electrical connection with the bump electrode 31 can be improved. Further, since the filled via hole 55 is formed by plating also on the copper surface of the land 6b exposed in the via hole 54, it can be firmly connected to the land 6b. As a result, the bump electrode 31 and the land 6b are finally formed. There is an effect that electrical connection with high connection reliability can be obtained.

  In the above processing, the semi-additive method is used to form the wiring pattern 56, but the present invention is not limited to this. That is, first, a conductive layer is formed on the entire surface by electrolytic copper plating using the plating base layer on the surfaces of the insulating resin layers 2 and 5 as a cathode, and a filled via hole 55 and a through-hole plating 57 integral therewith are formed. Next, a photosensitive dry film is attached to the outside of the conductor layer formed on the entire surface to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form an etching resist pattern. Then, the conductor layer can be etched using the etching resist pattern as a protective film to form the wiring pattern 56 of FIG.

(Step 9)
Next, as shown in FIG. 7A, insulating resin layers 52b are formed on both surfaces of the substrate.
(Process 10)
Next, as shown in FIG. 7B, a via hole 54b is formed at a predetermined position of the insulating resin layer 52b.
(Step 11)
Next, as shown in FIG. 8A, a filled via hole 55b is formed in the via hole 54b by copper plating, and a wiring pattern 56b is formed on the surface of the insulating resin layer 52b. If necessary, the wiring pattern 56b having a desired number of layers is formed by repeating the formation of the insulating resin layer, the filled via hole 55b, and the wiring pattern 56b a predetermined number of times.

(Step 12)
Next, a CZ process is performed as a roughening process for the electrolytic plating of the wiring pattern 56b of the substrate. Next, a photosensitive solder resist is applied to a thickness of about 20 μm by spray coating, roll coating, curtain coating, or screen method, and dried to form a solder resist on the outer layer. Alternatively, a photosensitive dry film / solder resist is attached to the substrate by roll lamination to form a solder resist. Next, as shown in FIG. 8B, the solder resist is exposed and developed to open the external connection pad opening, and is cured by heating to form a solder resist pattern 58. Next, 3 μm or more of electroless Ni plating is formed in the external connection pad opening of the solder resist pattern 58, and 0.03 μm or more of electroless Au plating is formed thereon. The electroless Au plating can be formed to 1 μm or more. Further, it is possible to pre-coat with solder. Further, instead of electroless plating, electrolytic Ni plating can be formed to 3 μm or more, and electrolytic Au plating can be formed thereon to 0.5 μm or more. Alternatively, an organic rust preventive film such as tough ace can be formed in addition to the plating treatment.
(Step 13)
The printed circuit board with built-in components is obtained by processing the outer shape of the finished board with a dicer or the like.

  In this embodiment, the through-hole plating 57 shown in FIG. 6B can be formed by a filling-type through-hole plating 57 that fills the entire space of the through-hole lower hole 53.

  In the present embodiment, the integrated circuit chip 30 is installed face-down with the NCF or NCP non-conductive adhesive resin film 7 adhered to the base plate 10 and then landed on the land 6b with which the bump electrode 31 of the integrated circuit chip 30 contacts. An opening hole 6a is formed, and a hole 54 for a via hole that exposes the bump electrode 31 through the land opening hole 6a and exposes the metal surface of the land 6b by laser drilling from the insulating resin layer 2 side of the base plate 10 is formed. Form. Then, the filled via hole 55 filled with metal plating has an effect of making a strong and reliable electrical connection between the bump electrode 31 and the land 6b.

<Second Embodiment>
In the second embodiment of the present invention, in step 2 corresponding to step 2 of the first embodiment, the land 6b of the wiring pattern 6 does not form the land opening hole 6a and has a thickness of about 10 μm to 15 μm. A copper land 6b is formed. Then, in step 7 corresponding to step 7 of the first embodiment, a via hole hole for exposing the bump electrode 31 by penetrating the copper pattern of the land 6b having a thickness of about 10 μm to 15 μm with a laser drilling laser. 54 is formed. The manufacturing process other than these manufactures the component built-in printed wiring board in the same manufacturing process as in the first embodiment.

<Third Embodiment>
In the third embodiment of the present invention, the inner layer substrate 8 in which the inner layer through filled via hole 59 is formed is used as the inner layer substrate 8 used in step 4 of the first embodiment. Similarly to the second modification of the first embodiment, a B-stage resin in which a prepreg 43b containing a filler such as glass cloth or organic fiber cloth is used as the thermosetting insulating resin 43 is layered on the copper foil 60. A thermosetting insulating resin film 42 of a copper foil with resin is used.

(Step 1 to Step 3)
As shown in the lower part of FIG. 9, an insulating resin layer having a thickness of 20 μm to 30 μm is formed on the support substrate 1 by the same process as the process 1 to the process 3 shown in FIGS. 1 to 2 of the first embodiment. 2 is manufactured, and the base plate 10 is formed on which the wiring pattern 6 having the pattern of the land 6b having the land opening hole 6a therein is formed. As the base plate 10, a manufacturing method using the base plate 10 using the insulating resin layer 2 alone without using the support substrate 1 is also possible. A bump electrode 31 of a chip component 30a such as an integrated circuit chip 30, a laminated ceramic capacitor chip or a resistor chip is formed on the land 6b and the land opening hole 6a of the wiring pattern 6 of the base plate 10 by a non-conductive adhesive resin film 7. An electrode 31a such as a terminal is adhered and brought into contact with each other to form the structure of FIG. 2B of the first embodiment.

  The chip component 30 a is precisely aligned with the fine land 6 b while being observed with the imaging camera, and is adhered to the surface of the insulating resin layer 2 and the wiring pattern 6 through the non-conductive adhesive resin film 7. Accordingly, there is an effect that the chip component 30a can be accurately positioned and installed on the fine land 6b. The effect of being able to form a small gap between the prepreg opening 41 of the opening prepreg 40 into which the chip component 30a is inserted later and the chip component 30a by precisely positioning the chip component 30a on the wiring pattern 6 and installing it. There is. In addition, there is an effect that the gap between the chip part 30a and the shape of the opening 8a of the inner layer substrate 8 formed in consideration of the alignment error of the outer shape of the chip part 30a can be formed. As described above, the gap between the chip component 30a and the opening 8a of the inner layer substrate 8 can be reduced, so that the amount of resin flowing out from the prepreg during stacking can be reduced in order to fill the gap. Therefore, at the time of lamination, the thickness of the prepreg 43b of the thermosetting insulating resin film 42 of the B stage that is stacked on the inner layer substrate 8 can be reduced, thereby reducing the thickness of the substrate.

(Process 4)
Next, as shown in FIG. 9, an opening in which a prepreg opening 41 having the size of the chip component 30a is formed at a predetermined position of a prepreg having a thickness of 30 μm to 40 μm by drilling, punching, laser processing or the like. A prepreg 40 is formed. The opening prepreg 40 is overlaid on the insulating resin layer 2 and the wiring pattern 6 on the base plate 10 by inserting the chip component 30 a into the prepreg opening 41. Further, a through hole having a diameter of 40 μm to 150 μm is formed in the inner substrate 8 having a thickness of about 60 μm, and a columnar inner layer through filled via hole 59 formed by filling the through hole with copper plating is formed. Further, an opening 8 a having a size of the chip component 30 a is formed in the inner layer substrate 8. By aligning the inner layer substrate 8 so that the chip component 30a is fitted into the opening 8a and overlapping the opening prepreg 40, the inner layer substrate 8 is placed on the insulating resin layer 2 and the wiring pattern 6 on the base plate 10. A structure in which the opening prepreg 40 and the inner layer substrate 8 are stacked thereon is formed.

  Here, since the prepreg opening 41 and the opening 8a are processed with holes according to the size of the chip component 30a, when forming the printed wiring board intermediate 50 to be described later, heating and pressure molding are performed. There is an effect that the pressurizing pressure can be prevented from being concentrated on the chip component 30a. The insulating material of the opening prepreg 40 has a small coefficient of thermal expansion in the direction of the substrate surface after curing (thermal expansion coefficient at 30 to 120 ° C. tested according to JIS-C6481) of about 8 to 12 × 10 −6 / Kelvin. A material having a high Tg with a glass transition temperature Tg value of about 160 to 170 ° C. obtained by testing under processing conditions TMA is used. By using a material having this characteristic, there is an effect that it is consistent with the characteristic of the insulating resin plate of the base plate 10, and in the subsequent manufacturing process, no stress remains in the substrate and the substrate is not warped and the manufacturing is stabilized. In particular, in the inner substrate 8, since the position of the chip component 30a to be fitted into the opening 8a can be precisely aligned with the wiring pattern 6 and the installation positional error is small, the opening that allows for the positional deviation of the chip component 30a. There is an effect that the gap between 8a and the chip component 30a can be designed to be small. Accordingly, there is an effect that the gap between the opening 8a and the chip component 30a can be filled with a small amount of insulating resin.

(Process 5)
Then, as shown in FIG. 9, the inner layer substrate 20 with the component including the support substrate 1, and the opening prepreg 40 and the inner layer substrate 8 avoiding the chip component 30a by the prepreg opening 41 and the opening 8a are stacked thereon, A thermosetting insulating resin film 42 in a B-stage state having a thickness of 30 μm is stacked thereon. As the thermosetting insulating resin film 42 in the B-stage state, as in Modification 2 of the first embodiment, a copper foil with resin in which a prepreg 43b with a thickness of 30 μm is superimposed on a copper foil 60 with a thickness of 12 μm is used. Use. The surface of the prepreg 43b of the thermosetting insulating resin film 42 is placed toward the inner layer substrate 8 having the opening 8a.

  Next, lamination is performed using a vacuum press, and the resin of the opening prepreg 40 and the prepreg 43b is heated and fluidized to fill the opening 8a with the resin, and is cured to form the thermosetting insulating resin layer 43. The printed wiring board intermediate 50 is manufactured as shown in FIG. 10 by removing the copper foil 60 by quick etching after the lamination. The condition of this lamination process is that the degree of vacuum between about 30 minutes and 60 minutes from the start of lamination is reduced to 4 kPa or less, and then returned to atmospheric pressure. Pressurization of the substrate is performed at 0.5 MPa for 10 to 30 minutes from the start of lamination, and then the pressure is increased to 2 to 3 MPa. The hot press temperature of the vacuum press is raised from 80 ° C. to 130 ° C. in 1.5 to 2.5 minutes, and after returning the degree of vacuum to atmospheric pressure, the substrate temperature reaches 170 ° C. or higher. When it reaches, it is laminated while maintaining the heating holding time of 40 minutes or more (for example, 45 minutes). The degree of vacuum is returned to the atmospheric pressure before the substrate temperature reaches 170 ° C. or higher. However, if the degree of vacuum is not returned to the atmospheric pressure at this timing, there is a problem that bubbles are generated in the resin. In addition, if the substrate temperature is not maintained at 170 ° C. or higher for 40 minutes or more, the filling property by the resin of the gap between the chip component 30a of the printed wiring board intermediate body 50 by the resin from the opening prepreg 40 and the opening prepreg 40 is deteriorated. Arise.

During the heating and pressurization of this lamination, the resin melts from the opening prepreg 40 and the prepreg 43b, and the gap between the chip component 30a is filled. Thus, as shown in FIG. 10, the printed wiring board intermediate 50 in which the opening prepreg 40, the inner layer substrate 8, and the thermosetting insulating resin layer 43 are laminated on the inner layer substrate 20 on which the chip component 30 a is mounted on the base plate 10. To manufacture. Since the chip component 30a can be precisely aligned with the wiring pattern 6 by the above manufacturing process, the gap between the chip component 30a and the opening 8a of the inner layer substrate 8 can be reduced. Therefore, since the amount of resin flowing out from the prepreg at the time of stacking can be reduced to fill the gap, the chip component 30a and the opening 8a of the inner substrate 8 can be obtained only by melting the resin of the opening prepreg 40 at the time of stacking. It is also possible to fill the gaps. Therefore, it is also possible to manufacture the printed wiring board intermediate body 50 that does not use the thermosetting insulating resin film 42. That is, it is also possible to manufacture the printed wiring board intermediate 50 in which the gap between the chip component 30a and the opening 8a of the inner substrate 8 is filled by only melting the resin of the opening prepreg 40.

(Step 6)
Next, as shown in FIG. 11 (a), a copper foil with resin is thermocompression bonded to the printed wiring board intermediate body 50 by roll lamination or lamination press. For example, an insulating resin layer 52 such as an epoxy resin having a thickness of 20 μm to 30 μm and a copper foil with resin composed of the copper foil 51 are roll-laminated. As the insulating resin layer 52, an insulating resin layer containing a reinforcing material such as glass fiber, glass flake, or filler can be used. Next, as shown in FIG. 11B, the copper foil 51 as the outer layer of the printed wiring board intermediate 50 and the support substrate 1 of the copper plate are removed by etching. Here, the insulating resin layer 52 can also be formed by roll laminating a resin film that does not use copper foil.

(Step 7)
Next, as shown in FIG. 12A, a hole is formed from below the insulating resin layer 2 below the printed wiring board intermediate 50 with an ultraviolet laser such as a harmonic YAG laser or an excimer laser, or an infrared laser such as a carbon dioxide gas laser. By processing, a via hole 54 having a bottom surface diameter of 40 μm and an opening diameter of 60 μm is formed on the land 6 b of the wiring pattern 6 on the land 6 b, and the land 6 b is formed on the bottom surface of the hole. The copper surface and the electrode 31a are exposed. That is, the via hole 54 penetrates the land opening hole 6a having a diameter of 0.03 mm to 0.06 mm, and opens the non-conductive adhesive resin film 7 filled in the land opening hole 6a to expose the electrode 31a. Let

  Further, similarly, a hole for a via hole reaching the lower surface of the inner layer through filled via hole 59 of the inner layer substrate 8 through the insulating resin layer 2 and the opening prepreg 40 from below the printed wiring board intermediate body 50 by drilling with a laser. 61 is formed. The via hole 61 is formed such that the bottom of the funnel-shaped hole has a diameter of 80 μm and the opening has a diameter of 100 μm, and the lower surface of the inner layer filled filled via hole 59 is exposed at the bottom of the hole. Further, a via hole reaching the upper surface of the inner layer through filled via hole 59 of the inner layer substrate 8 through the insulating resin layer 52 and the thermosetting insulating resin layer 43 from above the printed wiring board intermediate 50 by drilling with a laser. A hole 61 is formed. As a result, the upper surface of the inner layer through filled via hole 59 is exposed at the bottom surface of the via hole 61. Here, the upper and lower via-hole holes 61 of the inner layer through-filled via hole 59 have the same thickness, the insulating resin layer 2 or the insulating resin layer 52 having a thickness of 20 μm to 30 μm, and a thickness of 30 μm to 40 μm. Since the opening prepreg 40 or the thermosetting insulating resin layer 43 made of the prepreg 43b is formed so as to penetrate, the upper and lower via hole holes 61 can be quickly processed in a continuous process without changing the manufacturing conditions of the via hole holes 61. effective.

(Step 8)
Next, a roughening process is performed on the surfaces of the insulating resin layer 2 and the insulating resin layer 52. For the roughening treatment, wet treatment such as permanganic acid treatment or dry treatment such as plasma desmear can be used. Next, plating catalyst provision and electroless copper plating are performed to form a plating underlayer (not shown). Next, a photosensitive layer is formed by applying a resist or a photosensitive dry film on the outside of the plating base layer, and a series of patterning processes such as pattern exposure and development are performed to form a plating resist pattern. Form. Next, the wiring pattern 56 is formed on the surfaces of the insulating resin layers 2 and 52 as shown in FIG. 12B by dipping in a copper sulfate plating bath and performing electrolytic copper plating using the plating base layer as a cathode. Then, a filled via hole 55 in which the via hole 54 is filled with copper plating is formed integrally with the wiring pattern 56, and a via hole plating 62 is formed on the side wall surface of the via hole 61 by copper plating. Next, the plating resist pattern is peeled off, and the plating base layer located under the plating resist pattern is removed by flash etching to form a wiring pattern 56.

Here, since the filled via hole 55 is formed by metal plating in the via hole hole 54 that reaches the electrode 31a through the land opening hole 6a in the land 6b, the filled via hole 55 is firmly attached to the electrode 31a of the chip component 30a by metal plating. Electrical connection can be achieved, and the reliability of electrical connection with the electrode 31a can be increased. Further, since the filled via hole 55 is also formed by electrolytic copper plating on the copper surface of the land 6b exposed in the via hole 54, it can be firmly connected to the land 6b. There is an effect that electrical connection with high connection reliability in which 31a and land 6b are firmly connected by plating can be obtained. As a result, there is an effect that the electrode 31a of the chip component 30a is electrically connected to the wiring pattern 6 on the insulating resin layer 2 closest to the chip component 30a with higher reliability than soldering. In addition, this electrical connection is formed in the wiring pattern 6 with a pattern of the land 6b having a smaller size than in the prior art in which the electrode 31a of the chip component 30a is electrically connected to the land 6b using a large amount of solder in the prior art. By doing so, it is possible to make a strong electrical connection, so that the wiring density of the wiring pattern 6 on the insulating resin layer 2 can be increased.

  Further, since the wiring pattern can be formed on the wiring pattern 6 on the upper surface of the insulating resin layer 2 in contact with the electrode 31a and the wiring pattern 56 to be formed later on the lower surface of the insulating resin layer 2, high wiring can be obtained by using both wiring layers. There is an effect that density can be obtained. Further, since the filled via hole 55 connected to the electrode 31a is formed through the insulating resin layer 2, the filled via hole 55 has an effect of having a sufficient height having a thickness equal to or larger than the thickness of the insulating resin layer 2. Further, the filled via hole 55 has a land 6b firmly connected thereto supporting the insulating resin layer 2 from above, and a wiring pattern 56 formed integrally with the filled via hole 55 supports the insulating resin layer 2 from below to insulate. Since the structure that supports the resin layer 2 from above and below is configured, the resin layer 2 is fixed to the insulating resin layer 2 with sufficiently strong mechanical strength, can be formed into a mechanically reliable structure, and the electrode 31a can be supported by the strong structure. As a result, the electrode 31a can be firmly fixed.

  In the above processing, the semi-additive method is used to form the wiring pattern 56, but the present invention is not limited to this. That is, first, a conductive layer is formed on the entire surface by electrolytic copper plating using the plating base layer on the surfaces of the insulating resin layers 2 and 5 as the cathode, and a filled via hole 55 and a via hole plating 62 integrated therewith are formed. Next, a photosensitive dry film is attached to the outside of the conductor layer formed on the entire surface to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form an etching resist pattern. Then, the conductor layer can be etched using the etching resist pattern as a protective film to form the wiring pattern 56 of FIG.

(Step 9)
Next, as shown in FIG. 13 (a), a copper foil with a resin in which a copper foil 64 having a thickness of 9 μm is laminated on a prepreg having a thickness of 30 μm is stacked on both surfaces of the substrate, and thermocompression-bonded by a laminating press. The insulating resin layer 63 is cured.
.
(Process 10)
Next, as shown in FIG. 13B, the both sides of the base material are punched with a carbon dioxide laser so that the copper foil 64 having a thickness of 9 μm and the underlying insulating resin layer 63 are penetrated to form a funnel-like shape. A via hole 54b having a hole bottom diameter of 55 μm and an opening diameter of 75 μm is formed. Next, the copper foil 64 is removed by quick etching.
(Step 11)
Next, as shown in FIG. 14A, a filled via hole 55 b is formed in the via hole 54 b by copper plating, and a wiring pattern 56 b is formed on the surface of the insulating resin layer 63. If necessary, the wiring pattern 56b having a desired number of layers is formed by repeating the formation of the insulating resin layer, the filled via hole 55b, and the wiring pattern 56b a predetermined number of times.

(Step 12)
Next, in the same manner as in the first embodiment, a solder resist pattern 58 is formed on the outer layer, an electroless Ni plating is formed at 3 μm or more on the external connection pad opening, and an electroless Au plating is formed thereon. 0.03 μm or more is formed.
(Step 13)
The printed circuit board with built-in components is obtained by processing the outer shape of the finished board with a dicer or the like.

  In the third embodiment, since the inner layer substrate 8 having the inner layer through filled via hole 59 is used, it is not necessary to form the through hole lower hole 53 penetrating the printed wiring board intermediate body 50 containing the chip component 30a, and the printed wiring board. The via hole plating 61 is formed by laser drilling from both sides of the intermediate body 50 to reach the inner layer through filled via hole 59 to form the via hole plating 62, whereby the printed wiring board intermediate body 50 can be made conductive. As a result, the mismatch between the processing position of the through-hole lower hole 53 and the processing position of the via hole 54 formed by laser drilling is reduced, and the alignment accuracy between the via hole 54 and the wiring pattern 56 is improved. There is an effect that a good printed wiring board with built-in components is obtained.

  According to the manufacturing method of the first to third embodiments, the chip component 30a such as an integrated circuit chip is face down, and the electrode 31a such as the bump electrode is insulated by the non-conductive adhesive resin film 7 of NCF or NCP. The electrode 31a is formed by a filled via hole 55 having a structure in contact with the land 6b on the layer 2 and penetrating through the land 6b and reaching the electrode 31a through the land 6b and filled with metal plating. Thus, a component built-in printed wiring board in which the lands 6b are electrically connected can be obtained. Since the connection between the electrode 31a and the land 6b is connected by metal plating, the connection strength between the electrode 31a and the land 6b is also changed by heat treatment when soldering the component built-in printed wiring board to another printed wiring board. There is an effect that a highly reliable electrical connection can be obtained. In addition, since it is not necessary to connect the electrode 31a and the land 6b at a high soldering temperature, damage to the base plate 10 can be reduced, and there is an effect that a printed wiring board with a good quality can be obtained.

  The base plate 10 of the present invention can also use the support substrate 1 of a resin substrate other than a metal plate. Moreover, it is also possible to use the base plate 10 using the film-like insulating resin layer 2 alone without using the support substrate 1.

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2, 52, 52b, 63 ... Insulating resin layer 3 ... Plating ground conductive layer 4 ... Plating resist 5 ... Wiring pattern part 6, 56, 56b ... Wiring pattern 6a ... Land opening hole 6b ... Land 7 ... Non-conductive adhesive resin film 8 ... Inner layer substrate 8a ... Opening 10 ... Base plate 20 ... Inner layer substrate 30 with parts ... Integrated circuit chip 30a ... chip component 31 ... bump electrode 31a ... electrode 40 ... open prepreg 41 ... prepreg opening 42 ... thermosetting insulating resin film 43 ... thermosetting Insulating resin layer 43b ... prepreg 44 ... PET film 50 ... printed wiring board intermediates 51, 60, 64 ... copper foil 53 ... through-hole lower holes 54, 54b, 61 ... for via holes Hole 55, 55 ... filled via holes 57 ... through-hole plating 58 ... solder resist pattern 59 ... the inner layer through-filled via holes 62 ... hole plating

Claims (8)

  A wiring pattern having lands is formed on the first insulating resin layer, and a chip component is adhered on the wiring pattern by a non-conductive adhesive resin film, whereby the electrodes of the chip component are brought into contact with the lands. 1 and an opening prepreg in which a prepreg opening for avoiding the chip component is formed on the first insulating resin layer and the wiring pattern, and an opening for avoiding the chip component is formed on the opening prepreg. A second step of manufacturing the printed wiring board intermediate by installing the inner layer substrate, placing a B-stage thermosetting insulating resin film on the inner layer substrate, laminating, heating and pressurizing, and the printing By laser drilling from the first insulating resin layer side of the wiring board intermediate body, a part of the land and a part of the electrode were exposed through the land and the non-conductive adhesive resin film. A printed wiring with a built-in component comprising at least a third step of forming an hole for a hole and a fourth step of forming a via hole for electrically connecting the land and the electrode by metal plating the via hole. A manufacturing method of a board.   2. The method of manufacturing a component built-in printed wiring board according to claim 1, wherein the chip component is an integrated circuit chip and the electrode is a bump electrode.   2. The method of manufacturing a component built-in printed wiring board according to claim 1, wherein in the first step, the land is formed into a pattern having a land opening hole, and in the third step, the land opening hole is formed by the laser drilling. A method of manufacturing a printed wiring board with a built-in component, wherein a hole for a via hole that exposes the electrode is formed by penetrating a wire.   2. The method of manufacturing a component-embedded printed wiring board according to claim 1, wherein in the first step, the land is formed with a copper pattern having a thickness of 10 μm to 15 μm, and in the third step, the laser drilling is performed. A method of manufacturing a printed wiring board with built-in components, wherein a via hole for exposing the electrode is formed by penetrating a copper pattern of the land.   5. The method of manufacturing a component built-in printed wiring board according to claim 1, wherein the inner layer substrate has an inner layer through-filled via hole, and the third step is a step of forming the printed wiring board intermediate. Forming a second via hole from both sides to the inner layer filled filled via hole, wherein the fourth step forms via hole plating in the second via hole; Production method.   A land wiring pattern having a land opening hole is provided on the first insulating resin layer, a chip component is adhered to the wiring pattern by a non-conductive adhesive resin film, and an electrode of the chip component is brought into contact with the land. And an opening prepreg formed with a prepreg opening for avoiding the chip component on the insulating resin layer and the wiring pattern, and an inner layer substrate formed with an opening for avoiding the chip component, the first insulating resin layer side A printed wiring board with a built-in component comprising a via hole in which a part of the land and the electrode on the land opening hole are electrically connected by metal plating.   7. The component built-in printed wiring board according to claim 6, wherein the chip component is an integrated circuit chip and the electrode is a bump electrode.   The printed wiring board with a built-in component according to claim 6, further comprising a thermosetting insulating resin layer on the inner layer substrate, the inner layer substrate having an inner layer through filled via hole, and the first insulating layer under the inner layer substrate. A component having via hole plating reaching the inner layer through filled via hole from the lower side of the resin layer and via hole plating reaching the inner layer through filled via hole from the upper side of the thermosetting insulating resin layer on the inner layer substrate. Built-in printed wiring board.

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