JP2001298149A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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JP2001298149A
JP2001298149A JP2000113769A JP2000113769A JP2001298149A JP 2001298149 A JP2001298149 A JP 2001298149A JP 2000113769 A JP2000113769 A JP 2000113769A JP 2000113769 A JP2000113769 A JP 2000113769A JP 2001298149 A JP2001298149 A JP 2001298149A
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step
electrode
semiconductor element
opening
semiconductor device
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JP4178715B2 (en )
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Hideyuki Kaneko
Akira Koga
Takahiro Kumakawa
Kazuhiko Matsumura
Koichi Nagao
Yukiko Nakaoka
Ryuichi Sawara
由紀子 中岡
隆一 佐原
彰 小賀
和彦 松村
英之 金子
浩一 長尾
隆博 隈川
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Abstract

PROBLEM TO BE SOLVED: To solve a problem that, as a plurality of laminated semiconductor elements join to a metal wiring formed on an interposer via a metal fine line, it was necessary to increase the size of the interposer by a region of the metal wiring more than the semiconductor element to be mounted, and this was a factor of interfering with a miniaturization of the semiconductor device. SOLUTION: A second semiconductor element 3 has a structure of a lamination via adhesives 5 so that an electrode 2 in a first semiconductor element 1 is exposed onto the first semiconductor element 1, and in this structure, a first insulation resin 6 is formed on the first semiconductor element 1 and the second semiconductor element 3, and a plating wiring 8 is formed on the first insulation resin 6 and is electrically connected to the electrode 2 in the first semiconductor element 1 and an electrode 4 in a second semiconductor element 3. Thus, a plurality of semiconductor elements are laminated while being capable of miniaturizing.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、トランジスタ等の半導体素子を有する半導体装置であって、特に複数の半導体素子を積層する、半導体装置およびその製造方法に関するものである。 BACKGROUND OF THE INVENTION The present invention is a semiconductor device having a semiconductor element such as a transistor, in particular stacking a plurality of semiconductor elements, to a semiconductor device and a manufacturing method thereof.

【0002】 [0002]

【従来の技術】近年、半導体装置およびその製造方法は、電子機器の小型化、高機能化に伴い、小型化、高密度化、高速化を要求されるようになり、たとえばスタックドCSP(Chip Size Package)のような、複数の半導体素子を積層して、高密度化を図るパッケージが開発されている。 In recent years, a semiconductor device and a manufacturing method thereof, miniaturization of electronic devices, become more sophisticated, compact, high density, it will be required to speed, for example, stacked CSP (Chip Size package), such as, by stacking a plurality of semiconductor devices, the package to achieve high density has been developed.

【0003】以下、従来のスタックドCSPと呼ばれる半導体装置について図面を参照しながら説明する。 [0003] Hereinafter, will be described with reference to the drawings semiconductor device called a conventional stacked CSP.

【0004】図10は、従来のスタックドCSPと呼ばれる半導体装置を示す断面図である。 [0004] Figure 10 is a sectional view showing a semiconductor device called a conventional stacked CSP.

【0005】図10において、201は第一の半導体素子、202は第一の半導体素子上電極、203は、第二の半導体素子、204は第二の半導体素子上電極、20 [0005] In FIG. 10, the first semiconductor element 201, a first semiconductor element on the electrodes 202, 203, the second semiconductor element 204 and the second semiconductor element on the electrode, 20
5はインターポーザー、206は第一の金属細線、20 5 interposer, the 206 first thin metal wire, 20
7は第二の金属細線、208は接着剤、209は封止樹脂、210は外部電極端子、211は、インターポーザー上に形成された金属配線である。 The second thin metal wires 7, 208 glue, 209 sealing resin, 210 external electrode terminal, 211 is a metal wiring formed on the interposer.

【0006】図示するように、従来のスタックドCSP [0006] As shown in the figure, the conventional stacked CSP
と呼ばれる半導体装置は、第一の半導体素子201上に第二の半導体素子203を積層し、第一の半導体素子上電極202および第二の半導体素子上電極204をそれぞれ第一の金属細線206および、第二の金属細線20 The semiconductor device, the second semiconductor element 203 is stacked on the first semiconductor element 201, the first metal thin wire 206 a first semiconductor element on the electrode 202 and the second semiconductor element on the electrode 204, respectively and called , the second of the thin metal wires 20
7を介して、インターポーザー上に形成された金属配線211に電気的に接続された構造であり、封止樹脂20 7 through an electrically connected structure the metal wiring 211 formed on the interposer, the sealing resin 20
9で、第一の半導体素子201、第二の半導体素子20 9, the first semiconductor element 201, the second semiconductor element 20
3、第一の金属細線206、第二の金属細線207、インターポーザー上に形成された金属配線211を封止している。 3, the first metal thin wire 206, a second metal thin wire 207, sealing the metal wiring 211 formed on the interposer.

【0007】同図に示すように、従来のスタックドCS [0007] As shown in the figure, the conventional stacked CS
Pと呼ばれる半導体装置は、第一の半導体素子201上に第二の半導体素子203を積層する構造により、高密度化を達成している。 The semiconductor device called a P is the structure of laminating a second semiconductor element 203 on the first semiconductor element 201, we have achieved high density.

【0008】 [0008]

【発明が解決しようとする課題】しかしながら前記従来の半導体装置において、第一の半導体素子上電極202 [SUMMARY OF THE INVENTION] However, in the conventional semiconductor device, the first semiconductor element electrode 202
および第二の半導体素子上電極204と、インターポーザー上に形成された金属配線211との電気的な接合は、それぞれ第一の金属細線206および、第二の金属細線207を介して行われているため、インターポーザー205は、第一の半導体素子201よりも、インターポーザー上に形成された金属配線211の領域分だけ、 A and the second semiconductor element on the electrode 204, electrical connection between the metal wiring 211 formed on the interposer, the first metal thin wire 206, respectively, and, being conducted through the second metal thin wire 207 because you are, interposer 205, than the first semiconductor device 201, by the space of the metal wiring 211 formed on the interposer,
大きくする必要があり、半導体装置の小型化を妨げる要因となっていた。 It should be larger, which is a factor hindering the miniaturization of the semiconductor device.

【0009】本発明は前記従来の課題を解決するもので、複数の半導体素子を積層し、かつ、小型化を可能とする、半導体装置およびその製造方法を提供することを目的とする。 [0009] The present invention is intended to solve the conventional problem above, by stacking a plurality of semiconductor elements, and allows size reduction, and an object thereof is to provide a semiconductor device and a manufacturing method thereof.

【0010】 [0010]

【課題を解決するための手段】この目的を達成するために本発明の半導体装置およびその製造方法は以下の構成を有している。 Means for Solving the Problems A semiconductor device and a manufacturing method thereof of the present invention in order to achieve this object has the following configuration.

【0011】請求項1記載の半導体装置は、主面上に複数の第一の電極が配列された第一の半導体素子と、前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、主面上に複数の第二の電極が配列された第二の半導体素子と、前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように形成された第一の絶縁性樹脂と、前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に延在された、 [0011] The semiconductor device according to claim 1, a first semiconductor device in which a plurality of first electrodes on a main surface arranged, on a main surface of said first semiconductor device, at least the first electrodes are stacked so as to expose a portion of the region being arranged, and a second semiconductor device in which a plurality of second electrodes on the main surface are arranged, on the main surface of the first semiconductor element and, formed on the main surface of the second semiconductor element, regions of at least the first electrode is disposed and that has an opening in a part of a region where the second electrode is arranged a first insulating resin formed on said first electrode and from said second electrode, through an opening formed in said first insulating layer, the first insulating layer It has been extended,
第一のめっき配線と、少なくとも前記第一のめっき配線の一部の領域に開口部を有する、第二の絶縁性樹脂と、 A first plated wiring, having an opening in a part of the region of at least the first plated wiring, a second insulating resin,
前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子とからなる。 Through the opening of the second insulating resin, it is the first plating wiring and electrically connected, consisting of an external electrode terminal.

【0012】請求項2記載の半導体装置は、主面上に複数の第一の電極が配列された第一の半導体素子と、前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、第二、第三以降複数の半導体素子と、前記第二、 [0012] The semiconductor device according to claim 2, a first semiconductor device in which a plurality of first electrodes on a main surface arranged, on a main surface of said first semiconductor device, at least the first electrodes are stacked so as to expose a portion of the region being arranged, second, a plurality of semiconductor elements third or later, the second,
第三以降複数の半導体素子上に形成された電極と、前記第一の半導体素子の主面上および、前記第二、第三以降複数の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二、第三以降複数の半導体素子上に形成された電極が配置されている領域の、一部に開口部を有するように形成された第一の絶縁性樹脂と、前記第一の電極および、前記第二、第三以降複数の半導体素子上に形成された電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に延在された、第一のめっき配線と、 An electrode formed on the third and later on a plurality of semiconductor elements, the main surface of the first semiconductor element and the second, formed on the main surface of the third and subsequent plurality of semiconductor elements, at least the first area electrodes are arranged and, the second, the region where the third and subsequent plurality of semiconductor elements formed on the electrode is disposed, the first formed to have an opening part an insulating resin, said first electrode and said second, from the third and subsequent plurality of semiconductor elements formed on the electrode, through the opening formed in the first insulating layer, said first It was extended on the insulating layer, a first plated wiring,
少なくとも前記第一のめっき配線上の一部の領域に開口部を有する、第二の絶縁性樹脂と、前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子とからなる。 Having an opening in a part of the region on at least said first plated wiring, a second insulating resin, through the opening of the second insulating resin, electrical said first plated wiring connected to, and a external electrode terminal.

【0013】請求項3記載の半導体装置は、主面上に複数の第一の電極が配列された第一の半導体素子と、前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、主面上に複数の第二の電極が配列された第二の半導体素子と、前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように形成された第一の絶縁性樹脂と、前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に延在された、 [0013] The semiconductor device according to claim 3, a first semiconductor device in which a plurality of first electrodes on a main surface arranged, on a main surface of said first semiconductor device, at least the first electrodes are stacked so as to expose a portion of the region being arranged, and a second semiconductor device in which a plurality of second electrodes on the main surface are arranged, on the main surface of the first semiconductor element and, formed on the main surface of the second semiconductor element, regions of at least the first electrode is disposed and that has an opening in a part of a region where the second electrode is arranged a first insulating resin formed on said first electrode and from said second electrode, through an opening formed in said first insulating layer, the first insulating layer It has been extended,
第一のめっき配線と、少なくとも前記第一のめっき配線が形成されている領域の一部を露出するように積層された、主面上に複数の第三の電極が配列された第三の半導体素子と、少なくとも前記第三の半導体素子の主面上に形成され、少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に開口部を有するように形成された第二の絶縁性樹脂と、少なくとも前記第三の電極および、前記第一のめっき配線から、第二の絶縁性樹脂の開口部を介して、第二の絶縁性樹脂上に延在された第二のめっき配線と、少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、第三の絶縁性樹脂と、前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外 A first plated wiring, at least the first plated wiring are laminated so as to expose a portion of the region being formed, the third semiconductor where a plurality of third electrodes on a main surface arranged and elements, are formed on the main surface of at least the third semiconductor element, regions of at least the third electrode is disposed and an opening in a part of a region where the first plating wires are disposed a second insulating resin formed to have, at least the third electrode and, from the first plating wiring through the opening of the second insulating resin, the second insulating resin a second plating wiring which runs in a top having an opening in a part of the region on at least said second plated wiring, a third insulating resin, the third opening of the insulating resin through, it was the second plated wiring electrically connected, outside 電極端子とからなる。 Consisting of an electrode terminal.

【0014】請求項4記載の半導体装置の製造方法は、 [0014] The method according to claim 4, wherein the
複数の第一の電極が配置された第一の半導体素子の主面上に、前記第一の電極が配置されている領域が露出するように、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有する第一の絶縁性樹脂を形成する第二の工程と、前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に第一のめっき配線を延在する第三の工程と、 On the main surface of the first semiconductor element in which a plurality of first electrodes arranged, as the area where the first electrode is disposed is exposed, the plurality over the main surface second electrode array a first step of laminating a second semiconductor element, the main surface and on the first semiconductor element, on the main surface of the second semiconductor element, is disposed at least said first electrode region and the a second step of the second electrode forming a first insulating resin having an opening in a portion of the region being arranged, said first electrode and said second electrode are from the third step via an opening formed in said first insulating layer, extending on the first plated wiring on the first insulating layer,
少なくとも前記第一のめっき配線の一部の領域に開口部を有する、第二の絶縁性樹脂を形成する第四の工程と、 Having an opening in a part of the region of at least the first plated wiring, a fourth step of forming a second insulating resin,
前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子を形成する第五の工程とを有することを特徴とする。 Through the opening of the second insulating resin, said being first plating wiring and electrically connected, and having a fifth step of forming an external electrode terminal.

【0015】請求項5記載の半導体装置の製造方法は、 [0015] The method according to claim 5, wherein the
請求項4に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、および前記第四の工程を、前記第一の半導体素子がウェハの状態で行われ、さらに、前記第一の半導体素子をウェハ状態から個片に分割する第六の工程とを有することを特徴とする。 The method of manufacturing a semiconductor device according to claim 4, at least, the first step, the second step, the third step, and the fourth step, the first semiconductor device in a wafer state place at further characterized by having a sixth step of dividing said first semiconductor device into individual pieces from a wafer state.

【0016】請求項6記載の半導体装置の製造方法は、 The method according to claim 6, wherein the
主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように、第二、第三以降複数の半導体素子を積層する第一の工程と、前記第一の半導体素子の主面上および、前記第二、第三以降複数の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二、第三以降複数の半導体素子上に形成された電極が配置されている領域の、一部に開口部を有するように、第一の絶縁性樹脂を形成する第二の工程と、前記第一の電極および、前記第二、第三以降複数の半導体素子上に形成された電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第三の工程と、 On the main surface of the first semiconductor element in which a plurality of first electrodes arranged on the main surface, so as to expose a portion of the region where at least the first electrode is disposed, second, a first step of laminating a plurality of semiconductor elements three later, the main surface and the first semiconductor element, the second, on a major surface of the third and subsequent plurality of semiconductor elements, at least the first electrode There regions are arranged and the second, the region where the third and subsequent plurality of semiconductor elements formed on the electrode are arranged so as to have an opening in a part, the first insulating resin a second step of forming the first electrode and the second, the third and subsequent plurality of semiconductor elements formed on the electrode, through the opening formed in the first insulating layer, the first insulating layer, and a third step of extending the first plated wiring,
少なくとも前記第一のめっき配線上の一部の領域に開口部を有するように、第二の絶縁性樹脂を形成する第四の工程と、前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子を形成する第五の工程とを有することを特徴とする。 So as to have an opening portion in a part of the region on at least said first plated wiring, a fourth step of forming a second insulating resin, through the opening of the second insulating resin, the is first plated wiring electrically connected, and having a fifth step of forming an external electrode terminal.

【0017】請求項7記載の半導体装置の製造方法は、 The method according to claim 7, wherein the
請求項6に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、および前記第四の工程を、前記第一の半導体素子がウェハの状態で行われ、さらに、前記第一の半導体素子をウェハ状態から個片に分割する第六の工程とを有することを特徴とする。 The method of manufacturing a semiconductor device according to claim 6, at least, the first step, the second step, the third step, and the fourth step, the first semiconductor device in a wafer state place at further characterized by having a sixth step of dividing said first semiconductor device into individual pieces from a wafer state.

【0018】請求項8記載の半導体装置の製造方法は、 [0018] The method of manufacturing a semiconductor device according to claim 8,
主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように第一の絶縁性樹脂を形成する第二の工程と、前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第三の工程と、少なくとも前記第一のめっき配線が形成されている領域の一部を露出するように、主面上に複数の On a first main surface of the semiconductor device in which a plurality of first electrodes on the main surface are arranged so as to expose a portion of the region where at least the first electrode is disposed, on the main surface a first step of the plurality of second electrodes are stacked a second semiconductor elements arranged, said upper major surface of the first semiconductor element and, on the main surface of the second semiconductor device, at least the region first electrode is disposed and, a second step of forming a first insulating resin so as to have an opening portion in a part of a region where the second electrode is disposed, the first from one electrode and said second electrode, through the opening formed in the first insulating layer, said the first insulating layer, a third step of extending the first plated wiring If, so as to expose a portion of a region in which at least the first plating wiring is formed, the plurality over the main surface 三の電極が配列された第三の半導体素子を積層する第四の工程と、少なくとも前記第三の半導体素子の主面上に、少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に開口部を有するように、第二の絶縁性樹脂を形成する第五の工程と、少なくとも前記第三の電極および、前記第一のめっき配線から、第二の絶縁性樹脂の開口部を介して、第二の絶縁性樹脂上に、第二のめっき配線を延在する第六の工程と、少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、 A fourth step of laminating a third semiconductor device and third electrodes are arranged, on a main surface of at least the third semiconductor element, regions of at least the third electrode is disposed and the second so as to have an opening portion in a part of a region in which one of the plating wires are disposed, and a fifth step of forming a second insulating resin, at least the third electrode and the first plated wiring from through the opening of the second insulating resin, the second insulative resin, and a sixth step of extending the second plated wiring, a part on at least said second plated wiring having an opening in the region,
第三の絶縁性樹脂を形成する第七の工程と、前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外部電極端子を形成する第八の工程と、を有することを特徴とする。 A seventh step of forming a third insulating resin, through an opening in the third insulating resin, is the second plated wiring electrically connected, first to form an external electrode terminal and having a eighth step.

【0019】請求項9記載の半導体装置の製造方法は、 The method according to claim 9, wherein the
請求項8に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、前記第四の工程、前記第五の工程、前記第六の工程、および前記第七の工程を、前記第一の半導体素子がウェハの状態で行われ、さらに、前記第一の半導体素子をウェハ状態から個片に分割する第九の工程とを有することを特徴とする。 The method of manufacturing a semiconductor device according to claim 8, at least, the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, the and the seventh step, the first semiconductor device is performed in a wafer state, further comprising; and a ninth step of dividing said first semiconductor device into individual pieces from a wafer state to.

【0020】請求項10記載の半導体装置の製造方法は、主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、前記第二の半導体素子の主面上に、第一の絶縁性樹脂を形成する第二の工程と、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に、第一の開口部を形成する第三の工程と、前記第一の電極および、前記第二の電極から、前記第一開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第四の工程と、少なくとも前記第一絶縁性樹脂上および、前記第一のめっき配線上に、主面上に複数の第三の電極が配列された第三の半導体素子を積層する第五の工程と、前 The method according to claim 10, wherein the on the main surface of the first semiconductor element in which a plurality of first electrodes on a main surface are arranged, the plurality of second electrodes on the main surface There a first step of laminating a second semiconductor elements arranged, on a main surface of the second semiconductor element, a second step of forming a first insulating resin, at least the first area electrodes are arranged and, in a part of a region where the second electrodes are arranged, a third step of forming a first opening, said first electrode and said second from the electrode, through the first opening, the first insulating layer, and a fourth step of extending the first plated wiring, on at least said first insulating resin and the first on plated wiring, a fifth step of laminating the third semiconductor device where a plurality of third electrodes on the main surface are arranged, prior to 第三の半導体素子の主面上に、第二の絶縁性樹脂を形成する第六の工程と少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に、第二の開口部を形成する第七の工程と、少なくとも前記第三の電極および、前記第一のめっき配線から、第二の開口部を介して、第二の絶縁性樹脂上に、第二のめっき配線を延在する第八の工程と、少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、第三の絶縁性樹脂を形成する第九の工程と、前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外部電極端子を形成する第十の工程とを有することを特徴とする。 On the main surface of the third semiconductor element, regions of at least the third electrode and the sixth step of forming a second insulating resin is disposed and said first plating wires are disposed some of the region, and the seventh step of forming a second opening, at least the third electrode and, from the first plating wiring, via a second opening, the second insulating on the resin, and the eighth step of extending the second plating wire, having an opening in a part of the region on at least said second plated wiring, ninth to form a third insulating resin a step, through the opening in the third insulating resin, the second plated wiring electrically connected, and having a tenth step of forming an external electrode terminal.

【0021】請求項11記載の半導体装置の製造方法は、請求項10に係る半導体装置の製造方法において、 The method according to claim 11, wherein, in the manufacturing method of the semiconductor device according to claim 10,
少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、前記第四の工程、前記第五の工程、前記第六の工程、前記第七の工程、前記第八の工程、および前記第九の工程を、前記第一の半導体素子がウェハの状態で行われ、さらに、前記第一の半導体素子をウェハ状態から個片に分割する第十一の工程とを有することを特徴とする。 At least, the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, the seventh step, the eighth step, the and the ninth step, the first semiconductor device is performed in a wafer state, further characterized by having a eleventh step of dividing said first semiconductor device into individual pieces from a wafer state to.

【0022】請求項1の構成により、第一の半導体素子と同じサイズで、2つの半導体素子を積層した半導体装置が得られる。 [0022] The arrangement of claim 1, the same size as the first semiconductor element, a semiconductor device formed by stacking two semiconductor device can be obtained.

【0023】請求項2の構成により、第一の半導体素子と同じサイズで、3つ以上の半導体素子を積層した半導体装置が得られる。 [0023] The arrangement according to claim 2, the same size as the first semiconductor element, a semiconductor device is obtained by laminating three or more semiconductor elements.

【0024】請求項3の構成により、第一の半導体素子と同じサイズで、3つ以上の半導体素子を積層した半導体装置がえられるとともに、第二の半導体素子と第三の半導体素子のサイズを第一の半導体素子と同じサイズにすることができる。 [0024] The arrangement according to claim 3, in the same size as the first semiconductor element, together with the semiconductor device will be obtained by laminating three or more semiconductor devices, the size of the second semiconductor element and the third semiconductor element it can be the same size as the first semiconductor element.

【0025】請求項4の半導体装置の製造方法により、 [0025] The method according to claim 4,
請求項1記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 1.

【0026】請求項5の半導体装置の製造方法により、 [0026] The method according to claim 5,
請求項1記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device of claim 1, wherein it is possible to produce in a wafer state.

【0027】請求項6の半導体装置の製造方法により、 [0027] The method according to claim 6,
請求項2記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 2, wherein.

【0028】請求項7の半導体装置の製造方法により、 [0028] The manufacturing method of a semiconductor device according to claim 7,
請求項2記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device according to claim 2, wherein it is possible to produce in a wafer state.

【0029】請求項8の半導体装置の製造方法により、 [0029] The method according to claim 8,
請求項3記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 3, wherein.

【0030】請求項9の半導体装置の製造方法により、 [0030] The method according to claim 9,
請求項3記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device according to claim 3, wherein it is possible to produce in a wafer state.

【0031】請求項10の半導体装置の製造方法により、請求項3記載の半導体素子を製造することができる。 [0031] The method according to claim 10, it is possible to manufacture a semiconductor device according to claim 3, wherein.

【0032】請求項11の半導体装置の製造方法により、請求項3記載の半導体素子をウェハ状態で製造することができる。 [0032] The method according to claim 11, the semiconductor device according to claim 3, wherein it is possible to produce in a wafer state.

【0033】 [0033]

【発明の実施の形態】以下、本発明の実施形態について図面を参照しながら説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the accompanying drawings, embodiments of the present invention.

【0034】(第一の実施形態)図1は本発明の第一の実施形態に係る半導体装置の例を示す斜視図であり、図2は本発明の第一の実施形態に係る半導体装置の例を示す断面図である。 [0034] (First Embodiment) FIG. 1 is a perspective view showing an example of a semiconductor device according to a first embodiment of the present invention, FIG. 2 of a semiconductor device according to a first embodiment of the present invention example is a sectional view showing a.

【0035】図1および、図2において、1は第一の半導体素子、2は第一の半導体素子上電極、3は第二の半導体素子、4は第二の半導体素子上電極、5は接着剤、 FIG. 1 and 2, reference numeral 1 denotes a first semiconductor element, the first semiconductor element on the electrode 2, the second semiconductor element 3, the second semiconductor element on the electrodes 4, 5 adhered agent,
6は第一の絶縁性樹脂、7は第二の絶縁性樹脂、8はめっき配線、9は外部電極端子、10は第一の絶縁性樹脂に形成された開口部である。 6 first insulating resin 7 is a second insulating resin 8 is plated wiring, 9 external electrode terminal, 10 is an opening portion formed in the first insulating resin.

【0036】図1,図2において、第二の半導体素子3 [0036] In FIGS. 1 and 2, the second semiconductor element 3
は、第一の半導体素子1の上に、第一の半導体素子上電極2が露出するように、接着剤5を介して積層された構造である。 Is on the first semiconductor element 1, as the first semiconductor element on the electrode 2 is exposed, is laminated via an adhesive 5 structure. このとき、第二の半導体素子3の厚みは、2 At this time, the second thickness of the semiconductor element 3, 2
00[μm]以下が望ましい。 00 [μm] or less. また、接着剤5は絶縁性を有しかつ、線膨張係数は10[ppm]以下が望ましい。 The adhesive 5 has an insulating property and the linear expansion coefficient desirably 10 [ppm] or less.

【0037】第一の絶縁性樹脂6は、第一の半導体素子1および第二の半導体素子3上に、第一の半導体素子上電極2および第二の半導体素子上電極4が開口するように形成されている。 The first insulating resin 6, on the first semiconductor element 1 and the second semiconductor element 3, as the first semiconductor element electrode 2 and the second semiconductor element on the electrode 4 is opened It is formed. めっき配線8は第一の絶縁性樹脂6 The plated wiring 8 first insulating resin 6
上に形成され、さらに、第一の絶縁性樹脂6に形成された開口部10を介して、第一の半導体素子上電極2および第二の半導体素子上電極4と電気的に接続されている構造である。 Formed thereon, further, through the opening 10 formed in the first insulating resin 6 and is electrically connected to the first semiconductor element electrode 2 and the second semiconductor element on the electrode 4 it is a structure. このときめっき配線8は必ずしも第一の半導体素子上電極2および第二の半導体素子上電極4と電気的に接続する必要はなく、また、第一の半導体素子上電極2と、第二の半導体素子上電極4は、第一の絶縁性樹脂6上に形成されためっき配線8を介して電気的に接続されていてもよい。 In this case plated wiring 8 need not necessarily be connected first on the semiconductor element electrode 2 and the second semiconductor element electrode 4 electrically, and the electrode 2 a first semiconductor device, the second semiconductor element on the electrode 4 may be electrically connected via the first insulating resin 6 plated wiring 8 formed on. ここでめっき配線8の材質は電気特性上、銅が望ましい。 Wherein the material of the plated wiring 8 on the electrical characteristics, copper is preferable.

【0038】第二の絶縁性樹脂7は、めっき配線8の一部を開口するように形成されており、この開口部(図示せず)を介して外部電極端子9とめっき配線8は電気的に接続されている構造である。 The second insulating resin 7 is formed so as to open a portion of the plated wiring 8, plated wiring 8 and the external electrode terminals 9 through the opening (not shown) is electrically it is a structure that is connected to.

【0039】(第一の実施形態の製造方法)図3は本発明の第一の実施形態に係る半導体装置の製造方法の例を示す断面図である。 FIG. 3 (the manufacturing method of the first embodiment) is a sectional view showing an example of a manufacturing method of a semiconductor device according to a first embodiment of the present invention.

【0040】図3において、1は第一の半導体素子、2 [0040] In FIG. 3, 1 is a first semiconductor element, 2
は第一の半導体素子上電極、3は第二の半導体素子、4 The first semiconductor element on the electrode, the 3 second semiconductor element, 4
は第二の半導体素子上電極、5は接着剤、6は第一の絶縁性樹脂、7は第二の絶縁性樹脂、8はめっき配線、9 The second semiconductor element on the electrode, 5 is an adhesive, the first insulating resin 6, 7 second insulating resin 8 is plated wiring 9
は外部電極端子、10は第一の絶縁性樹脂に形成された開口部である。 The external electrode terminal, 10 is an opening formed in the first insulating resin.

【0041】まず、図3−Aに示すように第一の半導体素子上電極2を有した第一の半導体素子1を用意し、そして図3−Bに示すように、第二の半導体素子3を第一の半導体素子1の上に接着剤5によって接着する。 [0041] First, a first semiconductor element 1 having a first semiconductor element on the electrode 2 as shown in FIG. 3-A, and as shown in FIG. 3-B, the second semiconductor element 3 the bonding by adhesive 5 on the first semiconductor element 1. このとき接着剤5は、液状の熱硬化型樹脂でも、フィルム状の熱硬化型樹脂でもよい。 Adhesive 5 at this time, even thermosetting liquid resin, or a film-like thermosetting resin. 接着剤5に液状の熱硬化型樹脂を用いた場合は、予め第一の半導体素子1上に適量塗布しておき、第二の半導体素子を積層した後、高温槽またはホットプレートを用いて接着剤5を硬化する。 If the adhesive 5 with thermosetting liquid resin is leave an appropriate amount coated on advance first semiconductor element 1, after laminating the second semiconductor device, using a high-temperature bath or a hot plate bonding to cure the agent 5. また、接着剤5にフィルム状の熱硬化型樹脂を用いた場合は、予め第二の半導体素子3の裏面に貼り付けておき、 In the case of using a film-like thermosetting resin adhesive 5, paste them on the back of the previously second semiconductor element 3,
第一の半導体素子1または、第二の半導体素子3を加熱しながら、第一の半導体素子1に接着する。 The first semiconductor element 1 or, while heating the second semiconductor element 3 is bonded to the first semiconductor element 1.

【0042】次に、図3−Cに示すように、第一の絶縁性樹脂6を第一の半導体素子1および第二の半導体素子3上に塗布する。 Next, as shown in FIG. 3-C, applying a first insulating resin 6 on the first semiconductor element 1 and the second semiconductor element 3. このとき第一の絶縁性樹脂6には液状の感光性樹脂を用いて、印刷法または、スピンコートで塗布する。 At this time, the first insulating resin 6 with liquid photosensitive resin, a printing method or is applied by spin coating. ここで、第一の絶縁性樹脂6はフィルム状の感光性樹脂でもよい。 Here, first insulating resin 6 may be a film-shaped photosensitive resin.

【0043】その後に、図3−Dに示すように、第一の絶縁性樹脂6を仮硬化し、第一の半導体素子上電極2および、第二の半導体素子上電極4を開口するように、露光、現像、本硬化する。 [0043] Then, as shown in FIG. 3-D, a first insulating resin 6 and temporarily cured, the first semiconductor element electrodes 2 and so as to open the upper electrode 4 the second semiconductor element , exposure, development, and curing.

【0044】次に、図3−Eに示すように、第一の絶縁性樹脂6上および、第一の絶縁性樹脂に形成された開口部10を介して、少なくとも第一の半導体素子上電極2 Next, as shown in FIG. 3-E, above the first insulating resin 6 and, via a first insulating resin which is formed in the opening 10, on at least a first semiconductor element electrode 2
または、第二の半導体素子上電極4の一部と電気的に接続するように、めっき配線8を形成する。 Or so as to connect a portion electrically second semiconductor element on the electrode 4, to form a plated wiring 8. めっき配線8 Plated wiring 8
はフォトリソによって形成し、その材質には銅が望ましい。 It was formed by photolithography, and its material Copper is desirable.

【0045】次に、図3−Fおよび図3−Gに示すように、第一の絶縁性樹脂6を形成するのと同様の方法で、 Next, as shown in FIG. 3-F and FIG. 3-G, in the same manner as forming the first insulating resin 6,
第二の絶縁性樹脂7をめっき配線8の一部が開口するように形成する。 A portion of the second insulating resin 7 a plated wiring 8 is formed so as to open.

【0046】最後に、図3−Hに示すように外部電極端子9を第二の絶縁性樹脂7の開口部を介してめっき配線8と電気的に接続する。 [0046] Finally, electrically connected to the plated wiring 8 through the external electrode terminals 9 as shown in FIG. 3-H opening of the second insulating resin 7. ここで、外部電極端子9の接続法には、ボール転写法や、はんだ印刷法を用いる。 Here, the method of connecting the external electrode terminals 9, ball transfer method and, using a solder printing method.

【0047】図3において、第一の半導体素子1は個片で図示しているが、個片に分割する前のウェハ状態で製造してもよい。 [0047] In FIG. 3, although the first semiconductor element 1 is illustrated in pieces, may be manufactured in a wafer state before the split into pieces. このときウェハ状態から個片への分割は、図3−Hに示す外部電極端子9を接続する工程の前または後に行うことが望ましい。 In this case the division of the wafer state to individual pieces is preferably carried out after or before the step of connecting the external electrode terminals 9 shown in Fig. 3-H.

【0048】(第二の実施形態)図4は本発明の第二の実施形態に係る半導体装置の例を示す断面図である。 [0048] (Second Embodiment) FIG. 4 is a sectional view showing an example of a semiconductor device according to a second embodiment of the present invention.

【0049】図4において、1は第一の半導体素子、2 [0049] In FIG. 4, 1 is a first semiconductor element, 2
は第一の半導体素子上電極、3は第二の半導体素子、4 The first semiconductor element on the electrode, the 3 second semiconductor element, 4
は第二の半導体素子上電極、5は接着剤、6は第一の絶縁性樹脂、7は第二の絶縁性樹脂、8はめっき配線、9 The second semiconductor element on the electrode, 5 is an adhesive, the first insulating resin 6, 7 second insulating resin 8 is plated wiring 9
は外部電極端子、10は第一の絶縁性樹脂に形成された開口部、11は第三の半導体素子、12は第三の半導体素子上電極である。 The external electrode terminal, 10 is an opening portion formed in the first insulating resin 11 and the third semiconductor element 12 is on the third semiconductor element electrode.

【0050】図4において、第二の半導体素子3は、第一の半導体素子1の上に、第一の半導体素子上電極2が露出するように、また、第三の半導体素子11は、第二の半導体素子3の上に、第二の半導体素子上電極4が露出するように、接着剤5を介して積層された構造である。 [0050] In FIG. 4, the second semiconductor element 3, on the first semiconductor element 1, as the first semiconductor element on the electrode 2 is exposed, also, the third semiconductor element 11, the on the second semiconductor element 3, as the second semiconductor element on the electrode 4 is exposed, it is laminated through an adhesive 5 structure. このとき、第二の半導体素子3および第三の半導体素子11の厚みは、200[μm]以下が望ましい。 At this time, the thickness of the second semiconductor element 3 and the third semiconductor element 11, 200 [[mu] m] or less. また、接着剤5は絶縁性を有しかつ、線膨張係数は10 The adhesive 5 has an insulating property and the linear expansion coefficient 10
[ppm]以下が望ましい。 [Ppm] or less is desirable.

【0051】第一の絶縁性樹脂6は、第一の半導体素子1、第二の半導体素子3および第三の半導体素子11上に、第一の半導体素子上電極2、第二の半導体素子上電極4および第三の半導体素子上電極12が開口するように形成されている。 The first insulating resin 6, the first semiconductor element 1, the second on the semiconductor element 3 and the third semiconductor element 11, a first semiconductor element on the electrode 2, the second semiconductor device electrode 4 and the third semiconductor element on the electrode 12 is formed so as to open. めっき配線8は第一の絶縁性樹脂6 The plated wiring 8 first insulating resin 6
上に形成され、さらに、第一の絶縁性樹脂6に形成された開口部10を介して、第一の半導体素子上電極2、第二の半導体素子上電極4および第三の半導体素子上電極12と電気的に接続されている構造である。 Formed thereon, further, through the opening 10 formed in the first insulating resin 6, the first semiconductor element on the electrode 2, the second semiconductor element on the electrode 4 and the third semiconductor element on the electrode 12 and which is electrically the attached structure. このときめっき配線8は必ずしも第一の半導体素子上電極2、第二の半導体素子上電極4および第三の半導体素子上電極1 In this case plated wiring 8 is necessarily the first semiconductor element on the electrode 2, on the second semiconductor element on the electrode 4 and the third semiconductor element electrode 1
2と電気的に接続する必要はなく、また、第一の半導体素子上電極2、第二の半導体素子上電極4および第三の半導体素子上電極12はそれぞれ、第一の絶縁性樹脂6 2 and electrically not need to be connected, also, the first semiconductor element on the electrode 2, respectively the second semiconductor element on the electrode 4 and the third semiconductor element on the electrode 12 of the first insulating resin 6
上に形成されためっき配線8を介して電気的に接続されていてもよい。 It may be electrically connected via the plated wiring 8 formed thereon. ここでめっき配線8の材質は電気特性上、銅が望ましい。 Wherein the material of the plated wiring 8 on the electrical characteristics, copper is preferable.

【0052】第二の絶縁性樹脂7は、めっき配線8の一部を開口するように形成されており、この開口部(図示せず)を介して外部電極端子9とめっき配線8は電気的に接続されている構造である。 [0052] The second insulating resin 7 is formed so as to open a portion of the plated wiring 8, plated wiring 8 and the external electrode terminals 9 through the opening (not shown) is electrically it is a structure that is connected to.

【0053】ここでは、3つの半導体素子を積層しているが、第三の半導体素子12の上にさらに、第四、第五と複数の半導体素子を積層してもよい。 [0053] Here, although the laminated three semiconductor elements, further on the third semiconductor element 12, the fourth, may be stacked fifth plurality of semiconductor elements.

【0054】(第二の実施形態の製造方法)図5は本発明の第一の実施形態に係る半導体装置の製造方法の例を示す断面図である。 [0054] FIG. 5 (a manufacturing method of the second embodiment) is a sectional view showing an example of a manufacturing method of a semiconductor device according to a first embodiment of the present invention.

【0055】図5において、1は第一の半導体素子、2 [0055] In FIG. 5, 1 the first semiconductor element, 2
は第一の半導体素子上電極、3は第二の半導体素子、4 The first semiconductor element on the electrode, the 3 second semiconductor element, 4
は第二の半導体素子上電極、5は接着剤、6は第一の絶縁性樹脂、7は第二の絶縁性樹脂、8はめっき配線、9 The second semiconductor element on the electrode, 5 is an adhesive, the first insulating resin 6, 7 second insulating resin 8 is plated wiring 9
は外部電極端子、10は第一の絶縁性樹脂に形成された開口部、11は第三の半導体素子、12は第三の半導体素子上電極であるである。 The external electrode terminal, 10 is an opening portion formed in the first insulating resin 11 and the third semiconductor element 12 is located on the third semiconductor element electrodes.

【0056】まず、図5−Aに示すように第一の半導体素子上電極2を有した第一の半導体素子1を用意し、そして図5−Bに示すように、第二の半導体素子3を第一の半導体素子1の上に接着剤5によって接着する。 [0056] First, a first semiconductor element 1 having a first semiconductor element on the electrode 2 as shown in FIG. 5-A, and as shown in FIG. 5-B, the second semiconductor element 3 the bonding by adhesive 5 on the first semiconductor element 1. このとき接着剤5は、液状の熱硬化型樹脂でも、フィルム状の熱硬化型樹脂でもよい。 Adhesive 5 at this time, even thermosetting liquid resin, or a film-like thermosetting resin. 接着剤5に液状の熱硬化型樹脂を用いた場合は、予め第一の半導体素子1上に適量塗布しておき、第二の半導体素子を積層した後、高温槽またはホットプレートを用いて接着剤5を硬化する。 If the adhesive 5 with thermosetting liquid resin is leave an appropriate amount coated on advance first semiconductor element 1, after laminating the second semiconductor device, using a high-temperature bath or a hot plate bonding to cure the agent 5. また、接着剤5にフィルム状の熱硬化型樹脂を用いた場合は、予め第二の半導体素子3の裏面に貼り付けておき、 In the case of using a film-like thermosetting resin adhesive 5, paste them on the back of the previously second semiconductor element 3,
第一の半導体素子1または、第二の半導体素子3を加熱しながら、第一の半導体素子1に接着する。 The first semiconductor element 1 or, while heating the second semiconductor element 3 is bonded to the first semiconductor element 1.

【0057】さらに、図5−Cに示すように、第二の半導体素子3を第一の半導体素子1の上に接着するのと同様の方法で、第三の半導体素子11を第二の半導体素子3の上に接着する。 [0057] Further, as shown in FIG. 5-C, in a manner similar to bond the second semiconductor element 3 on the first semiconductor element 1, the third semiconductor element 11 and the second semiconductor to adhere to the top of the element 3.

【0058】次に、図5−Dに示すように、第一の絶縁性樹脂6を第一の半導体素子1、第二の半導体素子3および第三の半導体素子11上に塗布する。 Next, as shown in FIG. 5-D, applying a first insulating resin 6 on the first semiconductor element 1, the second semiconductor element 3 and the third semiconductor element 11. このとき第一の絶縁性樹脂6には液状の感光性樹脂を用いて、印刷法または、スピンコートで塗布する。 At this time, the first insulating resin 6 with liquid photosensitive resin, a printing method or is applied by spin coating. ここで、第一の絶縁性樹脂6はフィルム状の感光性樹脂でもよい。 Here, first insulating resin 6 may be a film-shaped photosensitive resin.

【0059】その後に、図5−Eに示すように、第一の絶縁性樹脂6を仮硬化し、第一の半導体素子上電極2、 [0059] Then, FIG as shown in 5-E, the first insulating resin 6 and temporarily cured, the first semiconductor element electrodes 2,
第二の半導体素子上電極4および、第三の半導体素子上電極12を開口するように、露光、現像、本硬化する。 The second semiconductor element on the electrode 4 and to open the third semiconductor element on the electrode 12, exposure, development, and curing.

【0060】次に、図5−Fに示すように、第一の絶縁性樹脂6上および、第一の絶縁性樹脂に形成された開口部10を介して、少なくとも第一の半導体素子上電極2、第二の半導体素子上電極4および、第三の半導体素子上電極12の一部と電気的に接続するように、めっき配線8を形成する。 Next, as shown in FIG. 5-F, on the first insulating resin 6 and, via a first insulating resin which is formed in the opening 10, on at least a first semiconductor element electrode 2, the second semiconductor element on the electrode 4 and to a portion electrically connected to the third semiconductor element on the electrode 12, to form a plated wiring 8. めっき配線8はフォトリソによって形成し、その材質には銅が望ましい。 The plated wiring 8 was formed by photolithography, copper on the material is desired.

【0061】次に、図5−Gおよび図5−Hに示すように、第一の絶縁性樹脂6を形成するのと同様の方法で、 Next, as shown in FIG. 5-G and Fig. 5-H, in a manner similar to forming the first insulating resin 6,
第二の絶縁性樹脂7をめっき配線8の一部が開口するように形成する。 A portion of the second insulating resin 7 a plated wiring 8 is formed so as to open.

【0062】最後に、図5−Iに示すように外部電極端子9を第二の絶縁性樹脂7の開口部を介してめっき配線8と電気的に接続する。 [0062] Finally, electrically connected to the plated wiring 8 through the external electrode terminals 9 as shown in FIG. 5-I opening of the second insulating resin 7. ここで、外部電極端子9の接続法には、ボール転写法や、はんだ印刷法を用いる。 Here, the method of connecting the external electrode terminals 9, ball transfer method and, using a solder printing method.

【0063】図5において、第一の半導体素子1は個片で図示しているが、個片に分割する前のウェハ状態で製造してもよい。 [0063] In FIG. 5, the first semiconductor element 1 is illustrated in pieces, it may be manufactured in a wafer state before the split into pieces. このときウェハ状態から個片への分割は、図5−Iに示す外部電極端子9を接続する工程の前または後に行うことが望ましい。 In this case the division of the wafer state to individual pieces is preferably performed before or after the step of connecting the external electrode terminals 9 shown in Fig. 5-I.

【0064】(第三の実施形態)図6は本発明の第三の実施形態に係る半導体装置の例を示す断面図である。 [0064] (Third Embodiment) FIG. 6 is a sectional view showing an example of a semiconductor device according to a third embodiment of the present invention.

【0065】図6において、101は第一の半導体素子、102は第一の半導体素子上電極、103は第二の半導体素子、104は第二の半導体素子上電極、105 [0065] In FIG. 6, 101 a first semiconductor element, 102 a first semiconductor element on the electrode, the second semiconductor element 103, 104 is the second semiconductor element on the electrode, 105
は第三の半導体素子、106は第三の半導体素子上電極、107は第一の接着剤、108は第二の接着剤、1 The third semiconductor device, the third semiconductor element on the electrodes 106, 107 first adhesive 108 second adhesive, 1
09は第一の絶縁性樹脂、110は第二の絶縁性樹脂、 09 first insulating resin, 110 a second insulating resin,
111は第三の絶縁性樹脂、112は第一のめっき配線、113は第二のめっき配線、114は第一の絶縁性樹脂に形成された開口部、115は第二の絶縁性樹脂に形成された開口部、116は外部電極端子である。 111 third insulating resin 112 is first plated wiring, 113 opening the second plating wiring is 114 formed on the first insulating resin 115 formed on the second insulating resin has been opening, 116 denotes an external electrode terminal.

【0066】図6において、第二の半導体素子103 [0066] In FIG. 6, the second semiconductor element 103
は、第一の半導体素子101の上に、第一の半導体素子上電極102が露出するように、接着剤107を介して積層された構造である。 It is on the first semiconductor element 101, as the first semiconductor element on the electrode 102 is exposed, is laminated via an adhesive 107 structures.

【0067】第一の絶縁性樹脂109は、第一の半導体素子101、および第二の半導体素子103上に、少なくとも第一の半導体素子上電極102、または第二の半導体素子上電極104が開口するように形成されている。 [0067] The first insulating resin 109, on the first semiconductor element 101 and the second semiconductor element 103, at least a first semiconductor element on the electrode 102 or the second semiconductor element on the electrode 104, the opening It is formed so as to.

【0068】第一のめっき配線112は第一の絶縁性樹脂109上に形成され、さらに、第一の絶縁性樹脂に形成された開口部114を介して、少なくとも第一の半導体素子上電極102、または第二の半導体素子上電極1 [0068] The first plating wiring 112 is formed on the first insulating resin 109, further through the first insulating resin which is formed in the opening 114, on at least a first semiconductor element electrode 102 , or the second semiconductor element electrode 1
04と電気的に接続されている構造である。 04 and which is electrically the attached structure. このとき第一のめっき配線112は必ずしも第一の半導体素子上電極102、および第二の半導体素子上電極104と電気的に接続する必要はなく、また、第一の半導体素子上電極102と、第二の半導体素子上電極104が、第一の絶縁性樹脂109上に形成された第一のめっき配線11 In this case the first plated wiring 112 is not always necessary to connect the first semiconductor element on the electrode 102, and the second on the electrode 104 and the electrically semiconductor device also includes a first semiconductor element on the electrode 102, the second semiconductor element on the electrode 104, the first plated wiring 11 formed on the first insulating resin 109
2を介して電気的に接続されていてもよい。 2 may be electrically connected via a.

【0069】第三の半導体素子105は、第一のめっき配線112が形成された第二の半導体素子103の上に、少なくとも第二の半導体素子上電極104または、 [0069] The third semiconductor element 105, on the second semiconductor element 103 in which the first plating wiring 112 is formed, at least a second semiconductor element on the electrode 104 or,
第一のめっき配線112が露出するように、接着剤10 As the first plated wiring 112 is exposed, the adhesive 10
8を介して積層された構造である。 8 is a laminated structure via.

【0070】第二の絶縁性樹脂110は、第二の半導体素子105、および第三の半導体素子105上に、少なくとも第二の半導体素子上電極104、第三の半導体素子上電極106および、第一のめっき配線112のいずれかが開口するように形成されている。 [0070] The second insulating resin 110, on the second semiconductor element 105 and the third semiconductor element 105, at least a second semiconductor element on the electrode 104, and the third semiconductor element on the electrode 106, the any one of the plated wiring 112 is formed so as to open.

【0071】第二のめっき配線113は第二の絶縁性樹脂110上に形成され、さらに、第二の絶縁性樹脂に形成された開口部115を介して、少なくとも第二の半導体素子上電極104または、第三の半導体素子上電極1 [0071] The second plating wiring 113 is formed on the second insulating resin 110, further through the second opening 115 formed in the insulating resin, at least a second semiconductor element on the electrode 104 or, on the third semiconductor element electrode 1
06または、第一のめっき配線112と電気的に接続されている構造である。 06 or a structure which is electrically connected to the first plating wiring 112. このとき第二のめっき配線113 At this time, the second of the plated wiring 113
は、必ずしも第二の半導体素子上電極104、第三の半導体素子上電極106および、第一のめっき配線112 Is not necessarily the second semiconductor element on the electrode 104, and the third semiconductor element on the electrode 106, the first plating wiring 112
と電気的に接続する必要はなく、また、第二の半導体素子上電極104、第三の半導体素子上電極106および、第一のめっき配線112は、それぞれ第一の絶縁性樹脂109上に形成された第二のめっき配線113を介して電気的に接続されていてもよい。 And need not be electrically connected, also, the second semiconductor element on the electrode 104, the third semiconductor element on the electrode 106 and the first plated wiring 112 is formed on the first insulating resin 109 respectively it may be electrically connected via a second plated wiring 113.

【0072】ここで第一のめっき配線112および第二のめっき配線113の材質は電気特性上、銅が望ましい。 [0072] wherein the first plated wiring 112 and the material of the second plated wiring 113 on the electrical characteristics, copper is preferable.

【0073】また、このとき第二の半導体素子103および第三の半導体素子105の厚みは、200μm以下が望ましい。 [0073] The thickness of this time the second semiconductor element 103 and the third semiconductor element 105, or less desirably 200 [mu] m. また、接着剤107および接着剤108は絶縁性を有しかつ、線膨張係数は10ppm以下が望ましい。 The adhesive 107 and the adhesive 108 and has an insulating property, the linear expansion coefficient of less desirable 10 ppm.

【0074】第三の絶縁性樹脂111は、第二のめっき配線113の一部を開口するように形成されており、この開口部(図示せず)を介して外部電極端子116と第二のめっき配線113は電気的に接続されている構造である。 [0074] A third insulating resin 111 is formed so as to open a portion of the second plated wiring 113, the opening (not shown) of the external electrode terminals 116 and the second via plated wiring 113 is a structure that is electrically connected.

【0075】ここでは、3つの半導体素子を積層しているが、第三の半導体素子105の上にさらに、第四、第五と複数の半導体素子を積層してもよい。 [0075] Here, although the laminated three semiconductor elements, further on the third semiconductor element 105, the fourth, may be stacked fifth plurality of semiconductor elements.

【0076】(第三の実施形態の製造方法)図7は本発明の第三の実施形態に係る半導体装置の製造方法の例を示す断面図である。 [0076] The (third manufacturing method of the Embodiment) FIG. 7 is a sectional view showing an example of a manufacturing method of a semiconductor device according to a third embodiment of the present invention.

【0077】図7において、101は第一の半導体素子、102は第一の半導体素子上電極、103は第二の半導体素子、104は第二の半導体素子上電極、105 [0077] In FIG. 7, 101 the first semiconductor element, 102 a first semiconductor element on the electrode, the second semiconductor element 103, 104 is the second semiconductor element on the electrode, 105
は第三の半導体素子、106は第三の半導体素子上電極、107は第一の接着剤、108は第二の接着剤、1 The third semiconductor device, the third semiconductor element on the electrodes 106, 107 first adhesive 108 second adhesive, 1
09は第一の絶縁性樹脂、110は第二の絶縁性樹脂、 09 first insulating resin, 110 a second insulating resin,
111は第三の絶縁性樹脂、112は第一のめっき配線、113は第二のめっき配線、114は第一の絶縁性樹脂に形成された開口部、115は第二の絶縁性樹脂に形成された開口部、116は外部電極端子である。 111 third insulating resin 112 is first plated wiring, 113 opening the second plating wiring is 114 formed on the first insulating resin 115 formed on the second insulating resin has been opening, 116 denotes an external electrode terminal.

【0078】まず、図7−Aに示すように、第二の半導体素子103を第一の半導体素子101の上に第一の接着剤107によって接着する。 [0078] First, as shown in FIG. 7-A, adhered by the first adhesive 107 to the second semiconductor element 103 on the first semiconductor element 101. このとき第一の接着剤1 In this case the first adhesive 1
07は、液状の熱硬化型樹脂でも、フィルム状の熱硬化型樹脂でもよい。 07, even thermosetting liquid resin, or a film-like thermosetting resin. 接着剤107に液状の熱硬化型樹脂を用いた場合は、予め第一の半導体素子101上に適量塗布しておき、第二の半導体素子103を積層した後、高温槽またはホットプレートを用いて第一の接着剤107 When using the adhesive 107 in the liquid thermosetting resin is leave an appropriate amount coated on the previously first semiconductor element 101, after stacking the second semiconductor device 103, using a high-temperature bath or hot plate the first adhesive 107
を硬化する。 To cure the. また、第一の接着剤107にフィルム状の熱硬化型樹脂を用いた場合は、予め第二の半導体素子1 In the case of using a film-like thermosetting resin on the first adhesive 107, advance the second semiconductor element 1
03の裏面に貼り付けておき、第一の半導体素子101 03 paste them to the back surface, the first semiconductor element 101
または、第二の半導体素子103を加熱しながら、第一の半導体素子101に接着する。 Or, while heating the second semiconductor element 103 is bonded to the first semiconductor element 101.

【0079】次に、図7−Bに示すように、第一の絶縁性樹脂109を第一の半導体素子101および第二の半導体素子103上に塗布する。 [0079] Next, as shown in FIG. 7-B, applying a first insulating resin 109 on the first semiconductor element 101 and the second semiconductor element 103. このとき第一の絶縁性樹脂109には液状の感光性樹脂を用いて、印刷法または、スピンコートで塗布する。 At this time, the first insulating resin 109 by using a liquid photosensitive resin, a printing method or is applied by spin coating. ここで、第一の絶縁性樹脂109はフィルム状の感光性樹脂でもよい。 Here, first insulating resin 109 may be a film-shaped photosensitive resin. その後に、第一の絶縁性樹脂109を仮硬化し、第一の半導体素子上電極102および、第二の半導体素子上電極10 Thereafter, the first insulating resin 109 is temporarily cured, the first semiconductor element on the electrode 102 and, on the second semiconductor element electrodes 10
4を開口するように、露光、現像、本硬化する。 4 so as to open, exposed, developed, and cured.

【0080】次に、図7−Cに示すように、第一の絶縁性樹脂109上および、第一の絶縁性樹脂に形成された開口部114を介して、少なくとも第一の半導体素子上電極102または、第二の半導体素子上電極104の一部と電気的に接続するように、第一のめっき配線112 [0080] Next, as shown in FIG. 7-C, above the first insulating resin 109 and, via a first insulating resin which is formed in the opening 114, on at least a first semiconductor element electrode 102 or so as to connect a portion electrically the second semiconductor element on the electrode 104, the first plating wiring 112
をフォトリソによって形成する。 The formed by photolithography.

【0081】次に、図7−Dに示すように、第二の半導体素子103を第一の半導体素子101の上に第一の接着剤107によって接着するのと同様にして、第三の半導体素子105を第二の半導体素子103の上に、少なくとも第一のめっき配線112の一部が露出するように、第二の接着剤108によって接着する。 [0081] Next, as shown in FIG. 7-D, the second semiconductor element 103 in the same manner as bonding by means of a first adhesive 107 on the first semiconductor element 101, a third semiconductor the element 105 on the second semiconductor element 103, such that a portion of the at least a first plating wiring 112 is exposed, is adhered by a second adhesive 108.

【0082】次に、図7−Eに示すように、第一の絶縁性樹脂109を形成するのと同様の方法で、第二の絶縁性樹脂110を第一のめっき配線112の一部が開口するように形成する。 [0082] Next, as shown in FIG. 7-E, in a manner similar to forming the first insulating resin 109, is a second insulating resin 110 part of the first plating wiring 112 formed so as to open.

【0083】次に、図7−Fに示すように、第二の絶縁性樹脂110上に、第二の絶縁性樹脂に形成された開口部115を介して、少なくとも第一のめっき配線112 [0083] Next, as shown in FIG. 7-F, the second on the insulating resin 110, via a second opening 115 formed in the insulating resin, at least a first plating wiring 112
の一部と電気的に接続するように、第二のめっき配線1 As a portion electrically connected to the second plating wiring 1
13をフォトリソによって形成する。 13 is formed by photolithography a.

【0084】次に、図7−Gに示すように、第一の絶縁性樹脂109を形成するのと同様の方法で、第三の絶縁性樹脂111を第二のめっき配線113の一部が開口するように形成する。 [0084] Next, as shown in FIG. 7-G, in the same manner as forming the first insulating resin 109, a third insulating resin 111 is part of the second plated wiring 113 formed so as to open.

【0085】最後に、図7―Hに示すように外部電極端子116を第三の絶縁性樹脂111の開口部を介して第二のめっき配線113と電気的に接続する。 [0085] Finally, to connect the external electrode terminals 116 second plated wiring 113 and electrically through the opening in the third insulating resin 111 as shown in FIG. 7-H. ここで、外部電極端子116の接続法には、ボール転写法や、はんだ印刷法を用いる。 Here, the method of connecting the external electrode terminal 116, a ball transfer method and, using a solder printing method.

【0086】図7において、第一の半導体素子101は個片で図示しているが、個片に分割する前のウェハ状態で製造してもよい。 [0086] In FIG. 7, the first semiconductor element 101 is illustrated in pieces, it may be manufactured in a wafer state before the split into pieces. このときウェハ状態から個片への分割は、図7−Hに示す外部電極端子116を接続する工程の前または後に行うことが望ましい。 In this case the division of the wafer state to individual pieces is preferably carried out after or before the step of connecting the external electrode terminal 116 shown in FIG. 7-H.

【0087】(第四の実施形態)図8は本発明の第四の実施形態に係る半導体装置の例を示す断面図である。 [0087] (Fourth Embodiment) FIG. 8 is a sectional view showing an example of a semiconductor device according to a fourth embodiment of the present invention.

【0088】図8において、101は第一の半導体素子、102は第一の半導体素子上電極、103は第二の半導体素子、104は第二の半導体素子上電極、105 [0088] In FIG. 8, 101 first semiconductor element, 102 a first semiconductor element on the electrode, the second semiconductor element 103, 104 is the second semiconductor element on the electrode, 105
は第三の半導体素子、106は第三の半導体素子上電極、107は第一の接着剤、108は第二の接着剤、1 The third semiconductor device, the third semiconductor element on the electrodes 106, 107 first adhesive 108 second adhesive, 1
09は第一の絶縁性樹脂、110は第二の絶縁性樹脂、 09 first insulating resin, 110 a second insulating resin,
111は第三の絶縁性樹脂、112は第一のめっき配線、113は第二のめっき配線、114は第一の絶縁性樹脂に形成された開口部、115は第二の絶縁性樹脂に形成された開口部、116は外部電極端子、117は第二の半導体素子に形成された開口部、118は第三の半導体素子に形成された開口部である。 111 third insulating resin 112 is first plated wiring, 113 opening the second plating wiring is 114 formed on the first insulating resin 115 formed on the second insulating resin has been opening, 116 external electrode terminal, an opening portion formed in the second semiconductor element 117, 118 denotes an opening formed in the third semiconductor device.

【0089】図8において、第二の半導体素子103 [0089] In FIG. 8, the second semiconductor element 103
は、第一の半導体素子101の上に、第二の半導体素子に形成された開口部117によって、第一の半導体素子上電極2が露出するように、接着剤107を介して積層された構造である。 Is on the first semiconductor element 101, the second opening 117 formed in the semiconductor device, as the first semiconductor element on the electrode 2 is exposed, are laminated with an adhesive 107 structure it is.

【0090】第一の絶縁性樹脂109は、第二の半導体素子103上に、第一の半導体素子上電極102、および第二の半導体素子上電極104が開口するように形成されている。 [0090] The first insulating resin 109, on the second semiconductor element 103, a first semiconductor element on the electrode 102 and the second semiconductor element on the electrode 104, is formed so as to open.

【0091】第一のめっき配線112は第一の絶縁性樹脂109上に形成され、さらに、第一の絶縁性樹脂に形成された開口部114を介して、第二の半導体素子上電極104と、また、第一の絶縁性樹脂に形成された開口部114および、第二の半導体素子に形成された開口部117を介して第一の半導体素子上電極102と電気的に接続されている構造である。 [0091] The first plating wiring 112 is formed on the first insulating resin 109, further through the first insulating resin which is formed in the opening 114, a second semiconductor element on the electrode 104 in addition, the first insulating aperture 114 formed in the resin and are connected a second first electrically semiconductor element on the electrode 102 through an opening 117 formed in the semiconductor device structure it is. このとき第一のめっき配線112は必ずしも第一の半導体素子上電極102、および第二の半導体素子上電極104と電気的に接続する必要はなく、また、第一の半導体素子上電極102、および第二の半導体素子上電極104は、第一の絶縁性樹脂109上に形成された第一のめっき配線112を介して電気的に接続されていてもよい。 In this case the first plated wiring 112 is not always necessary to connect the first semiconductor element on the electrode 102, and the second on the electrode 104 and the electrically semiconductor device, also the first semiconductor element electrodes 102 and, the second semiconductor element on the electrode 104 may be electrically connected via the first plated wiring 112 formed on the first insulating resin 109.

【0092】第三の半導体素子105は、第一のめっき配線112が形成された第二の半導体素子103の上に、少なくとも、第三の半導体素子に形成された開口部118によって、第一のめっき配線112が露出するように、接着剤108を介して積層された構造である。 [0092] The third semiconductor element 105, on the second semiconductor element 103 in which the first plating wiring 112 is formed, at least, by a third opening 118 formed on the semiconductor element, the first as the plating wiring 112 exposed, it is laminated via adhesive 108 structures.

【0093】第二の絶縁性樹脂110は、第三の半導体素子105上に、少なくとも第三の半導体素子上電極1 [0093] The second insulating resin 110, on the third semiconductor element 105, at least on the third semiconductor element electrode 1
06、または、第一のめっき配線112が開口するように形成されている。 06, or, the first plating wiring 112 is formed so as to open.

【0094】第二のめっき配線113は第二の絶縁性樹脂110上に形成され、さらに、第二の絶縁性樹脂に形成された開口部115を介して、第三の半導体素子上電極106と、また、第二の絶縁性樹脂に形成された開口部115および、第三の半導体素子に形成された開口部118を介して、第一のめっき配線112と電気的に接続されている構造である。 [0094] The second plating wiring 113 is formed on the second insulating resin 110, further through the second opening 115 formed in the insulating resin, and the third semiconductor element on the electrode 106 in addition, the second insulating aperture 115 formed in the resin and, via a third opening 118 formed on the semiconductor element, a structure is electrically connected with the first plated wiring 112 is there. このとき第二のめっき配線1 At this time, the second plating wiring 1
13は、必ずしも第三の半導体素子上電極106または、第一のめっき配線112と電気的に接続する必要はなく、また、第三の半導体素子上電極106と、第一のめっき配線112は、第一の絶縁性樹脂109上に形成された第二のめっき配線113を介して電気的に接続されていてもよい。 13 are not necessarily or third semiconductor element on the electrode 106 is not necessary to connect the first plated wiring 112 electrically, also with the third semiconductor element on the electrode 106, the first plating wiring 112, it may be electrically connected via a second plated wiring 113 formed on the first insulating resin 109.

【0095】ここで第一のめっき配線112および第二のめっき配線113の材質は電気特性上、銅が望ましい。 [0095] wherein the first plated wiring 112 and the material of the second plated wiring 113 on the electrical characteristics, copper is preferable.

【0096】また、このとき第二の半導体素子103および第三の半導体素子105の厚みは、200[μm] [0096] The thickness of this time the second semiconductor element 103 and the third semiconductor element 105, 200 [[mu] m]
以下が望ましい。 The following is desirable. また、接着剤107および接着剤10 The adhesive 107 and the adhesive 10
8は絶縁性を有しかつ、線膨張係数は10[ppm]以下が望ましい。 8 and has an insulating property, coefficient of linear expansion is desirable 10 [ppm] or less.

【0097】第三の絶縁性樹脂111は、第二のめっき配線113の一部を開口するように形成されており、この開口部(図示せず)を介して外部電極端子116と第二のめっき配線113は電気的に接続されている構造である。 [0097] A third insulating resin 111 is formed so as to open a portion of the second plated wiring 113, the opening (not shown) of the external electrode terminals 116 and the second via plated wiring 113 is a structure that is electrically connected.

【0098】ここでは、3つの半導体素子を積層しているが、第三の半導体素子105の上にさらに、第四、第五と複数の半導体素子を積層してもよい。 [0098] Here, although the laminated three semiconductor elements, further on the third semiconductor element 105, the fourth, may be stacked fifth plurality of semiconductor elements.

【0099】(第四の実施形態の製造方法)図9は本発明の第四の実施形態に係る半導体装置の製造方法の例を示す断面図である。 [0099] Figure 9 (a manufacturing method of the fourth embodiment) is a sectional view showing an example of a manufacturing method of a semiconductor device according to a fourth embodiment of the present invention.

【0100】図9において、101は第一の半導体素子、102は第一の半導体素子上電極、103は第二の半導体素子、104は第二の半導体素子上電極、105 [0100] In FIG. 9, 101 a first semiconductor element, 102 a first semiconductor element on the electrode, the second semiconductor element 103, 104 is the second semiconductor element on the electrode, 105
は第三の半導体素子、106は第三の半導体素子上電極、107は第一の接着剤、108は第二の接着剤、1 The third semiconductor device, the third semiconductor element on the electrodes 106, 107 first adhesive 108 second adhesive, 1
09は第一の絶縁性樹脂、110は第二の絶縁性樹脂、 09 first insulating resin, 110 a second insulating resin,
111は第三の絶縁性樹脂、112は第一のめっき配線、113は第二のめっき配線、114は第一の絶縁性樹脂に形成された開口部、115は第二の絶縁性樹脂に形成された開口部、116は外部電極端子、117は第二の半導体素子に形成された開口部、118は第三の半導体素子に形成された開口部である。 111 third insulating resin 112 is first plated wiring, 113 opening the second plating wiring is 114 formed on the first insulating resin 115 formed on the second insulating resin has been opening, 116 external electrode terminal, an opening portion formed in the second semiconductor element 117, 118 denotes an opening formed in the third semiconductor device.

【0101】まず、図9−Aに示すように、第二の半導体素子103を第一の半導体素子101の上に第一の接着剤107によって接着する。 [0102] First, as shown in FIG. 9-A, adhered by the first adhesive 107 to the second semiconductor element 103 on the first semiconductor element 101. このとき第一の接着剤1 In this case the first adhesive 1
07は、液状の熱硬化型樹脂でも、フィルム状の熱硬化型樹脂でもよい。 07, even thermosetting liquid resin, or a film-like thermosetting resin. 接着剤107に液状の熱硬化型樹脂を用いた場合は、予め第一の半導体素子101上に適量塗布しておき、第二の半導体素子103を積層した後、高温槽またはホットプレートを用いて第一の接着剤107 When using the adhesive 107 in the liquid thermosetting resin is leave an appropriate amount coated on the previously first semiconductor element 101, after stacking the second semiconductor device 103, using a high-temperature bath or hot plate the first adhesive 107
を硬化する。 To cure the. また、第一の接着剤107にフィルム状の熱硬化型樹脂を用いた場合は、予め第二の半導体素子1 In the case of using a film-like thermosetting resin on the first adhesive 107, advance the second semiconductor element 1
03の裏面に貼り付けておき、第一の半導体素子101 03 paste them to the back surface, the first semiconductor element 101
または、第二の半導体素子103を加熱しながら、第一の半導体素子101に接着する。 Or, while heating the second semiconductor element 103 is bonded to the first semiconductor element 101.

【0102】次に、図9−Bに示すように、第一の絶縁性樹脂109を第一の半導体素子101および第二の半導体素子103上に塗布する。 [0102] Next, as shown in FIG. 9-B, applying a first insulating resin 109 on the first semiconductor element 101 and the second semiconductor element 103. このとき第一の絶縁性樹脂109には液状の感光性樹脂を用いて、印刷法または、スピンコートで塗布する。 At this time, the first insulating resin 109 by using a liquid photosensitive resin, a printing method or is applied by spin coating. ここで、第一の絶縁性樹脂109はフィルム状の感光性樹脂でもよい。 Here, first insulating resin 109 may be a film-shaped photosensitive resin.

【0103】次に、図9−Cに示すように、第一の絶縁性樹脂109を仮硬化、露光、現像、本硬化して第二の半導体素子上電極104を開口するとともに、第一の半導体素子上電極102が露出するように、第二の半導体素子103をエッチングして第二の半導体素子に形成された開口部117を形成する。 [0103] Next, as shown in FIG. 9-C, pre-curing the first insulating resin 109, exposure, development, as well as opening the second semiconductor element on the electrode 104 to the curing, the first as the semiconductor elements on the electrode 102 is exposed, to form a second semiconductor element 103 is etched second opening 117 formed in the semiconductor device.

【0104】エッチングには、第一の絶縁性樹脂109 [0104] The etching, the first insulating resin 109
をマスクとしたドライエッチングを用いる。 The use of dry etching using a mask.

【0105】次に、図9−Dに示すように、第一の絶縁性樹脂に形成された開口部114を介して第二の半導体素子上電極104の一部と、また、第一の絶縁性樹脂に形成された開口部114および、第二の半導体素子に形成された開口部117を介して、第一の半導体素子上電極102の一部と電気的に接続するように、第一の絶縁性樹脂109上に第一のめっき配線112をフォトリソによって形成する。 [0105] Next, as shown in FIG. 9-D, a portion of the second semiconductor element on the electrode 104 through the first insulating resin which is formed in the opening 114, also the first insulating opening 114 and formed rESIN, via a second opening 117 formed on the semiconductor element, so that a part electrically connected to the first semiconductor element on the electrode 102, the first a first plated wiring 112 is formed by photolithography on the insulating resin 109.

【0106】次に、図9−Eに示すように、第二の半導体素子103を第一の半導体素子101の上に第一の接着剤107によって接着するのと同様にして、第三の半導体素子105を第一の半導体素子103の上に第二の接着剤108によって接着する。 [0106] Next, as shown in FIG. 9-E, the second semiconductor element 103 in the same manner as bonding by means of a first adhesive 107 on the first semiconductor element 101, a third semiconductor bonding the element 105 on the first semiconductor element 103 by the second adhesive 108.

【0107】次に、図9−Fに示すように、第一の絶縁性樹脂109を形成するのと同様の方法で、第二の絶縁性樹脂110を形成する。 [0107] Next, as shown in FIG. 9-F, in a manner similar to forming the first insulating resin 109 to form a second insulating resin 110.

【0108】次に、図9−Gに示すように、第二の絶縁性樹脂110を仮硬化、露光、現像、本硬化して第三の半導体素子上電極106を開口するとともに、第一のめっき配線112の一部が露出するように、第三の半導体素子105をエッチングして第三の半導体素子に形成された開口部118を形成する。 [0108] Next, as shown in FIG. 9-G, temporarily cured second insulating resin 110, exposure, development, as well as opening the third semiconductor element on the electrode 106 to the curing, the first as part of the plated wiring 112 is exposed, to form a third semiconductor element 105 by etching the third opening 118 formed in the semiconductor device.

【0109】エッチングには、第二の絶縁性樹脂110 [0109] The etching, the second insulating resin 110
をマスクとしたドライエッチングを用いる。 The use of dry etching using a mask.

【0110】次に、図9−Hに示すように、第二の絶縁性樹脂に形成された開口部115を介して第三の半導体素子上電極106の一部と、また、第二の絶縁性樹脂に形成された開口部115および、第三の半導体素子に形成された開口部118を介して、第一のめっき配線11 [0110] Next, as shown in FIG. 9-H, a part of the second insulating resin through an opening 115 formed third semiconductor element on the electrode 106, also the second insulating opening 115 formed in the sexual resin and, via a third opening 118 formed in the semiconductor device, the first plated wiring 11
2の一部と電気的に接続するように、第二の絶縁性樹脂110上に第二のめっき配線113をフォトリソによって形成する。 To connect a portion of the 2 and electrically to form a second plated wiring 113 by photolithography on the second insulating resin 110.

【0111】次に、図9−Iに示すように、第二の絶縁性樹脂110を形成するのと同様の方法で、第三の絶縁性樹脂111を第二のめっき配線113の一部が開口するように形成する。 [0111] Next, as shown in FIG. 9-I, in the same manner as forming a second insulating resin 110, a third insulating resin 111 is part of the second plated wiring 113 formed so as to open.

【0112】最後に、図9―Jに示すように外部電極端子116を第三の絶縁性樹脂111の開口部を介して第二のめっき配線113と電気的に接続する。 [0112] Finally, to connect the external electrode terminals 116 third second plated wiring 113 electrically through the opening of the insulating resin 111 as shown in FIG. 9-J. ここで、外部電極端子116の接続法には、ボール転写法や、はんだ印刷法を用いる。 Here, the method of connecting the external electrode terminal 116, a ball transfer method and, using a solder printing method.

【0113】図9において、第一の半導体素子101は個片で図示しているが、個片に分割する前のウェハ状態で製造してもよい。 [0113] In FIG. 9, the first semiconductor element 101 is illustrated in pieces, it may be manufactured in a wafer state before the split into pieces. このときウェハ状態から個片への分割は、図7−Hに示す外部電極端子116を接続する工程の前または後に行うことが望ましい。 In this case the division of the wafer state to individual pieces is preferably carried out after or before the step of connecting the external electrode terminal 116 shown in FIG. 7-H.

【0114】 [0114]

【発明の効果】請求項1の構成により、第一の半導体素子と同じサイズで、2つの半導体素子を積層した半導体装置が得られる。 The of claim 1 configured according to the present invention, the same size as the first semiconductor element, a semiconductor device formed by stacking two semiconductor device can be obtained.

【0115】請求項2の構成により、第一の半導体素子と同じサイズで、3つ以上の半導体素子を積層した半導体装置が得られる。 [0115] The arrangement according to claim 2, the same size as the first semiconductor element, a semiconductor device is obtained by laminating three or more semiconductor elements.

【0116】請求項3の構成により、第一の半導体素子と同じサイズで、3つ以上の半導体素子を積層した半導体装置がえられるとともに、第二の半導体素子と第三の半導体素子のサイズを第一の半導体素子と同じサイズにすることができる。 [0116] The arrangement according to claim 3, in the same size as the first semiconductor element, together with the semiconductor device will be obtained by laminating three or more semiconductor devices, the size of the second semiconductor element and the third semiconductor element it can be the same size as the first semiconductor element.

【0117】請求項4の半導体装置の製造方法により、 [0117] The method according to claim 4,
請求項1記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 1.

【0118】請求項5の半導体装置の製造方法により、 [0118] The method according to claim 5,
請求項1記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device of claim 1, wherein it is possible to produce in a wafer state.

【0119】請求項6の半導体装置の製造方法により、 [0119] The method according to claim 6,
請求項2記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 2, wherein.

【0120】請求項7の半導体装置の製造方法により、 [0120] The manufacturing method of a semiconductor device according to claim 7,
請求項2記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device according to claim 2, wherein it is possible to produce in a wafer state.

【0121】請求項8の半導体装置の製造方法により、 [0121] The method according to claim 8,
請求項3記載の半導体素子を製造することができる。 It is possible to manufacture a semiconductor device according to claim 3, wherein.

【0122】請求項9の半導体装置の製造方法により、 [0122] The method according to claim 9,
請求項3記載の半導体素子をウェハ状態で製造することができる。 The semiconductor device according to claim 3, wherein it is possible to produce in a wafer state.

【0123】請求項10の半導体装置の製造方法により、請求項3記載の半導体素子を製造することができる。 [0123] The method according to claim 10, it is possible to manufacture a semiconductor device according to claim 3, wherein.

【0124】請求項11の半導体装置の製造方法により、請求項3記載の半導体素子をウェハ状態で製造することができる。 [0124] The method according to claim 11, the semiconductor device according to claim 3, wherein it is possible to produce in a wafer state.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第一の実施形態に係る半導体装置を示す斜視図 Perspective view of a semiconductor device according to a first embodiment of the present invention; FIG

【図2】本発明の第一の実施形態に係る半導体装置を示す断面図 Sectional view showing a semiconductor device according to a first embodiment of the present invention; FIG

【図3】本発明の第一の実施形態に係る半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a semiconductor device according to a first embodiment of the present invention; FIG

【図4】本発明の第二の実施形態に係る半導体装置を示す断面図 Sectional view showing a semiconductor device according to a second embodiment of the present invention; FIG

【図5】本発明の第二の実施形態に係る半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a semiconductor device according to a second embodiment of the present invention; FIG

【図6】本発明の第三の実施形態に係る半導体装置を示す断面図 Sectional view showing a semiconductor device according to a third embodiment of the invention; FIG

【図7】本発明の第三の実施形態に係る半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a semiconductor device according to a third embodiment of the present invention; FIG

【図8】本発明の第四の実施形態に係る半導体装置を示す断面図 Sectional view showing a semiconductor device according to a fourth embodiment of the invention; FIG

【図9】本発明の第四の実施形態に係る半導体装置の製造方法を示す断面図 Cross-sectional view showing a manufacturing method of a semiconductor device according to a fourth embodiment of the present invention; FIG

【図10】従来の半導体装置を示す断面図 Sectional view 10 shows a conventional semiconductor device

【符号の説明】 DESCRIPTION OF SYMBOLS

1 第一の半導体素子 2 第一の半導体素子上電極 3 第二の半導体素子 4 第二の半導体素子上電極 5 接着剤 6 第一の絶縁性樹脂 7 第二の絶縁性樹脂 8 めっき配線 9 外部電極端子 10 第一の絶縁性樹脂に形成された開口部 11 第三の半導体素子 12 第三の半導体素子上電極 101 第一の半導体素子 102 第一の半導体素子上電極 103 第二の半導体素子 104 第二の半導体素子上電極 105 第三の半導体素子 106 第三の半導体素子上電極 107 第一の接着剤 108 第二の接着剤 109 第一の絶縁性樹脂 110 第二の絶縁性樹脂 111 第三の絶縁性樹脂 112 第一のめっき配線 113 第二のめっき配線 114 第一の絶縁性樹脂に形成された開口部 115 第二の絶縁性樹脂に形成された開口部 116 外部電極端 1 first semiconductor device 2 first semiconductor element on the electrode 3 a second semiconductor element 4 the second semiconductor element on the electrode 5 adhesive 6 first insulating resin 7 second insulating resin 8 plated wiring 9 external electrode terminal 10 first opening 11 formed in the insulating resin third semiconductor element 12 a third semiconductor element on the electrode 101 first semiconductor element 102 the first semiconductor element on the electrode 103 the second semiconductor element 104 the second semiconductor element on the electrode 105 third semiconductor element 106 third semiconductor element on the electrode 107 first adhesive 108 second adhesive 109 first insulating resin 110 second insulating resin 111 third an insulating resin 112 first plated wiring 113 second plated wiring 114 first opening 115 formed in the insulating resin second insulating resin which is formed in the opening 116 outside the electrode end 子 117 第二の半導体素子に形成された開口部 118 第三の半導体素子に形成された開口部 201 第一の半導体素子 202 第一の半導体素子上電極 203 第二の半導体素子 204 第二の半導体素子上電極 205 インターポーザー 206 第一の金属細線 207 第二の金属細線 208 接着剤 209 封止樹脂 210 外部電極端子 211 インターポーザー上に形成された金属配線 Child 117 second semiconductor element opening 118 Third formed the opening 201 first formed on the semiconductor element semiconductor device 202 first semiconductor element on the electrode 203 the second semiconductor element 204 the second semiconductor element on the electrode 205 interposer 206 first thin metal wires 207 second forming metal wiring metal thin wires 208 adhesive 209 sealing resin 210 external electrode terminals 211 on the interposer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 長尾 浩一 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 金子 英之 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 松村 和彦 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 中岡 由紀子 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 佐原 隆一 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Koichi Nagao Osaka Takatsuki Saiwaicho No. 1 No. 1 Matsushita Electronics Co., Ltd. in the (72) inventor Hideyuki Kaneko Osaka Takatsuki Saiwaicho No. 1 No. 1 Matsushita Electronics within Co., Ltd. (72) inventor Kazuhiko Matsumura Osaka Takatsuki Saiwaicho No. 1 No. 1 Matsushita Electronics Co., Ltd. in the (72) inventor Yukiko Nakaoka Osaka Takatsuki Saiwaicho No. 1 No. 1 Matsushita Electronics within Co., Ltd. ( 72) inventor Ryuichi Sahara Osaka Takatsuki Saiwaicho No. 1 No. 1 Matsushita Electronics Co., Ltd. in

Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 主面上に複数の第一の電極が配列された第一の半導体素子と、 前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、主面上に複数の第二の電極が配列された第二の半導体素子と、 前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように形成された第一の絶縁性樹脂と、 前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に延在された、第一のめっき配線と、 少なくとも前記第一のめっき配線の一部の領域に開口部を有する、第二の絶縁 And 1. A first semiconductor device where the first electrodes of the plurality on the main surface are arranged, on a main surface of the first semiconductor element, are disposed at least said first electrode region It stacked so as to expose a portion of the second semiconductor element in which a plurality of second electrodes on the main surface are arranged, on the main surface of the first semiconductor element and the second semiconductor is formed on the main surface of the element, the area of ​​at least the first electrode is disposed and a first formed to have an opening in a part of a region where the second electrode is arranged an insulating resin, from said first electrode and said second electrode, through an opening formed in said first insulating layer, said extending in the first insulating layer, the first and plated wiring, having an opening in a part of the region of at least the first plated wiring, the second insulating 樹脂と、 前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子とからなる半導体装置。 And the resin, through the opening of the second insulating resin, is the first plating wiring and electrically connected, a semiconductor device comprising the external electrode terminal.
  2. 【請求項2】 主面上に複数の第一の電極が配列された第一の半導体素子と、 前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、第二、第三以降複数の半導体素子と、 前記第二、第三以降複数の半導体素子上に形成された電極と、 前記第一の半導体素子の主面上および、前記第二、第三以降複数の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二、第三以降複数の半導体素子上に形成された電極が配置されている領域の、一部に開口部を有するように形成された第一の絶縁性樹脂と、 前記第一の電極および、前記第二、第三以降複数の半導体素子上に形成された電極から、前記第一の絶縁層に形成された開口部を介し 2. A first semiconductor device where the first electrodes of the plurality on the main surface are arranged, on a main surface of the first semiconductor element, are disposed at least said first electrode region the stacked so as to expose a portion, a plurality of semiconductor devices second, third or later, the second, and the electrode formed on the third and later on a plurality of semiconductor elements, of the first semiconductor element principal plane and the second, formed on the main surface of the third and subsequent plurality of semiconductor elements, regions are arranged at least the first electrode and the second, third or later on a plurality of semiconductor elements the region where the formed electrode is arranged, a first insulating resin formed to have an opening portion, the first electrode and the second, third and subsequent plurality of semiconductor from formed on the device electrodes, through the opening formed in the first insulating layer 、前記第一の絶縁層上に延在された、第一のめっき配線と、 少なくとも前記第一のめっき配線上の一部の領域に開口部を有する、第二の絶縁性樹脂と、 前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子とからなる半導体装置。 , Said extending in the first insulating layer, a first plated wiring, having an opening in a part of the region on at least said first plated wiring, a second insulating resin, said first through the opening in the second insulating resin, it is connected the first plating wiring and electrically, the semiconductor device comprising the external electrode terminal.
  3. 【請求項3】 主面上に複数の第一の電極が配列された第一の半導体素子と、 前記第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように積層された、主面上に複数の第二の電極が配列された第二の半導体素子と、 前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に形成され、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように形成された第一の絶縁性樹脂と、 前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に延在された、第一のめっき配線と、 少なくとも前記第一のめっき配線が形成されている領域の一部を露出するよう 3. A first semiconductor device where the first electrodes of the plurality on the main surface are arranged, on a main surface of the first semiconductor element, are disposed at least said first electrode region It stacked so as to expose a portion of the second semiconductor element in which a plurality of second electrodes on the main surface are arranged, on the main surface of the first semiconductor element and the second semiconductor is formed on the main surface of the element, the area of ​​at least the first electrode is disposed and a first formed to have an opening in a part of a region where the second electrode is arranged an insulating resin, from said first electrode and said second electrode, through an opening formed in said first insulating layer, said extending in the first insulating layer, the first and plated wiring, so as to expose a portion of a region in which at least the first plating wiring is formed 積層された、主面上に複数の第三の電極が配列された第三の半導体素子と、 少なくとも前記第三の半導体素子の主面上に形成され、 Stacked, and the third semiconductor elements arranged plurality of third electrodes on the principal surface, are formed on the main surface of at least the third semiconductor element,
    少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に開口部を有するように形成された第二の絶縁性樹脂と、 少なくとも前記第三の電極および、前記第一のめっき配線から、第二の絶縁性樹脂の開口部を介して、第二の絶縁性樹脂上に延在された第二のめっき配線と、 少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、第三の絶縁性樹脂と、 前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外部電極端子とからなる半導体装置。 At least a region wherein the third electrode is arranged and a second insulating resin formed to have an opening part of a region in which the first plating wires are disposed, at least the first third electrodes and, from the first plating wiring through the opening of the second insulating resin, and a second plating wiring which runs in a second insulative resin, at least the second having an opening in a part of the area on the plated wiring, a third insulating resin, through an opening in the third insulating resin, is the second plated wiring electrically connected, semiconductor device comprising a external electrode terminal.
  4. 【請求項4】 複数の第一の電極が配置された第一の半導体素子の主面上に、前記第一の電極が配置されている領域が露出するように、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、 前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有する第一の絶縁性樹脂を形成する第二の工程と、 前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に第一のめっき配線を延在する第三の工程と、 少なくとも前記第一のめっき配線の一部の領域に開口部を有する、第二の絶縁性樹脂を形成する第四の工程と、 前記 4. A on the main surface of the first semiconductor element in which a plurality of first electrodes are arranged, as a region where the first electrode is disposed is exposed, the plurality over the main surface the a first step of laminating a second semiconductor device and second electrodes are arranged, said upper major surface of the first semiconductor element and, on the main surface of the second semiconductor device, at least the first area electrodes are disposed and a second step of forming a first insulating resin having an opening in a part of a region where the second electrodes are arranged, the first electrode and, from said second electrode, through an opening formed in said first insulating layer, and a third step of extending the first plated wiring on the first insulating layer, at least the first having an opening in a part of the region of the plating wiring, a fourth step of forming a second insulating resin, wherein 二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子を形成する第五の工程とを有することを特徴とする半導体装置の製造方法。 Through the opening in the second insulating resin, said being first plating wiring and electrically connected, a method of manufacturing a semiconductor device characterized by having a fifth step of forming an external electrode terminal.
  5. 【請求項5】 請求項4に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、および前記第四の工程を、前記第一の半導体素子がウェハの状態で行われ、 さらに、前記第一の半導体素子をウェハ状態から個片に分割する第六の工程とを有することを特徴とする半導体装置の製造方法。 5. A method of manufacturing a semiconductor device according to claim 4, at least, the first step, the second step, the third step, and the fourth step, the first semiconductor element is performed in a wafer state, further, a method of manufacturing a semiconductor device characterized by having a sixth step of dividing said first semiconductor device into individual pieces from a wafer state.
  6. 【請求項6】 主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように、第二、第三以降複数の半導体素子を積層する第一の工程と、 前記第一の半導体素子の主面上および、前記第二、第三以降複数の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二、第三以降複数の半導体素子上に形成された電極が配置されている領域の、一部に開口部を有するように、第一の絶縁性樹脂を形成する第二の工程と、 前記第一の電極および、前記第二、第三以降複数の半導体素子上に形成された電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第三の工程と、 少 6. A on the main surface of the first semiconductor device the first electrodes of the plurality on the main surface are arranged so as to expose a portion of the region where at least the first electrode is arranged second, a first step of laminating a plurality of semiconductor elements third or later, main surface and the first semiconductor element, the second, on the main surface of the third and subsequent plurality of semiconductor elements, at least region and the first electrode is disposed and the second, the region where the third and subsequent plurality of semiconductor elements formed on the electrode are arranged so as to have an opening in a part, the first of a second step of forming an insulating resin, said first electrode and said second, from the third and subsequent plurality of electrodes formed on a semiconductor device, the first insulating layer opening formed through the parts, the first insulating layer, and a third step of extending the first plated wiring, low なくとも前記第一のめっき配線上の一部の領域に開口部を有するように、第二の絶縁性樹脂を形成する第四の工程と、 前記第二の絶縁性樹脂の開口部を介して、前記第一のめっき配線と電気的に接続された、外部電極端子を形成する第五の工程とを有することを特徴とする半導体装置の製造方法。 Even so as to have an opening portion in a part of the area on the first plating wiring without a fourth step of forming a second insulating resin, through the opening of the second insulating resin the first plated wire and electrically connected, a method of manufacturing a semiconductor device characterized by having a fifth step of forming an external electrode terminal.
  7. 【請求項7】 請求項6に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、および前記第四の工程を、前記第一の半導体素子がウェハの状態で行われ、 さらに、前記第一の半導体素子をウェハ状態から個片に分割する第六の工程とを有することを特徴とする半導体装置の製造方法。 7. A method of manufacturing a semiconductor device according to claim 6, at least, the first step, the second step, the third step, and the fourth step, the first semiconductor element is performed in a wafer state, further, a method of manufacturing a semiconductor device characterized by having a sixth step of dividing said first semiconductor device into individual pieces from a wafer state.
  8. 【請求項8】 主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域の一部を露出するように、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、 前記第一の半導体素子の主面上および、前記第二の半導体素子の主面上に、少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に開口部を有するように第一の絶縁性樹脂を形成する第二の工程と、 前記第一の電極および、前記第二の電極から、前記第一の絶縁層に形成された開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第三の工程と、 少なくとも前記第一のめっき配線が形成されている領域の一部を露出するように、 8. A on the main surface of the first semiconductor device the first electrodes of the plurality on the main surface are arranged so as to expose a portion of the region where at least the first electrode is arranged a first step of laminating a second semiconductor device in which a plurality of second electrodes on the main surface are arranged, on the main surface of the first semiconductor element and the main surface of the second semiconductor device above, regions of at least the first electrode is disposed and the second where the second electrode forming a first insulating resin so as to have an opening in part of the area is located a step, from the first electrode and the second electrode, through the opening formed in the first insulating layer, said the first insulating layer, extending the first plated wiring a third step of, so as to expose a portion of the area where at least the first plating wiring is formed, 主面上に複数の第三の電極が配列された第三の半導体素子を積層する第四の工程と、 少なくとも前記第三の半導体素子の主面上に、少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に開口部を有するように、第二の絶縁性樹脂を形成する第五の工程と、少なくとも前記第三の電極および、前記第一のめっき配線から、第二の絶縁性樹脂の開口部を介して、第二の絶縁性樹脂上に、第二のめっき配線を延在する第六の工程と、 少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、第三の絶縁性樹脂を形成する第七の工程と、 前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外部電極端子を形成する第八の工程と、を有すること A fourth step of laminating a third semiconductor device having a plurality of third electrodes on the main surface are arranged, on the main surface of at least the third semiconductor element, it is disposed at least the third electrode and which region and to have an opening part of a region where the first plating wiring is disposed, and a fifth step of forming a second insulating resin, at least the third electrode and , from the first plating wiring through the opening of the second insulating resin, the second insulative resin, and a sixth step of extending the second plated wiring, at least the second having an opening in a part of the region on the plated wiring, a seventh step of forming a third insulating resin, through an opening in the third insulating resin, the second plated wiring electrically connected, having a eighth step of forming an external electrode terminal, a 特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim.
  9. 【請求項9】 請求項8に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、前記第四の工程、前記第五の工程、前記第六の工程、および前記第七の工程を、前記第一の半導体素子がウェハの状態で行われ、 さらに、前記第一の半導体素子をウェハ状態から個片に分割する第九の工程とを有することを特徴とする半導体装置の製造方法。 9. A method of manufacturing a semiconductor device according to claim 8, at least, the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, and the seventh step, the first semiconductor device is performed in a wafer state, further, the first semiconductor device and a ninth step of dividing the wafer state into individual pieces the method of manufacturing a semiconductor device characterized in that it comprises.
  10. 【請求項10】 主面上に複数の第一の電極が配列された第一の半導体素子の主面上に、主面上に複数の第二の電極が配列された第二の半導体素子を積層する第一の工程と、 前記第二の半導体素子の主面上に、第一の絶縁性樹脂を形成する第二の工程と、 少なくとも前記第一の電極が配置されている領域および、前記第二の電極が配置されている領域の一部に、第一の開口部を形成する第三の工程と、 前記第一の電極および、前記第二の電極から、前記第一開口部を介して、前記第一の絶縁層上に、第一のめっき配線を延在する第四の工程と、 少なくとも前記第一絶縁性樹脂上および、前記第一のめっき配線上に、主面上に複数の第三の電極が配列された第三の半導体素子を積層する第五の工程と、 前記第三の半導体素子の主面上に、第二 10. A over the main surface of the first semiconductor element in which a plurality of first electrodes on the main surface are arranged, the second semiconductor device in which a plurality of second electrodes on a main surface arranged a first step of laminating, on the principal surface of the second semiconductor element, a second step of forming a first insulating resin regions are arranged at least said first electrode and said the part of the area the second electrode is disposed, and a third step of forming a first opening, said first electrode and from said second electrode, through the first opening Te, the first insulating layer, and a fourth step of extending the first plated wiring, on at least said first insulating resin and, on the first plated wiring, the plurality over the main surface a fifth step in which the third electrode is stacked a third semiconductor elements arranged in, on the main surface of said third semiconductor device, the second 絶縁性樹脂を形成する第六の工程と少なくとも前記第三の電極が配置されている領域および、前記第一のめっき配線が配置されている領域の一部に、第二の開口部を形成する第七の工程と、 少なくとも前記第三の電極および、前記第一のめっき配線から、第二の開口部を介して、第二の絶縁性樹脂上に、第二のめっき配線を延在する第八の工程と、 少なくとも前記第二のめっき配線上の一部の領域に開口部を有する、第三の絶縁性樹脂を形成する第九の工程と、 前記第三の絶縁性樹脂の開口部を介して、前記第二のめっき配線と電気的に接続された、外部電極端子を形成する第十の工程とを有することを特徴とする半導体装置の製造方法。 Region at least the third electrode and the sixth step of forming an insulating resin is disposed and, in a part of a region where the first plating wiring is arranged to form a second opening a seventh step, at least the third electrode and, from the first plating wiring, via a second opening, the second insulative resin, the extending of the second plated wiring and eighth steps, has an opening in a part of the region on at least said second plated wiring, a ninth step of forming a third insulating resin, the opening of the third insulating resin through it, the second plated wire and electrically connected, a method of manufacturing a semiconductor device, characterized in that it comprises a tenth step of forming an external electrode terminal.
  11. 【請求項11】 請求項10に係る半導体装置の製造方法において、少なくとも、前記第一の工程、前記第二の工程、前記第三の工程、前記第四の工程、前記第五の工程、前記第六の工程、前記第七の工程、前記第八の工程、および前記第九の工程を、前記第一の半導体素子がウェハの状態で行われ、 さらに、前記第一の半導体素子をウェハ状態から個片に分割する第十一の工程とを有することを特徴とする半導体装置の製造方法。 11. A method of manufacturing a semiconductor device according to claim 10, at least, the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, the seventh step, the eighth step, and the ninth step, the first semiconductor device is performed in a wafer state, further, the first semiconductor device wafer state the method of manufacturing a semiconductor device characterized by having a eleventh step of dividing into individual pieces from.
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US8293574B2 (en) 2006-01-10 2012-10-23 Teramikros, Inc. Semiconductor device having a plurality of semiconductor constructs
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US8330279B2 (en) 2009-12-18 2012-12-11 Shinko Electric Industries Co., Ltd. Semiconductor device
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