JP2001135750A - Method for manufacturing semiconductor package substrate - Google Patents
Method for manufacturing semiconductor package substrateInfo
- Publication number
- JP2001135750A JP2001135750A JP34658599A JP34658599A JP2001135750A JP 2001135750 A JP2001135750 A JP 2001135750A JP 34658599 A JP34658599 A JP 34658599A JP 34658599 A JP34658599 A JP 34658599A JP 2001135750 A JP2001135750 A JP 2001135750A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- plating
- copper
- manufacturing
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、電子機器、電気機器、
コンピューター、通信機器等に用いられるＰＧＡ（ピン
グリッドアレイ）、ＢＧＡ（ボールグリッドアレイ）、
ＣＳＰ（チップサイズパッケージ）、ＭＣＭ（マルチチ
ップモジュール）、ＦＣ−ＢＧＡ（フリップチップ・ボ
ールグリッドアレイ）等に使用するプリント基板に関す
る。The present invention relates to electronic equipment, electrical equipment,
PGA (pin grid array), BGA (ball grid array), used for computers, communication devices, etc.
The present invention relates to a printed circuit board used for CSP (chip size package), MCM (multi-chip module), FC-BGA (flip chip ball grid array) and the like.
【０００２】[0002]
【従来の技術】半導体素子の高集積化に伴って、半導体
パッケージ用プリント基板の高密度化も必要となってい
る。特にこの分野で用いられるプリント配線板において
は、多層化、配線の細線化ばかりでなく、スルーホール
の微小化、高密度化が急激に進んでいる。即ち、従来用
いられてきたドリルによるスルーホールの形成から、レ
ーザーによるスルーホールの形成が試みられている。ス
ルーホールは、水分等の侵入による基板性能の低下を防
ぐために、絶縁性樹脂等で穴埋めすることが行われてい
る。2. Description of the Related Art As semiconductor devices become more highly integrated, it is necessary to increase the density of printed circuit boards for semiconductor packages. In particular, in printed wiring boards used in this field, not only multi-layering and thinning of wirings, but also miniaturization and high density of through holes are rapidly advancing. That is, formation of a through hole by a laser has been attempted instead of formation of a through hole by a conventionally used drill. The through holes are filled with an insulating resin or the like in order to prevent the performance of the substrate from being degraded due to intrusion of moisture or the like.
【０００３】[0003]
【発明が解決しようとする課題】スルーホールの穴埋め
は、ソルダーレジスト塗工時に行われたり、別工程にて
ソルダーレジスト塗工前に行われている。しかし、穴埋
めした樹脂が陥没したり、脱落したりする問題が発生す
る。又、半導体パッケージとなった後も穴埋め樹脂は水
分を透過するため、基板とモールド樹脂との間での剥
離、所謂ポップコーン現象の原因にもなっている。この
対策として、レーザーにより貫通孔を形成した後にメッ
キにより貫通個所を塞ぐ、即ち、封止（以下、貫通孔を
メッキで塞ぐことを封止と言う）する方法では、樹脂孔
及び銅箔孔の孔径のバラツキ，銅箔孔の形状のバラツキ
により、５０〜２０００個に及ぶ基板内の全ての孔を均
一にメッキ封止することは困難である。The filling of the through holes is performed at the time of solder resist coating, or is performed in a separate step before solder resist coating. However, there arises a problem that the filled resin collapses or falls off. In addition, even after the semiconductor package is formed, the filling resin transmits moisture, which causes peeling between the substrate and the mold resin, a so-called popcorn phenomenon. As a countermeasure against this, in a method of forming a through hole with a laser and then closing the penetrating portion by plating, that is, sealing (hereinafter, closing the through hole with plating is referred to as sealing), a resin hole and a copper foil hole are sealed. Due to variations in the hole diameters and variations in the shape of the copper foil holes, it is difficult to uniformly plate and seal all the holes in the substrate ranging from 50 to 2000.
【０００４】[0004]
【課題を解決するための手段】両面板におけるレーザー
穴加工において、片面銅箔のみを残した未貫通穴を形成
した後、エッチングにより貫通孔を形成し、孔をメッキ
で封止することで導通を確保し、封止された穴の位置に
半田ボール接続端子を形成した半導体パッケージ用基板
の製造方法である。本発明は、両面銅張積層板におい
て、 （１） レーザー加工により片面銅箔のみを残した未貫
通穴を形成する （２） エッチング処理により片面銅箔に貫通孔を形成
する （３） デスミア処理する （４） メッキにより貫通孔の封止、基板表裏の導通を
させる （５） 封止された孔の位置に半田接続用端子を形成す
る ことによる半導体パッケージ基板の製造方法である。本
発明は、両面銅張積層基板が、板厚０．０４〜０．４ｍ
ｍ、表裏の各銅箔厚５〜２０μｍであることによる半導
体パッケージ用基板の製造方法である。本発明は、レー
ザー加工が、炭酸ガスレーザーによるもので、穴径が７
０〜１２０μｍであることによる半導体パッケージ用基
板の製造方法である。本発明は、エッチング処理による
貫通孔径が、１０〜１００μｍであることによる半導体
パッケージ用基板の製造方法である。本発明は、エッチ
ング処理が過酸化水素又は過硫酸塩を含有する水溶液に
よる半導体パッケージ用基板の製造法である。本発明
は、デスミア処理が過マンガン酸カリウム又はクロム酸
カリウム水溶液による半導体パッケージ用基板の製造方
法である。本発明は、メッキによる貫通孔の封止が、無
電解メッキ及び／又は電解メッキで行うことによる半導
体パッケージ用基板の製造法である。本発明は、電解メ
ッキが電解銅メッキ液中で電流密度が０．３〜１．５Ａ
／ｄｍ２で行うことによる半導体パッケージ用基板の製
造方法である。Means for Solving the Problems In laser drilling on a double-sided board, after forming a non-through hole leaving only one-sided copper foil, a through-hole is formed by etching, and the hole is sealed by plating to conduct. And a method for manufacturing a semiconductor package substrate in which solder ball connection terminals are formed at the positions of sealed holes. The present invention relates to a double-sided copper-clad laminate, (1) forming a non-through hole leaving only one-sided copper foil by laser processing (2) forming a through-hole in the single-sided copper foil by etching (3) desmearing (4) A method of manufacturing a semiconductor package substrate by forming a through-hole by plating and providing conduction between the front and back of the substrate (5) Forming a solder connection terminal at the position of the sealed hole. The present invention provides a double-sided copper-clad laminate having a thickness of 0.04 to 0.4 m.
m, wherein the thickness of each of the front and back copper foils is 5 to 20 μm. In the present invention, the laser processing is performed by a carbon dioxide laser, and the hole diameter is 7 mm.
This is a method for manufacturing a semiconductor package substrate having a thickness of 0 to 120 μm. The present invention is a method for manufacturing a substrate for a semiconductor package, wherein the diameter of the through-hole by the etching treatment is 10 to 100 μm. The present invention is a method of manufacturing a semiconductor package substrate using an aqueous solution containing hydrogen peroxide or a persulfate in an etching process. The present invention is a method of manufacturing a substrate for a semiconductor package in which desmear treatment is performed using an aqueous solution of potassium permanganate or potassium chromate. The present invention is a method for manufacturing a substrate for a semiconductor package by sealing a through hole by plating by electroless plating and / or electrolytic plating. In the present invention, the electrolytic plating is carried out in an electrolytic copper plating solution having a current density of 0.3 to 1.5 A.
/ Dm 2 is a method for manufacturing a semiconductor package substrate.
【０００５】[0005]
【発明の実施の形態】本発明は、両面銅張積層板に、レ
ーザー加工により、未貫通穴を作り、エッチング処理に
より貫通孔を形成する。デスミア処理後、メッキにより
基板表裏の回路を導通させ、同時に、貫通孔の封止をす
る。メッキ封止された孔の銅箔の位置（以下、封止され
た銅箔の位置と言う）に半田接続用端子を形成すること
によるプリント基板の製造方法である。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a non-through hole is formed in a double-sided copper-clad laminate by laser processing, and a through hole is formed by etching. After the desmear treatment, the circuits on the front and back of the substrate are made conductive by plating, and at the same time, the through holes are sealed. This is a method of manufacturing a printed circuit board by forming a solder connection terminal at a position of a copper foil in a hole sealed by plating (hereinafter, referred to as a position of a sealed copper foil).
【０００６】本発明に使用する絶縁基材は、エポキシ樹
脂、ビスマレイミドトリアジン樹脂（ＢＴ樹脂）、ポリ
イミド樹脂、ＰＰＯ樹脂等或いはガラス繊維、ガラス
布、紙にこれらの樹脂を含浸させたプリプレーグであ
る。本発明に使用する銅箔は、厚さ：５−２０μｍ、好
ましくは、９〜１５μｍの電解銅箔である。プリプレー
グに銅箔を載せてプレス成形して、絶縁層厚：０．０４
〜０．４ｍｍの両面銅張積層板を形成する。The insulating base material used in the present invention is an epoxy resin, a bismaleimide triazine resin (BT resin), a polyimide resin, a PPO resin or the like, or a prepreg obtained by impregnating glass fiber, glass cloth, or paper with these resins. . The copper foil used in the present invention is an electrolytic copper foil having a thickness of 5 to 20 μm, preferably 9 to 15 μm. The copper foil is placed on the pre-plaque and press-formed, and the insulating layer thickness: 0.04
Form a double-sided copper-clad laminate of ~ 0.4 mm.
【０００７】本発明の、レーザー加工について詳述す
る。本発明で形成される穴の形状は、レーザーにより表
面の銅箔、絶縁層に穴を明け、底面の銅箔には孔が開い
ていない未貫通穴の状態となるように照射エネルギー、
パルス数、ビーム径をコントロールする。本発明に使用
するレーザーは、波長９〜１１μｍの炭酸ガスレーザー
穴明機を用いて行なう。 ビーム径：５０〜１５０μ
ｍ；出力×ショット数：（２０〜４０ｍＪ）×（１〜２
ｓｈｏｔ）＋（１０〜２０ｍＪ）×（１〜４ｓｈｏｔ）
で行い、表面銅箔の穴径は、平均穴径：９０〜１００μ
ｍの未貫通穴を形成する。本発明で形成される穴の表面
の穴径変動幅は、最小７０〜最大１２０μｍ、絶縁層の
底部の穴径は、３０〜１００μｍであれば、本発明を実
施するのに好ましい形状の穴である。The laser processing of the present invention will be described in detail. The shape of the hole formed in the present invention, the copper foil on the surface by laser, a hole in the insulating layer, the irradiation energy so that the copper foil on the bottom is in a state of a non-through hole with no holes,
Control the number of pulses and beam diameter. The laser used in the present invention is performed using a carbon dioxide laser drilling machine having a wavelength of 9 to 11 μm. Beam diameter: 50-150μ
m; output × number of shots: (20 to 40 mJ) × (1 to 2
shot) + (10-20 mJ) × (1-4 shot)
The hole diameter of the surface copper foil, average hole diameter: 90 ~ 100μ
m are formed. The hole diameter variation width of the surface of the hole formed in the present invention is 70 to 120 μm at the minimum, and the hole diameter at the bottom of the insulating layer is 30 to 100 μm. is there.
【０００８】本発明のエッチング処理による銅箔への貫
通孔の形成について説明する。本発明のエッチング処理
の薬液は、過硫酸塩、過酸化水素−硫酸等の水溶液であ
る。レーザー加工した基板を該薬液に漬ける或は該薬液
を吹き付ける方法で底部の銅箔に孔を明ける。更に、エ
ッチング処理により薬液と接触した銅面は、粗化され。
粗化された銅面は、後工程のメッキ銅の密着性が向上す
ると言う効果がある。る。The formation of a through-hole in a copper foil by the etching process of the present invention will be described. The chemical for the etching treatment of the present invention is an aqueous solution of persulfate, hydrogen peroxide-sulfuric acid, or the like. A hole is made in the bottom copper foil by immersing the laser-processed substrate in the chemical solution or spraying the chemical solution. Further, the copper surface that has come into contact with the chemical solution by the etching treatment is roughened.
The roughened copper surface has the effect of improving the adhesion of plated copper in a later step. You.
【０００９】レーザー照射により表面の銅箔は熔融蒸発
し、絶縁層の樹脂は分解蒸発して排出されるが、一部は
生成した未貫通孔の内部に滞留し、一方、穴底部の銅箔
は、レーザーによって穴は明いていないが熱により変質
しているため、エッチング処理において、排出されない
で滞留している銅や変質した銅箔と反応して溶解し、穴
底部の銅箔に細孔を明ける効果がある。しかし、本発明
のエッチング処理では、穴底部の径が、３０μｍより小
さいと、エッチング工程で貫通孔を形成できないことも
時々起こる。叉、孔が明いても、メッキ加工において、
特に、無電解メッキ加工において、メッキ液を攪拌した
り、振動したりしても、貫通孔部分に、メッキ成分を連
続して供給することが難しいため、メッキによる封止が
出来ないことがおこることがある。又、メッキで封止が
できても、基板の表裏の回路パターン間を接続させるメ
ッキ層の厚みが小さくなり過ぎて、メッキの接続信頼性
において問題となることがある。一方、１００μｍより
大きいと、通常のメッキ加工において、銅箔の貫通孔が
封止出来ないとか、メッキが厚くなり過ぎて、パターン
精度の低下が発生してしまうと言うことで、問題となる
こともある。一方、貫通孔の上部の径は、２００μｍよ
り大きいと、穴径が大きすぎて、高密度化を阻害する結
果となる。[0009] The copper foil on the surface is melted and evaporated by the laser irradiation, and the resin of the insulating layer is decomposed and evaporated and discharged, but a part of the resin stays inside the formed non-through hole, while the copper foil on the bottom of the hole is removed. The hole is not clear by the laser, but it is altered by heat, so in the etching process, it reacts with the copper that has stayed without being discharged and the dissolved copper foil and dissolves, resulting in pores in the copper foil at the bottom of the hole. Has the effect of clearing. However, in the etching process of the present invention, if the diameter of the hole bottom is smaller than 30 μm, it sometimes happens that a through hole cannot be formed in the etching process. Also, even if the hole is clear,
In particular, in electroless plating, even if the plating solution is stirred or vibrated, it is difficult to continuously supply plating components to the through-hole portions, so that sealing by plating cannot be performed. Sometimes. Further, even if sealing can be performed by plating, the thickness of the plating layer for connecting the circuit patterns on the front and back surfaces of the substrate becomes too small, which may cause a problem in connection reliability of plating. On the other hand, if the thickness is larger than 100 μm, a problem arises in that the through hole of the copper foil cannot be sealed in a normal plating process, or that the plating becomes too thick and the pattern accuracy is lowered, thereby causing a problem. There is also. On the other hand, if the diameter of the upper portion of the through hole is larger than 200 μm, the hole diameter is too large, which results in inhibiting high density.
【００１０】本発明のデスミア処理は、薬液は、過マン
ガン酸塩、クローム酸塩等の水溶液で、処理は５０〜９
０℃、１〜１５分で行なう。エッチング処理した基板
に、該薬液を吹き付ける方法あるいは浸漬する方法で、
表面の汚れ或は貫通孔内部の滞留物を分解、溶解、除去
する。レーザー加工において絶縁層の樹脂の分解物は、
一部孔より排出されないで内部に溜まったり、排出され
た分解物が表面の銅箔に付着するため、特に、底面銅箔
上に残留している樹脂及び樹脂分解物は、メッキの析
出、密着性の阻害要因となり、メッキの接着信頼性の低
下をもたらすため、デスミア処理が必要である。In the desmear treatment of the present invention, the chemical solution is an aqueous solution of permanganate, chromate, or the like, and the treatment is 50 to 9
Perform at 0 ° C. for 1 to 15 minutes. By spraying or dipping the chemical solution on the etched substrate,
It decomposes, dissolves, and removes dirt on the surface or retained matter inside the through-hole. In laser processing, the decomposition products of the resin of the insulating layer are:
Some of the decomposed substances are collected inside without being discharged from the holes, and the discharged decomposed substances adhere to the copper foil on the surface. Therefore, desmear treatment is required because it becomes a hindrance to the plating and lowers the adhesion reliability of the plating.
【００１１】本発明のメッキ加工による貫通孔の封止、
基板の表裏導通の方法について説明する。本発明のメッ
キ加工は、無電解メッキ及び／又は電解メッキの組み合
わせで行う。例えば、無電解メッキ、無電解メッキと電
解メッキあるいはダイレクトメッキを行う。メッキ加工
に用いられる金属は、金、銅、ニッケル、パラジュウム
等考えられるが、メッキ加工のやり易さ、基板の性能、
後工程の操作のしやすさ、コストのことを考慮すると、
銅メッキが好ましい。最初に無電解メッキを行って、貫
通孔の内壁絶縁層部分にも銅を析出させ、表裏の銅箔面
の導通を確保する。続いて、電解メッキで銅層を厚くし
貫通孔をメッキ金属により完全に封止する。メッキ時に
液の攪拌を十分行う等の操作により、貫通孔の内壁面に
も、メッキ金属層を均一に形成すると同時に、表裏及び
／又は内層回路と接続する。メッキ厚は、場所によって
多少異なるが、孔内で５〜２０μｍである。The sealing of the through hole by the plating process of the present invention,
A method of conducting the front and back of the substrate will be described. The plating of the present invention is performed by a combination of electroless plating and / or electrolytic plating. For example, electroless plating, electroless plating and electrolytic plating or direct plating are performed. Metals used for plating can be gold, copper, nickel, palladium, etc.
Considering the ease of operation in the post-process and cost,
Copper plating is preferred. First, electroless plating is performed to deposit copper also on the inner wall insulating layer portion of the through hole, thereby ensuring conduction between the front and back copper foil surfaces. Subsequently, the copper layer is thickened by electrolytic plating, and the through-hole is completely sealed with the plating metal. The plating metal layer is uniformly formed on the inner wall surface of the through hole by an operation such as sufficiently stirring the solution during plating, and at the same time, the plating metal layer is connected to the front and back and / or the inner layer circuit. The plating thickness varies slightly depending on the location, but is 5 to 20 μm in the hole.
【００１２】無電解メッキは、ＥＤＴＡ浴、ロッシェル
塩浴を用いる。続いて、電解メッキを行って、メッキ金
属を厚くして導通信頼性を確保する。電解メッキは、貫
通穴の完全な封止、基板の表裏導通を完全に確保する。
例えば、電解メッキ液は、硫酸銅或いはピロ燐酸銅を含
む電解液である。その液に漬けて、基板に電流を流し、
メッキ銅を析出させる。その電解銅メッキ液中での電流
密度は、０．３〜１．５Ａ／ｄｍ２である。エッチング
処理により、銅面は粗化されている上、デスミア処理に
より孔内部の異物がないので、メッキ銅の密着性は非常
に高くすることができる。For electroless plating, an EDTA bath and a Rochelle salt bath are used. Subsequently, electrolytic plating is performed to increase the thickness of the plated metal to ensure conduction reliability. Electroplating ensures complete sealing of the through hole and complete continuity of the front and back of the substrate.
For example, the electrolytic plating solution is an electrolytic solution containing copper sulfate or copper pyrophosphate. Immerse in the liquid, apply current to the substrate,
Deposit plated copper. Current density at the electrolytic copper plating solution is 0.3~1.5A / dm 2. The copper surface is roughened by the etching process, and there is no foreign matter inside the hole by the desmear process, so that the adhesion of the plated copper can be made very high.
【００１３】この時、メッキ加工の条件は、対象とする
基材によって多少違うが、普通に行われている方法で達
成できる。電解メッキの場合、電流密度を上げすぎる
と、均一性が悪くなったり（メッキ厚のバラツキ増
大）、メッキ焼けが発生したりして、後工程の回路形成
時に、精度の良いパターンにならないことがある。ま
た、電流密度が低いと生産性が低下し、好ましくない。At this time, the plating conditions are slightly different depending on the target substrate, but can be achieved by a commonly used method. In the case of electrolytic plating, if the current density is excessively increased, the uniformity is deteriorated (variation in plating thickness is increased), and plating is burned, so that an accurate pattern may not be formed when forming a circuit in a later process. is there. On the other hand, if the current density is low, the productivity decreases, which is not preferable.
【００１４】本発明の封止された底部銅箔の位置に半田
接続用端子を形成する方法について説明する。封止され
た孔の位置に径０．１〜１．０ｍｍの半田接続用端子を
形成する。封止された貫通孔の表裏の銅箔がメッキ銅で
接続しているので、半田ボールの搭載等の加熱をして
も、その面が剥離するあるいは変形するというような問
題は起こらない。A method for forming a solder connection terminal at the position of the sealed bottom copper foil according to the present invention will be described. A solder connection terminal having a diameter of 0.1 to 1.0 mm is formed at the position of the sealed hole. Since the copper foils on the front and back sides of the sealed through-hole are connected by plated copper, even if heating such as mounting of a solder ball does not cause a problem such as peeling or deformation of the surface.
【００１５】回路パターン形成後、通常、絶縁性物質で
スルーホールの被覆及び／又は充填が行われるが、本発
明においても、ソルダーレジストを孔内に埋め込み、パ
ターンの保護膜として塗布した。After the circuit pattern is formed, the through hole is usually covered and / or filled with an insulating material. In the present invention, a solder resist is embedded in the hole and applied as a protective film for the pattern.
【００１６】このようにして形成されたプリント配線板
は、半導体を塔載する半導体パッケージ用基板として用
いられる。The printed wiring board thus formed is used as a substrate for a semiconductor package on which a semiconductor is mounted.
【００１７】[0017]
【実施例】本発明は、公知方法（例えば、Ｃ．Ｆ．クー
ムズ編、安達芳夫、島田良乙共訳“プリント回路ハンド
ブック”近代科学社）に準じて実施した。理解を容易に
するため、図面で説明する。本発明に使用した絶縁基材
１は、両面に１２μｍの銅箔２を有する、厚さ０．２ｍ
ｍのガラス布入りＢＴ（ビスマレイミドトリアジン樹
脂）両面銅張積層板を使用したEXAMPLES The present invention was carried out according to a known method (for example, "Printed Circuit Handbook", edited by CF Coombs, translated by Yoshio Adachi and Yoshio Shimada, Modern Science Co., Ltd.). The description will be made with reference to the drawings for easy understanding. The insulating substrate 1 used in the present invention has a copper foil 2 of 12 μm on both sides and a thickness of 0.2 m.
BT (bismaleimide triazine resin) containing glass cloth with a double-sided copper-clad laminate
【図面１】。特開昭６１−９９５９６の方法を参考にし
て、基板表面を黒化処理して、レーザー穴明機（波長：
９．３μｍの炭酸ガスレーザー；出力７０Ｗ；パルス回
数５）により底面の片面銅箔のみを残した未貫通穴３を
形成する。未貫通穴の断面形状は、テーパー状で底面部
の径は３５μｍ、表面部の径は１００μｍになっていたDrawing 1 Referring to the method of JP-A-61-99596, the surface of the substrate is blackened, and a laser drilling machine (wavelength:
9.3 μm carbon dioxide laser; output 70 W; number of pulses 5) to form a non-through hole 3 leaving only a single-sided copper foil on the bottom surface. The cross-sectional shape of the non-through hole was tapered, the diameter of the bottom part was 35 μm, and the diameter of the surface part was 100 μm.
【図面２】。レーザー穴明け後の積層板を１２％過酸化
水素−６％硫酸溶液を（３０℃）、スプレー圧：２Ｋｇ
／ｍ２で基板面に吹き付けて、未貫通穴の底面銅箔に貫
通孔４が明いているのを確認した。続いて、２％過マン
ガン酸カリウム−２０％水酸化カリウム水溶液に漬け
て、貫通穴内の有機物を分解・溶解・除去したDrawing 2 The laminated plate after laser drilling was sprayed with 12% hydrogen peroxide-6% sulfuric acid solution (30 ° C.) and spray pressure: 2 kg
/ M 2 was sprayed onto the substrate surface, and it was confirmed that the through-hole 4 was clear on the bottom surface copper foil of the non-through-hole. Then, it was immersed in a 2% potassium permanganate-20% potassium hydroxide aqueous solution to decompose, dissolve, and remove organic substances in the through holes.
【図面３】。次に、無電解メッキによりメッキ銅５を析
出させDrawing 3. Next, plated copper 5 is deposited by electroless plating.
【図面４】（Ａ）、電解メッキによりメッキ銅６を析出
させたDrawing 4 (A), plated copper 6 was deposited by electrolytic plating
【図面４】（Ｂ）。無電解メッキは、ロッシェル塩浴に
て行い、貫通孔の絶縁層内壁及び上下銅層の表面にも厚
さ：０．５〜０．８μＭの銅を析出させて、上下銅層の
導通を行った。続いて、電解メッキ液中に基板を入れ
て、電流密度：１Ａ／ｄｍ２にて、貫通孔内にもメッキ
処理して銅厚を厚くすると同時に、孔底部の貫通孔を、
メッキ銅で封止し、表裏の銅層を接続した。メッキ厚
は、場所によって多少異なっていたが、穴の内壁部で１
０〜１２μｍになっていた。穴の断面を観察すると、銅
メッキされた貫通穴は、完全にメッキ封止され、封止さ
れた貫通穴の構造は、底面の銅層が完全にメッキ銅（１
０〜１２μｍ）で封止された構造７になっていて、接続
信頼性において、全く問題がないことが分かった。銅箔
２の上の無電解メッキ５と電解メッキ６のメッキ厚は、
均一に１５〜２０μｍであった。続いて、銅箔面に回路
パターンを形成して、封止された銅箔の位置に半田接続
用端子７を形成した。続いて、メッキ封止した穴を有す
る基板に、ソルダーレジストを塗布、穴埋め及びソルダ
ーレジストパターン８形成を行い半導体パッケージ用基
板を作製したDrawing 4 (B). The electroless plating is performed in a Rochelle salt bath, and copper having a thickness of 0.5 to 0.8 μM is deposited on the inner wall of the insulating layer of the through hole and the surface of the upper and lower copper layers to conduct the upper and lower copper layers. Was. Subsequently, the substrate was placed in an electrolytic plating solution, and at a current density of 1 A / dm 2 , plating was performed also in the through-hole to increase the copper thickness, and at the same time, the through-hole at the bottom of the hole was formed.
It sealed with plating copper, and the copper layer of the front and back was connected. The plating thickness was slightly different depending on the location.
It was 0 to 12 μm. Observing the cross section of the hole, the copper-plated through-hole is completely plated and sealed, and the structure of the sealed through-hole is such that the bottom copper layer is completely plated copper (1).
0 to 12 μm), and it was found that there was no problem in connection reliability. The plating thickness of the electroless plating 5 and the electrolytic plating 6 on the copper foil 2 is as follows:
It was 15 to 20 μm uniformly. Subsequently, a circuit pattern was formed on the copper foil surface, and solder connection terminals 7 were formed at the positions of the sealed copper foil. Subsequently, a solder resist was applied to the substrate having the plated-sealed holes, the holes were filled, and the solder resist pattern 8 was formed to produce a semiconductor package substrate.
【図６】。温度サイクル試験（−６５℃、３０分と１５
０℃、３０分で５００サイクル）により、銅箔のクラッ
クの発生を調べたが、クラックの発生は全く認められな
かった。FIG. Temperature cycle test (-65 ° C, 30 minutes and 15
(0 ° C, 30 minutes, 500 cycles), the occurrence of cracks in the copper foil was examined, but no cracks were observed.
【００１８】[0018]
【発明の効果】表裏パターンの導通を連続したメッキ層
で確保することができ、接続信頼性を向上することがで
き、高密度化に対応することが出来る。As described above, the conduction of the front and back patterns can be ensured by a continuous plating layer, the connection reliability can be improved, and it is possible to cope with high density.
【図１】両面板Fig. 1 Double-sided board
【図２】レーザー処理により未貫通穴のある基板FIG. 2 Substrate with a non-through hole by laser processing
【図３】エッチング処理により貫通孔のある基板FIG. 3 shows a substrate having a through-hole formed by etching.
【図４】（Ａ）無電解メッキにより上下銅箔が導通した
無電解メッキ銅の基板 （Ｂ）電解メッキによりメッキ銅でメッキ封止穴の形
成、および、電解メッキで厚化されたメッキ銅の基板FIG. 4 (A) Electroless plated copper substrate in which upper and lower copper foils are conducted by electroless plating. (B) Forming a plating sealing hole with electrolytic copper and plating copper thickened by electrolytic plating. Substrate
【図５】パターン形成後、ソルダーレジストパターン形
成、半田接続用端子形成された半導体パッケージ用基板FIG. 5 is a diagram illustrating a semiconductor package substrate on which a solder resist pattern is formed and a solder connection terminal is formed after pattern formation.
【図６】ソルダーレジストを塗布されたプリント配線板FIG. 6 is a printed wiring board coated with a solder resist.
１ 絶縁層 ２ 銅箔 ３ 未貫通穴 ４ 貫通孔 ５ 無電解メッキ銅 ６ 電解メッキ銅 ７ メッキ封止された孔 ８ 半田接続用端子 DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Copper foil 3 Non-through hole 4 Through hole 5 Electroless plated copper 6 Electroplated copper 7 Plated and sealed hole 8 Solder connection terminal
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１２年１月２４日（２０００．１．２
４）[Submission date] January 24, 2000 (2000.1.2
4)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１７[Correction target item name] 0017
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１７】[0017]
【実施例】本発明は、公知方法（例えば、Ｃ．Ｆ．クー
ムズ編、安達芳夫、島田良乙共訳“プリント回路ハンド
ブック”近代科学社）に準じて実施した。理解を容易に
するため、図面で説明する。本発明に使用した絶縁基材
１は、両面に１２μｍの銅箔２を有する、厚さ０．２ｍ
ｍのガラス布入りＢＴ（ビスマレイミドトリアジン樹
脂）両面銅張積層板を使用したEXAMPLES The present invention was carried out according to a known method (for example, "Printed Circuit Handbook", edited by CF Coombs, translated by Yoshio Adachi and Yoshio Shimada, Modern Science Co., Ltd.). The description will be made with reference to the drawings for easy understanding. The insulating substrate 1 used in the present invention has a copper foil 2 of 12 μm on both sides and a thickness of 0.2 m.
BT (bismaleimide triazine resin) containing glass cloth with a double-sided copper-clad laminate
【図面１】。特開昭６１−９９５９６の方法を参考にし
て、基板表面を黒化処理して、レーザー穴明機（波長：
９．３μｍの炭酸ガスレーザー；出力７０Ｗ；パルス回
数５）により底面の片面銅箔のみを残した未貫通穴３を
形成する。未貫通穴の断面形状は、テーパー状で底面部
の径は３５μｍ、表面部の径は１００μｍになっていたDrawing 1 Referring to the method of JP-A-61-99596, the surface of the substrate is blackened, and a laser drilling machine (wavelength:
9.3 μm carbon dioxide laser; output 70 W; number of pulses 5) to form a non-through hole 3 leaving only a single-sided copper foil on the bottom surface. The cross-sectional shape of the non-through hole was tapered, the diameter of the bottom part was 35 μm, and the diameter of the surface part was 100 μm.
【図面２】。レーザー穴明け後の積層板を１２％過酸化
水素−６％硫酸溶液を（３０℃）、スプレー圧：２Ｋｇ
／ｍ２で基板面に吹き付けて、未貫通穴の底面銅箔に貫
通孔４が明いているのを確認した。続いて、２％過マン
ガン酸カリウム−２０％水酸化カリウム水溶液に漬け
て、貫通穴内の有機物を分解・溶解・除去したDrawing 2 The laminated plate after laser drilling was sprayed with 12% hydrogen peroxide-6% sulfuric acid solution (30 ° C.) and spray pressure: 2 kg
/ M 2 was sprayed onto the substrate surface, and it was confirmed that the through-hole 4 was clear on the bottom surface copper foil of the non-through-hole. Then, it was immersed in a 2% potassium permanganate-20% potassium hydroxide aqueous solution to decompose, dissolve, and remove organic substances in the through holes.
【図面３】。次に、無電解メッキによりメッキ銅５を析
出させDrawing 3. Next, plated copper 5 is deposited by electroless plating.
【図面４】（Ａ）、電解メッキによりメッキ銅６を析出
させたDrawing 4 (A), plated copper 6 was deposited by electrolytic plating
【図面４】（Ｂ）。無電解メッキは、ロッシェル塩浴に
て行い、貫通孔の絶縁層内壁及び上下銅層の表面にも厚
さ：０．５〜０．８μＭの銅を析出させて、上下銅層の
導通を行った。続いて、電解メッキ液中に基板を入れ
て、電流密度：１Ａ／ｄｍ２にて、貫通孔内にもメッキ
処理して銅厚を厚くすると同時に、孔底部の貫通孔を、
メッキ銅で封止し、表裏の銅層を接続した。メッキ厚
は、場所によって多少異なっていたが、穴の内璧部で１
０〜１２μｍになっていた。穴の断面を観察すると、銅
メッキされた貫通穴は、完全にメッキ封止され、封止さ
れた貫通穴の構造は、底面の銅層が完全にメッキ銅（１
０〜１２μｍ）で封止された構造７になっていて、接続
信頼性において、全く問題がないことが分かった。銅箔
２の上の無電解メッキ５と電解メッキ６のメッキ厚は、
均一に１５〜２０μｍであった。続いて、銅箔面に回路
パターンを形成した。ソルダーレジストを塗布、穴埋め
及びソルダーレジストパターン形成を行いメッキ封止さ
れた孔７の位置に半田接続用端子８を有する半導体パッ
ケージ用基板を作製した Drawing 4 (B). The electroless plating is performed in a Rochelle salt bath, and copper having a thickness of 0.5 to 0.8 μM is deposited on the inner wall of the insulating layer of the through hole and the surface of the upper and lower copper layers to conduct the upper and lower copper layers. Was. Subsequently, the substrate was placed in an electrolytic plating solution, and at a current density of 1 A / dm 2 , plating was performed also in the through-hole to increase the copper thickness, and at the same time, the through-hole at the bottom of the hole was formed.
It sealed with plating copper, and the copper layer of the front and back was connected. The plating thickness was slightly different depending on the location.
It was 0 to 12 μm. Observing the cross section of the hole, the copper-plated through-hole is completely plated and sealed, and the structure of the sealed through-hole is such that the bottom copper layer is completely plated copper (1).
0 to 12 μm), and it was found that there was no problem in connection reliability. The plating thickness of the electroless plating 5 and the electrolytic plating 6 on the copper foil 2 is as follows:
It was 15 to 20 μm uniformly. Subsequently, a circuit pattern was formed on the copper foil surface . Apply solder resist and fill holes
And solder-resist pattern formation and plating sealing
Semiconductor package having solder connection terminals 8 at the positions of the holes 7
Fabricated a cage substrate
【図面５】。 温度サイクル試験（−６５℃、３０分と１
５０℃、３０分で５００サイクル）により、銅箔のクラ
ックの発生を調べたが、クラックの発生は全く認められ
なかった。 Drawing 5. Temperature cycle test (-65 ° C, 30 minutes and 1
The occurrence of cracks in the copper foil was examined by 500 cycles at 50 ° C. for 30 minutes), but no occurrence of cracks was observed.
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Correction target item name] Brief description of drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図面の簡単な説明】[Brief description of the drawings]
【図１】両面板Fig. 1 Double-sided board
【図２】レーザー処理により未貫通穴のある基板FIG. 2 Substrate with a non-through hole by laser processing
【図３】エッチング処理により貫通孔のある基板FIG. 3 shows a substrate having a through-hole formed by etching.
【図４】（Ａ）無電解メッキにより上下銅箔が導通した
無電解メッキ銅の基板 （Ｂ）電解メッキによりメッキ銅でメッキ封止穴の形
成、および、電解メッキで厚化されたメッキ銅の基板 FIG. 4 (A) Electroless plated copper substrate in which upper and lower copper foils are conducted by electroless plating. (B) Forming a plating sealing hole with electrolytic copper and plating copper thickened by electrolytic plating. Substrate
【図５】ソルダーレジストパターンを形成したプリントFIG. 5 is a print on which a solder resist pattern is formed.
配線板Wiring board
【符号の説明】 １ 絶縁層 ２ 銅箔 ３ 未貫通穴 ４ 貫通孔 ５ 無電解メッキ銅 ６ 電解メッキ銅 ７ メッキ封止された孔 ８ 半田接続用端子[Description of Signs] 1 Insulating layer 2 Copper foil 3 Non-through hole 4 Through hole 5 Electroless plated copper 6 Electroplated copper 7 Plated and sealed hole 8 Solder connection terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉岡 成康 愛知県豊田市神池町２丁目1236番地 日本 サーキット工 業株式会社内 (72)発明者 河原崎 幸浩 愛知県豊田市神池町２丁目1236番地 日本 サーキット工 業株式会社内 Ｆターム(参考） 5E317 AA01 AA24 BB03 BB12 CC32 CC33 CC39 CD01 CD25 CD27 CD32 GG09 GG14 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shigeyasu Yoshioka 2- 1236 Kamiike-cho, Toyota-shi, Aichi Japan Inside Circuit Industry Co., Ltd. (72) Inventor Yukihiro Kawarazaki 2- 1236 Kamiike-cho, Toyota-shi, Aichi Japan Circuit F-term (reference) in Kogyo Co., Ltd. 5E317 AA01 AA24 BB03 BB12 CC32 CC33 CC39 CD01 CD25 CD27 CD32 GG09 GG14
Claims (8)
穴を形成する （２）エッチング処理により片面銅箔に貫通孔を形成す
る （３）デスミア処理をする （４）メッキにより貫通孔の封止、基板表裏の導通をさ
せる （５）封止された孔の位置に半田接続用端子を形成する ことを特徴とする半導体パッケージ用基板の製造方法1. In a double-sided copper-clad laminate, (1) forming a non-through hole leaving only one-sided copper foil by laser processing; (2) forming a through-hole in the single-sided copper foil by etching; (3) desmear Processing (4) Sealing of through-holes by plating and conduction between the front and back of the substrate (5) A method for manufacturing a semiconductor package substrate, characterized by forming solder connection terminals at the positions of the sealed holes.
０．４ｍｍ、表裏の各銅箔厚５〜２０μｍであることを
特徴とする請求項１の半導体パッケージ用基板の製造方
法2. The double-sided copper-clad laminate has an insulating layer thickness of 0.04 to 0.04.
2. The method for manufacturing a substrate for a semiconductor package according to claim 1, wherein the thickness of each of the front and back copper foils is 5 to 20 [mu] m.
もので、穴径が７０〜１２０μｍであることを特徴とす
る請求項１の半導体パッケージ用基板の製造方法3. The method for manufacturing a semiconductor package substrate according to claim 1, wherein the laser processing is performed by a carbon dioxide gas laser, and the hole diameter is 70 to 120 μm.
における貫通孔径が、１０〜１００μｍであることを特
徴とする請求項１の半導体パッケージ用基板の製造方法4. The method for manufacturing a semiconductor package substrate according to claim 1, wherein the diameter of the through hole in the single-sided copper foil formed by the etching treatment is 10 to 100 μm.
を含有する水溶液によることを特徴とする請求項４のプ
リント配線板の製造法5. The method for manufacturing a printed wiring board according to claim 4, wherein the etching treatment is performed with an aqueous solution containing hydrogen peroxide or persulfate.
クロム酸カリウム水溶液によることを特徴とする請求項
１のプリント配線板の製造方法6. The method for manufacturing a printed wiring board according to claim 1, wherein the desmear treatment is performed with an aqueous solution of potassium permanganate or potassium chromate.
キ及び／又は電解メッキで行うことを特徴とする請求項
１のプリント配線板の製造法7. The method for manufacturing a printed wiring board according to claim 1, wherein the sealing of the through holes by plating is performed by electroless plating and / or electrolytic plating.
が０．３〜１．５Ａ／ｄｍ２で行うことを特徴とする請
求項７のプリント配線板の製造方法8. The method according to claim 7, wherein the electrolytic plating is performed in an electrolytic copper plating solution at a current density of 0.3 to 1.5 A / dm 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34658599A JP4129666B2 (en) | 1999-11-01 | 1999-11-01 | Manufacturing method of substrate for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34658599A JP4129666B2 (en) | 1999-11-01 | 1999-11-01 | Manufacturing method of substrate for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001135750A true JP2001135750A (en) | 2001-05-18 |
| JP4129666B2 JP4129666B2 (en) | 2008-08-06 |
Family
ID=18384426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34658599A Expired - Fee Related JP4129666B2 (en) | 1999-11-01 | 1999-11-01 | Manufacturing method of substrate for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4129666B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227648A (en) * | 2006-02-23 | 2007-09-06 | Sharp Corp | Printed wiring board, and method for manufacturing printed wiring board |
| CN100359655C (en) * | 2005-05-27 | 2008-01-02 | 江苏长电科技股份有限公司 | Planar salient point type technique for packaging intergrate circuit or discrete component |
| CN100369223C (en) * | 2005-05-27 | 2008-02-13 | 江苏长电科技股份有限公司 | Plane button type packing technology of integrated circuit or discrete component and its packing structure |
| WO2013042582A1 (en) | 2011-09-22 | 2013-03-28 | 上村工業株式会社 | Desmear solution and desmear method |
| WO2013160994A1 (en) * | 2012-04-24 | 2013-10-31 | 三共化成株式会社 | Plated structure of through-hole |
| CN111263518A (en) * | 2020-01-22 | 2020-06-09 | 惠州中京电子科技有限公司 | Manufacturing method of packaging substrate of novel LED electronic display screen |
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| JP2021150311A (en) | 2020-03-16 | 2021-09-27 | キオクシア株式会社 | Semiconductor device |
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1999
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359655C (en) * | 2005-05-27 | 2008-01-02 | 江苏长电科技股份有限公司 | Planar salient point type technique for packaging intergrate circuit or discrete component |
| CN100369223C (en) * | 2005-05-27 | 2008-02-13 | 江苏长电科技股份有限公司 | Plane button type packing technology of integrated circuit or discrete component and its packing structure |
| JP2007227648A (en) * | 2006-02-23 | 2007-09-06 | Sharp Corp | Printed wiring board, and method for manufacturing printed wiring board |
| WO2013042582A1 (en) | 2011-09-22 | 2013-03-28 | 上村工業株式会社 | Desmear solution and desmear method |
| KR20140063855A (en) | 2011-09-22 | 2014-05-27 | 우에무라 고교 가부시키가이샤 | Desmear solution and desmear method |
| WO2013160994A1 (en) * | 2012-04-24 | 2013-10-31 | 三共化成株式会社 | Plated structure of through-hole |
| JP5753628B2 (en) * | 2012-04-24 | 2015-07-22 | 三共化成株式会社 | Through-hole plating structure |
| CN111263518A (en) * | 2020-01-22 | 2020-06-09 | 惠州中京电子科技有限公司 | Manufacturing method of packaging substrate of novel LED electronic display screen |
| CN111263518B (en) * | 2020-01-22 | 2021-12-07 | 惠州中京电子科技有限公司 | Manufacturing method of packaging substrate of LED electronic display screen |
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