JP4129666B2 - Manufacturing method of substrate for semiconductor package - Google Patents

Manufacturing method of substrate for semiconductor package Download PDF

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Publication number
JP4129666B2
JP4129666B2 JP34658599A JP34658599A JP4129666B2 JP 4129666 B2 JP4129666 B2 JP 4129666B2 JP 34658599 A JP34658599 A JP 34658599A JP 34658599 A JP34658599 A JP 34658599A JP 4129666 B2 JP4129666 B2 JP 4129666B2
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Prior art keywords
hole
substrate
plating
copper
manufacturing
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JP34658599A
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JP2001135750A (en
Inventor
良彦 関根
章雅 田中
徹 山田
成康 吉岡
幸浩 河原崎
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Mitsubishi Gas Chemical Co Inc
Japan Circuit Industrial Co Ltd
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Mitsubishi Gas Chemical Co Inc
Japan Circuit Industrial Co Ltd
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Description

【0001】
【発明の属する分野】本発明は、電子機器、電気機器、コンピューター、通信機器等に用いられるPGA(ピングリッドアレイ)、BGA(ボールグリッドアレイ)、CSP(チップサイズパッケージ)、MCM(マルチチップモジュール)、FC−BGA(フリップチップ・ボールグリッドアレイ)等に使用するプリント基板に関する。
【0002】
【従来の技術】
半導体素子の高集積化に伴って、半導体パッケージ用プリント基板の高密度化も必要となっている。特にこの分野で用いられるプリント配線板においては、多層化、配線の細線化ばかりでなく、スルーホールの微小化、高密度化が急激に進んでいる。即ち、従来用いられてきたドリルによるスルーホールの形成から、レーザーによるスルーホールの形成が試みられている。スルーホールは、水分等の侵入による基板性能の低下を防ぐために、絶縁性樹脂等で穴埋めすることが行われている。
【0003】
【発明が解決しようとする課題】
スルーホールの穴埋めは、ソルダーレジスト塗工時に行われたり、別工程にてソルダーレジスト塗工前に行われている。しかし、穴埋めした樹脂が陥没したり、脱落したりする問題が発生する。又、半導体パッケージとなった後も穴埋め樹脂は水分を透過するため、基板とモールド樹脂との間での剥離、所謂ポップコーン現象の原因にもなっている。この対策として、レーザーにより貫通孔を形成した後にメッキにより貫通個所を塞ぐ、即ち、封止(以下、貫通孔をメッキで塞ぐことを封止と言う)する方法では、樹脂孔及び銅箔孔の孔径のバラツキ,銅箔孔の形状のバラツキにより、50〜2000個に及ぶ基板内の全ての孔を均一にメッキ封止することは困難である。
【0004】
【課題を解決するための手段】
両面板におけるレーザー穴加工において、片面銅箔のみを残した未貫通穴を形成した後、エッチングにより貫通孔を形成し、孔をメッキで封止することで導通を確保し、封止された穴の位置に半田ボール接続端子を形成した半導体パッケージ用基板の製造方法である。
本発明は、両面銅張積層板において、
(1) レーザー加工により片面銅箔のみを残した未貫通穴を形成する
(2) エッチング処理により片面銅箔に貫通孔を形成する
(3) デスミア処理する
(4) メッキにより貫通孔の封止、基板表裏の導通をさせる
(5) 封止された孔の位置に半田接続用端子を形成する
ことによる半導体パッケージ基板の製造方法である。
本発明は、両面銅張積層基板が、板厚0.04〜0.4mm、表裏の各銅箔厚5〜20μmであることによる半導体パッケージ用基板の製造方法である。
本発明は、レーザー加工が、炭酸ガスレーザーによるもので、穴径が70〜120μmであることによる半導体パッケージ用基板の製造方法である。
本発明は、エッチング処理による貫通孔径が、10〜100μmであることによる半導体パッケージ用基板の製造方法である。
本発明は、エッチング処理が過酸化水素又は過硫酸塩を含有する水溶液による半導体パッケージ用基板の製造法である。
本発明は、デスミア処理が過マンガン酸カリウム又はクロム酸カリウム水溶液による半導体パッケージ用基板の製造方法である。
本発明は、メッキによる貫通孔の封止が、無電解メッキ及び/又は電解メッキで行うことによる半導体パッケージ用基板の製造法である。
本発明は、電解メッキが電解銅メッキ液中で電流密度が0.3〜1.5A/dmで行うことによる半導体パッケージ用基板の製造方法である。
【0005】
【発明の実施の形態】
本発明は、両面銅張積層板に、レーザー加工により、未貫通穴を作り、エッチング処理により貫通孔を形成する。デスミア処理後、メッキにより基板表裏の回路を導通させ、同時に、貫通孔の封止をする。メッキ封止された孔の銅箔の位置(以下、封止された銅箔の位置と言う)に半田接続用端子を形成することによるプリント基板の製造方法である。
【0006】
本発明に使用する絶縁基材は、エポキシ樹脂、ビスマレイミドトリアジン樹脂(BT樹脂)、ポリイミド樹脂、PPO樹脂等或いはガラス繊維、ガラス布、紙にこれらの樹脂を含浸させたプリプレーグである。本発明に使用する銅箔は、厚さ:5−20μm、好ましくは、9〜15μmの電解銅箔である。プリプレーグに銅箔を載せてプレス成形して、絶縁層厚:0.04〜0.4mmの両面銅張積層板を形成する。
【0007】
本発明の、レーザー加工について詳述する。
本発明で形成される穴の形状は、レーザーにより表面の銅箔、絶縁層に穴を明け、底面の銅箔には孔が開いていない未貫通穴の状態となるように照射エネルギー、パルス数、ビーム径をコントロールする。本発明に使用するレーザーは、波長9〜11μmの炭酸ガスレーザー穴明機を用いて行なう。 ビーム径:50〜150μm;出力×ショット数:(20〜40mJ)×(1〜2shot)+(10〜20mJ)×(1〜4shot)で行い、表面銅箔の穴径は、平均穴径:90〜100μmの未貫通穴を形成する。本発明で形成される穴の表面の穴径変動幅は、最小70〜最大120μm、絶縁層の底部の穴径は、30〜100μmであれば、本発明を実施するのに好ましい形状の穴である。
【0008】
本発明のエッチング処理による銅箔への貫通孔の形成について説明する。
本発明のエッチング処理の薬液は、過硫酸塩、過酸化水素−硫酸等の水溶液である。レーザー加工した基板を該薬液に漬ける或は該薬液を吹き付ける方法で底部の銅箔に孔を明ける。更に、エッチング処理により薬液と接触した銅面は、粗化され。粗化された銅面は、後工程のメッキ銅の密着性が向上すると言う効果がある。
る。
【0009】
レーザー照射により表面の銅箔は熔融蒸発し、絶縁層の樹脂は分解蒸発して排出されるが、一部は生成した未貫通孔の内部に滞留し、一方、穴底部の銅箔は、レーザーによって穴は明いていないが熱により変質しているため、エッチング処理において、排出されないで滞留している銅や変質した銅箔と反応して溶解し、穴底部の銅箔に細孔を明ける効果がある。しかし、本発明のエッチング処理では、穴底部の径が、30μmより小さいと、エッチング工程で貫通孔を形成できないことも時々起こる。叉、孔が明いても、メッキ加工において、特に、無電解メッキ加工において、メッキ液を攪拌したり、振動したりしても、貫通孔部分に、メッキ成分を連続して供給することが難しいため、メッキによる封止が出来ないことがおこることがある。又、メッキで封止ができても、基板の表裏の回路パターン間を接続させるメッキ層の厚みが小さくなり過ぎて、メッキの接続信頼性において問題となることがある。一方、100μmより大きいと、通常のメッキ加工において、銅箔の貫通孔が封止出来ないとか、メッキが厚くなり過ぎて、パターン精度の低下が発生してしまうと言うことで、問題となることもある。一方、貫通孔の上部の径は、200μmより大きいと、穴径が大きすぎて、高密度化を阻害する結果となる。
【0010】
本発明のデスミア処理は、薬液は、過マンガン酸塩、クローム酸塩等の水溶液で、処理は50〜90℃、1〜15分で行なう。エッチング処理した基板に、該薬液を吹き付ける方法あるいは浸漬する方法で、表面の汚れ或は貫通孔内部の滞留物を分解、溶解、除去する。
レーザー加工において絶縁層の樹脂の分解物は、一部孔より排出されないで内部に溜まったり、排出された分解物が表面の銅箔に付着するため、特に、底面銅箔上に残留している樹脂及び樹脂分解物は、メッキの析出、密着性の阻害要因となり、メッキの接着信頼性の低下をもたらすため、デスミア処理が必要である。
【0011】
本発明のメッキ加工による貫通孔の封止、基板の表裏導通の方法について説明する。
本発明のメッキ加工は、無電解メッキ及び/又は電解メッキの組み合わせで行う。例えば、無電解メッキ、無電解メッキと電解メッキあるいはダイレクトメッキを行う。メッキ加工に用いられる金属は、金、銅、ニッケル、パラジュウム等考えられるが、メッキ加工のやり易さ、基板の性能、後工程の操作のしやすさ、コストのことを考慮すると、銅メッキが好ましい。
最初に無電解メッキを行って、貫通孔の内壁絶縁層部分にも銅を析出させ、表裏の銅箔面の導通を確保する。続いて、電解メッキで銅層を厚くし貫通孔をメッキ金属により完全に封止する。
メッキ時に液の攪拌を十分行う等の操作により、貫通孔の内壁面にも、メッキ金属層を均一に形成すると同時に、表裏及び/又は内層回路と接続する。メッキ厚は、場所によって多少異なるが、孔内で5〜20μmである。
【0012】
無電解メッキは、EDTA浴、ロッシェル塩浴を用いる。
続いて、電解メッキを行って、メッキ金属を厚くして導通信頼性を確保する。電解メッキは、貫通穴の完全な封止、基板の表裏導通を完全に確保する。例えば、電解メッキ液は、硫酸銅或いはピロ燐酸銅を含む電解液である。その液に漬けて、基板に電流を流し、メッキ銅を析出させる。その電解銅メッキ液中での電流密度は、0.3〜1.5A/dmである。エッチング処理により、銅面は粗化されている上、デスミア処理により孔内部の異物がないので、メッキ銅の密着性は非常に高くすることができる。
【0013】
この時、メッキ加工の条件は、対象とする基材によって多少違うが、普通に行われている方法で達成できる。電解メッキの場合、電流密度を上げすぎると、均一性が悪くなったり(メッキ厚のバラツキ増大)、メッキ焼けが発生したりして、後工程の回路形成時に、精度の良いパターンにならないことがある。また、電流密度が低いと生産性が低下し、好ましくない。
【0014】
本発明の封止された底部銅箔の位置に半田接続用端子を形成する方法について説明する。封止された孔の位置に径0.1〜1.0mmの半田接続用端子を形成する。封止された貫通孔の表裏の銅箔がメッキ銅で接続しているので、半田ボールの搭載等の加熱をしても、その面が剥離するあるいは変形するというような問題は起こらない。
【0015】
回路パターン形成後、通常、絶縁性物質でスルーホールの被覆及び/又は充填が行われるが、本発明においても、ソルダーレジストを孔内に埋め込み、パターンの保護膜として塗布した。
【0016】
このようにして形成されたプリント配線板は、半導体を塔載する半導体パッケージ用基板として用いられる。
【0017】
【実施例】
本発明は、公知方法(例えば、C.F.クームズ編、安達芳夫、島田良乙共訳“プリント回路ハンドブック”近代科学社)に準じて実施した。理解を容易にするため、図面で説明する。
本発明に使用した絶縁基材1は、両面に12μmの銅箔2を有する、厚さ0.2mmのガラス布入りBT(ビスマレイミドトリアジン樹脂)両面銅張積層板を使用した【図面1】。特開昭61−99596の方法を参考にして、基板表面を黒化処理して、レーザー穴明機(波長:9.3μmの炭酸ガスレーザー;出力70W;パルス回数5)により底面の片面銅箔のみを残した未貫通穴3を形成する。未貫通穴の断面形状は、テーパー状で底面部の径は35μm、表面部の径は100μmになっていた【図面2】。
レーザー穴明け後の積層板を12%過酸化水素−6%硫酸溶液を(30℃)、スプレー圧:2Kg/mで基板面に吹き付けて、未貫通穴の底面銅箔に貫通孔4が明いているのを確認した。
続いて、2%過マンガン酸カリウム−20%水酸化カリウム水溶液に漬けて、貫通穴内の有機物を分解・溶解・除去した【図面3】。
次に、無電解メッキによりメッキ銅5を析出させ【図面4】(A)、電解メッキによりメッキ銅6を析出させた【図面4】(B)。無電解メッキは、ロッシェル塩浴にて行い、貫通孔の絶縁層内壁及び上下銅層の表面にも厚さ:0.5〜0.8μMの銅を析出させて、上下銅層の導通を行った。続いて、電解メッキ液中に基板を入れて、電流密度:1A/dmにて、貫通孔内にもメッキ処理して銅厚を厚くすると同時に、孔底部の貫通孔を、メッキ銅で封止し、表裏の銅層を接続した。メッキ厚は、場所によって多少異なっていたが、穴の内璧部で10〜12μmになっていた。穴の断面を観察すると、銅メッキされた貫通穴は、完全にメッキ封止され、封止された貫通穴の構造は、底面の銅層が完全にメッキ銅(10〜12μm)で封止された構造7になっていて、接続信頼性において、全く問題がないことが分かった。銅箔2の上の無電解メッキ5と電解メッキ6のメッキ厚は、均一に15〜20μmであった。続いて、銅箔面に回路パターンを形成した 。ソルダーレジストを塗布、穴埋め及びソルダーレジストパターン形成を行いメッキ封止された孔7の位置に半田接続用端子8を有する半導体パッケージ用基板を作製した【図面5】。
温度サイクル試験(−65℃、30分と150℃、30分で500サイクル)により、銅箔のクラックの発生を調べたが、クラックの発生は全く認められなかった。
【0018】
【発明の効果】
表裏パターンの導通を連続したメッキ層で確保することができ、接続信頼性を向上することができ、高密度化に対応することが出来る。
【図面の簡単な説明】
【図1】両面板
【図2】レーザー処理により未貫通穴のある基板
【図3】エッチング処理により貫通孔のある基板
【図4】(A)無電解メッキにより上下銅箔が導通した無電解メッキ銅の基板
(B)電解メッキによりメッキ銅でメッキ封止穴の形成、および、電解メッキで厚化されたメッキ銅の基板
【図5】ソルダーレジストパターンを形成したプリント配線板
【符号の説明】
1 絶縁層
2 銅箔
3 未貫通穴
4 貫通孔
5 無電解メッキ銅
6 電解メッキ銅
7 メッキ封止された孔
8 半田接続用端子
[0001]
The present invention relates to PGA (pin grid array), BGA (ball grid array), CSP (chip size package), MCM (multi-chip module) used in electronic equipment, electrical equipment, computers, communication equipment, and the like. ), A printed circuit board used for FC-BGA (flip chip ball grid array) and the like.
[0002]
[Prior art]
Along with the high integration of semiconductor elements, it is also necessary to increase the density of printed circuit boards for semiconductor packages. In particular, in printed wiring boards used in this field, not only multilayering and thinning of wiring but also miniaturization and high density of through-holes are rapidly progressing. That is, the formation of a through hole by a laser is attempted from the formation of a through hole by a conventionally used drill. The through hole is filled with an insulating resin or the like in order to prevent deterioration of the substrate performance due to intrusion of moisture or the like.
[0003]
[Problems to be solved by the invention]
The filling of the through hole is performed at the time of solder resist coating or before solder resist coating in a separate process. However, there arises a problem that the resin filled in the hole collapses or falls off. Further, even after the semiconductor package is formed, since the hole-filling resin transmits moisture, it causes peeling between the substrate and the mold resin, so-called popcorn phenomenon. As a countermeasure against this, in a method of forming a through hole with a laser and then closing the through portion with plating, that is, sealing (hereinafter referred to as sealing the through hole with plating), a resin hole and a copper foil hole Due to the variation in the hole diameter and the variation in the shape of the copper foil holes, it is difficult to uniformly plate and seal all the holes in the substrate of 50 to 2000.
[0004]
[Means for Solving the Problems]
In the laser hole processing on the double-sided board, after forming the non-through hole leaving only the single-sided copper foil, the through hole is formed by etching, and the hole is sealed with plating to ensure conduction, and the sealed hole This is a method for manufacturing a semiconductor package substrate in which solder ball connection terminals are formed at the positions.
The present invention is a double-sided copper-clad laminate,
(1) Form a non-through hole that leaves only one-sided copper foil by laser processing (2) Form a through-hole in one-sided copper foil by etching treatment (3) Desmear treatment (4) Seal the through-hole by plating (5) A method of manufacturing a semiconductor package substrate by forming solder connection terminals at positions of sealed holes.
This invention is a manufacturing method of the board | substrate for semiconductor packages by a double-sided copper clad laminated board being board thickness 0.04-0.4mm and each copper foil thickness 5-20 micrometers of front and back.
The present invention is a method for manufacturing a substrate for a semiconductor package, wherein the laser processing is performed using a carbon dioxide laser, and the hole diameter is 70 to 120 μm.
This invention is a manufacturing method of the board | substrate for semiconductor packages by the through-hole diameter by an etching process being 10-100 micrometers.
The present invention is a method for manufacturing a substrate for a semiconductor package, in which an etching treatment is performed using an aqueous solution containing hydrogen peroxide or persulfate.
The present invention is a method for manufacturing a substrate for a semiconductor package, in which desmear treatment is performed using potassium permanganate or potassium chromate aqueous solution.
The present invention is a method for manufacturing a substrate for a semiconductor package, wherein sealing of a through hole by plating is performed by electroless plating and / or electrolytic plating.
The present invention is a method for manufacturing a substrate for a semiconductor package by performing electrolytic plating in an electrolytic copper plating solution at a current density of 0.3 to 1.5 A / dm 2 .
[0005]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a non-through hole is formed in a double-sided copper-clad laminate by laser processing, and a through hole is formed by etching. After the desmear process, the circuit on the front and back of the substrate is made conductive by plating, and at the same time, the through hole is sealed. This is a method of manufacturing a printed circuit board by forming solder connection terminals at the positions of the copper foils in the plated and sealed holes (hereinafter referred to as the positions of the sealed copper foils).
[0006]
The insulating substrate used in the present invention is an epoxy resin, a bismaleimide triazine resin (BT resin), a polyimide resin, a PPO resin, or the like, or a prepreg in which these resins are impregnated with glass fiber, glass cloth, or paper. The copper foil used in the present invention is an electrolytic copper foil having a thickness of 5 to 20 μm, preferably 9 to 15 μm. A copper foil is placed on the prepreg and press-molded to form a double-sided copper clad laminate having an insulating layer thickness of 0.04 to 0.4 mm.
[0007]
The laser processing of the present invention will be described in detail.
The shape of the hole formed in the present invention is such that the surface of the copper foil and the insulating layer are formed by a laser, and the irradiation energy and the number of pulses are set so that the copper foil on the bottom surface is a non-through hole. Control the beam diameter. The laser used in the present invention is performed using a carbon dioxide laser drilling machine having a wavelength of 9 to 11 μm. Beam diameter: 50 to 150 μm; output × number of shots: (20 to 40 mJ) × (1 to 2 shot) + (10 to 20 mJ) × (1 to 4 shot). The hole diameter of the surface copper foil is the average hole diameter: A non-through hole of 90 to 100 μm is formed. If the hole diameter variation width on the surface of the hole formed in the present invention is a minimum of 70 to 120 μm and the hole diameter of the bottom of the insulating layer is 30 to 100 μm, it is a hole having a preferable shape for carrying out the present invention. is there.
[0008]
The formation of the through hole in the copper foil by the etching process of the present invention will be described.
The chemical solution for the etching treatment of the present invention is an aqueous solution of persulfate, hydrogen peroxide-sulfuric acid or the like. A hole is made in the bottom copper foil by dipping the laser processed substrate in the chemical solution or spraying the chemical solution. Furthermore, the copper surface that has come into contact with the chemical solution by the etching process is roughened. The roughened copper surface has the effect of improving the adhesion of the plated copper in the subsequent process.
The
[0009]
The copper foil on the surface melts and evaporates by laser irradiation, and the resin of the insulating layer decomposes and evaporates and is discharged, but part of it stays inside the generated through-hole, while the copper foil at the bottom of the hole The hole has not been opened by the heat, but it has been altered by heat, so in the etching process, it reacts with the remaining copper and the altered copper foil without being discharged, dissolves, and opens the pores in the copper foil at the bottom of the hole There is. However, in the etching process of the present invention, if the diameter of the hole bottom is smaller than 30 μm, it sometimes happens that the through hole cannot be formed in the etching process. Even if the hole is formed, it is difficult to continuously supply the plating component to the through-hole portion even if the plating solution is stirred or vibrated in the plating process, particularly in the electroless plating process. For this reason, sealing by plating may not be possible. Even if sealing can be achieved by plating, the thickness of the plating layer that connects the circuit patterns on the front and back of the substrate becomes too small, which may cause problems in connection reliability of plating. On the other hand, if the thickness is larger than 100 μm, in normal plating processing, the copper foil through-holes cannot be sealed or the plating becomes too thick, resulting in a decrease in pattern accuracy. There is also. On the other hand, if the diameter of the upper part of the through hole is larger than 200 μm, the hole diameter is too large, which results in inhibiting high density.
[0010]
In the desmear treatment of the present invention, the chemical solution is an aqueous solution such as permanganate or chromate, and the treatment is performed at 50 to 90 ° C. for 1 to 15 minutes. By using a method of spraying or immersing the chemical solution on the etched substrate, the dirt on the surface or the accumulated matter inside the through-hole is decomposed, dissolved and removed.
In the laser processing, the resin decomposition product of the insulating layer is not discharged from the holes, but remains inside, or the discharged decomposition product adheres to the copper foil on the surface, so it remains particularly on the bottom copper foil. Resin and resin decomposition products are factors that hinder the deposition and adhesion of plating, and cause a decrease in the adhesion reliability of plating. Therefore, desmear treatment is necessary.
[0011]
A method for sealing a through hole and conducting the front and back of the substrate by plating according to the present invention will be described.
The plating process of the present invention is performed by a combination of electroless plating and / or electrolytic plating. For example, electroless plating, electroless plating and electrolytic plating or direct plating is performed. Gold, copper, nickel, palladium, etc. can be considered as the metal used for plating, but considering the ease of plating, the performance of the board, the ease of operation in the subsequent process, and the cost, copper plating is preferable.
First, electroless plating is performed to deposit copper on the inner wall insulating layer portion of the through hole to ensure conduction between the front and back copper foil surfaces. Subsequently, the copper layer is thickened by electrolytic plating, and the through hole is completely sealed with the plating metal.
A plating metal layer is uniformly formed on the inner wall surface of the through hole by an operation such as sufficiently stirring the solution during plating, and at the same time, connected to the front and back and / or the inner layer circuit. The plating thickness varies somewhat depending on the location, but is 5 to 20 μm in the hole.
[0012]
For electroless plating, an EDTA bath or a Rochelle salt bath is used.
Subsequently, electrolytic plating is performed to increase the thickness of the plated metal to ensure conduction reliability. Electrolytic plating ensures complete sealing of the through-holes and complete conduction of the substrate. For example, the electrolytic plating solution is an electrolytic solution containing copper sulfate or copper pyrophosphate. Immerse it in the solution and pass an electric current through the substrate to deposit plated copper. Current density at the electrolytic copper plating solution is 0.3~1.5A / dm 2. Since the copper surface is roughened by the etching process, and there is no foreign matter inside the hole by the desmear process, the adhesion of the plated copper can be made extremely high.
[0013]
At this time, the conditions of the plating process are somewhat different depending on the target substrate, but can be achieved by a commonly used method. In the case of electrolytic plating, if the current density is increased too much, the uniformity may deteriorate (increase in plating thickness variation), or plating burn may occur, and a precise pattern may not be obtained when forming a circuit in a subsequent process. is there. Moreover, when the current density is low, productivity is lowered, which is not preferable.
[0014]
A method for forming a solder connection terminal at the position of the sealed bottom copper foil of the present invention will be described. A solder connection terminal having a diameter of 0.1 to 1.0 mm is formed at the position of the sealed hole. Since the copper foils on the front and back sides of the sealed through-hole are connected by plated copper, there is no problem that the surface peels or deforms even when heating such as mounting of solder balls is performed.
[0015]
After the circuit pattern is formed, the through hole is usually covered and / or filled with an insulating material. In the present invention, a solder resist is buried in the hole and applied as a protective film for the pattern.
[0016]
The printed wiring board thus formed is used as a semiconductor package substrate on which a semiconductor is mounted.
[0017]
【Example】
The present invention was carried out according to a known method (for example, edited by CF Combs, Yoshio Adachi, Yoshito Shimada "Printed Circuit Handbook", Modern Science Co., Ltd.). For ease of understanding, description will be made with reference to the drawings.
As the insulating base material 1 used in the present invention, a BT (bismaleimide triazine resin) double-sided copper clad laminate with a glass cloth having a thickness of 0.2 mm having a copper foil 2 of 12 μm on both sides was used. With reference to the method of JP-A-61-99596, the substrate surface is blackened, and a single-sided copper foil on the bottom surface is obtained by a laser drilling machine (wavelength: 9.3 μm carbon dioxide laser; output 70 W; number of pulses 5). The non-through hole 3 is formed with only the remaining. The cross-sectional shape of the non-through hole was a tapered shape, the diameter of the bottom surface portion was 35 μm, and the diameter of the surface portion was 100 μm [Drawing 2].
The laminated plate after laser drilling is sprayed with a 12% hydrogen peroxide-6% sulfuric acid solution (30 ° C.) on the substrate surface at a spray pressure of 2 kg / m 2 , and the through hole 4 is formed on the bottom copper foil of the non-through hole. I confirmed it was bright.
Subsequently, it was immersed in a 2% potassium permanganate-20% potassium hydroxide aqueous solution to decompose, dissolve and remove organic substances in the through holes [Drawing 3].
Next, plated copper 5 was deposited by electroless plating [Drawing 4] (A), and plated copper 6 was deposited by electrolytic plating [Drawing 4] (B). Electroless plating is performed in a Rochelle salt bath, and copper of thickness 0.5 to 0.8 μM is deposited on the inner wall of the insulating layer of the through hole and the surface of the upper and lower copper layers to conduct the upper and lower copper layers. It was. Subsequently, the substrate is put in an electrolytic plating solution, and the through hole is plated at a current density of 1 A / dm 2 to increase the copper thickness. At the same time, the through hole at the bottom of the hole is sealed with plated copper. The copper layers on the front and back sides were connected. The plating thickness was slightly different depending on the location, but was 10 to 12 μm at the inner wall of the hole. When observing the cross section of the hole, the copper plated through hole is completely plated and sealed, and the structure of the sealed through hole is that the bottom copper layer is completely sealed with plated copper (10 to 12 μm). It was found that there was no problem in connection reliability. The plating thicknesses of the electroless plating 5 and the electrolytic plating 6 on the copper foil 2 were uniformly 15 to 20 μm. Subsequently, a circuit pattern was formed on the copper foil surface . A semiconductor package substrate having a solder connection terminal 8 at the position of the plated hole 7 was prepared by applying a solder resist, filling a hole, and forming a solder resist pattern [Drawing 5].
The occurrence of cracks in the copper foil was examined by a temperature cycle test (500 cycles at −65 ° C., 30 minutes and 150 ° C., 30 minutes), but no cracks were observed.
[0018]
【The invention's effect】
Conductivity between the front and back patterns can be ensured by a continuous plating layer, connection reliability can be improved, and high density can be accommodated.
[Brief description of the drawings]
[FIG. 1] Double-sided board [FIG. 2] Substrate with non-through holes by laser treatment [FIG. 3] Substrate with through-holes by etching treatment [FIG. 4] (A) Electroless with upper and lower copper foils conductive by electroless plating Plated copper substrate (B) Formation of plating sealing hole with plated copper by electrolytic plating, and plated copper substrate thickened by electrolytic plating
[Fig.5] Printed wiring board with solder resist pattern [Description of symbols]
1 Insulating layer 2 Copper foil 3 Non-through hole 4 Through hole 5 Electroless plated copper 6 Electroplated copper 7 Plated and sealed hole 8 Solder connection terminal

Claims (7)

両面銅張積層板において、
(1) レーザー加工により片面銅箔のみを残した未貫通穴を形成する
(2) エッチング処理により未貫通孔の底部の銅箔に貫通孔を形成する
(3) デスミヤ処理をする
(4) 無電解メッキを行って表裏の銅箔面の導通を確保し、続いて電解メッキで銅層を厚くし貫通孔をメッキ金属により封止する
(5) 封止された孔の位置に半田接続用端子を形成する
ことを特徴とする半導体パッケージ用基板の製造方法
In double-sided copper-clad laminates,
(1) Form a non-through hole that leaves only one-sided copper foil by laser processing (2) Form a through hole in the copper foil at the bottom of the non-through hole by etching (3) Perform desmear treatment (4) None to ensure continuity of the copper foil surface of the front and back by performing electrolytic plating, followed by thickening the copper layer by electrolytic plating to seal the through hole by plating metal (5) solder connection terminal to the position of the sealed hole For manufacturing a semiconductor package substrate characterized by comprising:
両面銅張り積層板が、絶縁層厚0.04〜0.4mm、表裏の各銅箔厚5〜20μmであることを特徴とする請求項1の半導体パッケージ用基板の製造方法  2. The method for manufacturing a substrate for a semiconductor package according to claim 1, wherein the double-sided copper-clad laminate has an insulating layer thickness of 0.04 to 0.4 mm and a thickness of each of the front and back copper foils of 5 to 20 [mu] m. レーザー加工が、炭酸ガスレーザーによるもので、穴径が70〜120μmであることを特徴とする請求項1の半導体パッケージ用基板の製造方法  2. The method of manufacturing a substrate for a semiconductor package according to claim 1, wherein the laser processing is performed by a carbon dioxide laser, and the hole diameter is 70 to 120 [mu] m. エッチング処理により形成された片面銅箔における貫通孔径が10〜100μmであることを特徴とする請求項1の半導体パッケージ用基板の製造方法  2. The method of manufacturing a substrate for a semiconductor package according to claim 1, wherein the through-hole diameter in the single-sided copper foil formed by the etching process is 10 to 100 [mu] m. エッチング処理が過酸化水素又は過硫酸塩を含有する水溶液によることを特徴とする請求項4の半導体パッケージ用基板の製造法5. The method of manufacturing a substrate for a semiconductor package according to claim 4, wherein the etching treatment is performed with an aqueous solution containing hydrogen peroxide or persulfate. デスミヤ処理が過マンガン酸カリウム又はクロム酸カリウム水溶液によることを特徴とする請求項1の半導体パッケージ用基板の製造法2. The method of manufacturing a substrate for a semiconductor package according to claim 1, wherein the desmear treatment is performed with an aqueous potassium permanganate or potassium chromate solution. 電解メッキが電解銅メッキ液中で電流密度が0.3〜1.5A/dmで行うことを特徴とする請求項半導体パッケージ用基板の製造方法 2. The method for manufacturing a substrate for a semiconductor package according to claim 1 , wherein the electrolytic plating is performed in an electrolytic copper plating solution at a current density of 0.3 to 1.5 A / dm2.
JP34658599A 1999-11-01 1999-11-01 Manufacturing method of substrate for semiconductor package Expired - Fee Related JP4129666B2 (en)

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CN100369223C (en) * 2005-05-27 2008-02-13 江苏长电科技股份有限公司 Plane button type packing technology of integrated circuit or discrete component and its packing structure
CN100359655C (en) * 2005-05-27 2008-01-02 江苏长电科技股份有限公司 Planar salient point type technique for packaging intergrate circuit or discrete component
JP2007227648A (en) * 2006-02-23 2007-09-06 Sharp Corp Printed wiring board, and method for manufacturing printed wiring board
JP5330474B2 (en) 2011-09-22 2013-10-30 上村工業株式会社 Desmear liquid and desmear treatment method
WO2013160994A1 (en) * 2012-04-24 2013-10-31 三共化成株式会社 Plated structure of through-hole
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