JP2004186354A - Method of manufacturing multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board which can closely pack wiring. <P>SOLUTION: The method of manufacturing a multilayer wiring board has a process comprising the steps of forming insulator layers 2 on wiring layers 3 on the wiring board 1 in which the wiring layers 3 formed on both surfaces of the insulator layers 2 are connected with bumps 4, forming holes 6 for exposing positions which are connected with the bumps 4 by irradiating a laser beam, forming vias 6a by plating therein, forming plating layers 9 which are filled in the vias 6a by plating the vias 6a, and etching it to form first wiring patterns 10; and separately a process comprising the steps of laminating the insulator layer 2 on a conductive support 5 having the bumps 4 thereon and pressurizing it so that the bumps 4 are penetrated through the insulator layer 2 and the tips of the bumps 4 are exposed from the insulator layer 2, laminating the tips 4a of the bumps 4 on the first wiring patterns 10 so that the tips 4a are compressed to the recessed parts of the plating layers 9 on the vias 6a, and etching it to form second wiring patterns 12. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer wiring board capable of fine wiring.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a multilayer wiring board in which a conductor layer is arranged between a plurality of laminated insulator layers and on the surface of the outermost layer, vias (interlayer connection portions) are provided in the insulator layer and the insulator layer is used. A method of connecting a plurality of separated conductor layers between layers has been adopted (for example, see Patent Document 1). For example, a laser via formed by forming a hole in an insulator layer by a laser and forming a plating layer on the inner wall surface of the hole is used as an interlayer connector. As another method for interlayer connection, instead of forming a via, a bump such as a silver paste is formed by printing on a sheet-like conductive support such as a copper foil, and a prepreg or the like is formed on the bump. A method has also been proposed in which the insulator layer is placed, the tip of the bump is penetrated through the insulator layer to be exposed, and the tip of the bump is press-bonded to the conductor layer for interlayer connection.
[0003]
On the other hand, as electronic devices such as mobile phones have become smaller and faster, there is a demand for high-density mounting and high-density wiring of multilayer wiring boards. In order to reduce the substrate area and to finely arrange wirings, it is necessary to stack vias or bumps at the same position (via-on-via). Therefore, conventionally, a multilayer wiring board in which bumps are vertically stacked at the same position has been manufactured. When mounting a semiconductor package called BGA (Ball Grid Array) or CSP (Chip Size / Scale Package) on such a multilayer wiring board, it is required to reduce the land diameter of the bump.
[0004]
However, when only the bumps are stacked, there is a problem that the land diameter of the bumps cannot be reduced. This is because the bumps are made of paste, and it is difficult to penetrate through an insulator layer such as a prepreg unless the bumps have a certain size. Further, when a laser via is laminated on the bump, for example, when filling the laser via with plating (via fill), it is difficult to flatten the surface of the via, and the bump is raised or dented. Therefore, there is a problem that the lamination with high connection reliability cannot be performed well.
[0005]
[Patent Document 1]
JP-A-2000-340953 (pages 4-5, FIG. 1-7)
[0006]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION In view of such a background, an object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of miniaturizing wiring.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of a method for manufacturing a multilayer wiring board according to the present invention is directed to a method for manufacturing a multilayer wiring board, wherein two wiring layers formed on both surfaces of the first insulating layer penetrate the first insulating layer. Forming a second insulating layer made of a synthetic resin on at least one wiring layer of the wiring substrate connected by the first bump to be formed, and applying a laser beam to the surface of the second insulating layer. Irradiating to form a hole that exposes a position of the wiring layer connected to the first bump; plating the second insulator layer and the hole to form the hole; Forming a first conductor layer by plating on the second insulator layer, and forming a via connecting the first conductor layer and the wiring layer by plating on the hole; Forming a plated layer filling the via by plating the via, and etching the first conductive layer. A first etching step of forming a predetermined first wiring pattern by applying a coating, and a third insulating layer made of a synthetic resin on a sheet-like conductive support having a second bump formed at a predetermined position separately. By stacking and pressing the body layers, the second bumps are made to penetrate the third insulator layer, and the tips of the second bumps are exposed from the third insulator layer to form a sheet-shaped conductive layer. A laminate forming step of forming a laminate of the support and the third insulator layer, and the tip of the second bump formed in the laminate forming step is placed on the via remaining in the first etching step. Bonding the third insulating layer and the sheet-shaped conductive support on the first wiring pattern formed in the first etching step by pressing the surface of the plating layer on the first wiring pattern; The sheet-shaped conductive support is etched to provide a predetermined second wiring pattern. A second etching step of forming a connection, wherein the first bump, the via, the plating layer, and the second bump are vertically stacked to form an interlayer connection. I do.
[0008]
According to the first aspect of the manufacturing method of the present invention, an insulator layer is formed on one of the wiring layers of the wiring board having the first bump built therein, and the surface is irradiated with a laser beam to form a second insulating layer. A hole is formed on one of the bumps, the surface thereof is plated, and a via formed by plating on the hole is filled with plating to form a plating layer. Then, the first conductor layer is etched in a first etching step to form a first wiring pattern. On the other hand, a third insulator layer is stacked on the sheet-like conductive support on which the second bump is formed in a stacked body forming step, and the tip of the second bump is moved to the third conductive layer. A laminate of the sheet-shaped conductive support and the third insulator layer is formed so as to be exposed from the insulator layer. Then, a sheet-shaped conductive support is laminated on the first wiring pattern such that the tip of the second bump is pressed against the surface of the plating layer after the first etching step. Further, in a second etching step, the sheet-shaped conductive support is etched to form a second wiring pattern.
[0009]
Therefore, the land diameter of the via formed on the first bump can be formed smaller than the land diameter of the first bump. Further, the surface of the plating layer formed when the via is filled with plating is not smoothed but dented. However, the tip of the second bump formed in the laminated body forming step is pressed against the plating layer, and the tip of the second bump is crushed and filled in the recess on the surface of the plating layer, so that the second bump and the plating The layers adhere. Therefore, the depression on the surface of the plating layer is eliminated by the tip of the second bump, and the interlayer connection is improved. Furthermore, since the first bump, the via, the plating layer, and the second bump are vertically stacked, a multilayer wiring board capable of fine wiring can be manufactured.
[0010]
In a second aspect of the method for manufacturing a multilayer wiring board according to the present invention, a step of forming a fourth insulating layer made of a synthetic resin on the second wiring pattern formed in the second etching step is provided. Irradiating the surface of the fourth insulator layer with a laser beam to form a second hole exposing a position of the second wiring pattern connected to the second bump; Plating on the fourth insulator layer and the second hole to form a second conductor layer by plating on the fourth insulator layer; Forming a second via connecting the second conductor layer and the second wiring pattern by plating on the hole; and plating the second via to form the second via. Forming a second plating layer filling the via, and etching the second conductor layer to form a predetermined third wiring pattern; And a third etching step of forming, the second vias and forming an interlayer connection stacked vertically on top of the second bump.
[0011]
According to the second aspect of the manufacturing method of the present invention, the four-layer substrate formed in the first aspect, that is, the wiring layer, the wiring layer via the first bump, and the fourth layer via the via from below. A fourth insulator layer is formed on a substrate including the first wiring pattern and the second wiring pattern via the second bump. Then, the surface is irradiated with a laser beam to form a second hole on the second bump, the surface is plated, and the second hole formed by plating applied to the second hole is formed. Are filled with plating to form a second plating layer. Then, etching is performed in a third etching step to form a third wiring pattern. Therefore, a laser via is formed in the outermost layer of the five-layer wiring board. The land diameter of the laser via can be formed smaller than the land diameters of the first and second bumps. Therefore, for example, it is possible to mount a CSP having a small pitch.
[0012]
According to a third aspect of the method for manufacturing a multilayer wiring board of the present invention, in addition to the steps of the second aspect, the tip of the second bump formed in the laminated body forming step is further removed by the third step. Press-fit onto the surface of the second plating layer on the second via formed in the third etching step, and place the third insulator layer on the third wiring pattern formed in the third etching step. And a laminating step of laminating the sheet-like conductive support and a fourth etching step of etching the sheet-like conductive support laminated in the laminating step to form a predetermined fourth wiring pattern. And an interlayer connection in which the second bumps stacked in the stacking step are vertically stacked on the second plating layer filled in the second via.
[0013]
According to the third aspect of the manufacturing method of the present invention, a third insulator layer is laminated and added on the sheet-like conductive support on which the second bump is formed by a separate laminate forming step. By pressing, the tip of the second bump is exposed from the third insulator layer to form a laminate of the conductor layer and the third insulator layer. Then, the five-layer substrate formed in the second mode, that is, from the bottom, the wiring layer, the wiring layer via the first bump, the first wiring pattern via the via, and the first wiring pattern via the second bump On the substrate including the second wiring pattern and the third wiring pattern via the second via, a laminate of the above-described conductor layer and third insulator layer is provided. At this time, the tip of the second bump of the laminate is pressed against the surface of the second plating layer of the second via of the five-layer substrate. Then, in a fourth etching step, the outermost sheet-shaped conductive support is etched to form a fourth wiring pattern. Therefore, in the six-layer wiring board, since the lands of the laser vias are formed in the second and fourth layers from the top, the wiring density can be increased as compared with the case where only the bumps are stacked.
[0014]
Further, the first to third aspects of the method for manufacturing a multilayer wiring board according to the present invention further include the same configuration as that of the method for manufacturing a multilayer wiring board on one wiring layer on the other wiring layer of the wiring board. It is preferable to include a step of forming According to the present invention, a six-layer wiring board capable of forming an interlayer connection in which vias and bumps stacked on the other wiring layer and the first bumps are stacked vertically to enable fine wiring, An eight-layer wiring board and a ten-layer wiring board can be realized.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment) Next, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is an explanatory cross-sectional view showing one configuration example of a core substrate used in the manufacturing method according to the first embodiment of the present invention, and FIG. 2 is an explanatory cross-sectional view showing a manufacturing method of the core substrate. FIGS. 3 to 10 are explanatory sectional views showing the steps of manufacturing the multilayer wiring board of the first embodiment.
[0016]
First, a core substrate used for the multilayer wiring board of the first embodiment will be described with reference to FIG. This core substrate corresponds to the wiring substrate of the present invention. In the core substrate 1 shown in FIG. 1, wiring layers 3 are provided on both front and back surfaces of an insulator layer 2 (synthetic resin sheet 2) made of a synthetic resin sheet such as a prepreg, and the wiring layers 3 and 3 are connected by bumps 4. It is configured. The synthetic resin sheet 2 and the bumps 4 sandwiched between the wiring layers 3 and 3 correspond to the first insulator layer and the first bumps of the present invention, respectively.
[0017]
The core substrate 1 can be manufactured as follows. First, as shown in FIG. 2A, a plurality of bumps 4 are formed at predetermined positions on a conductive support 5 such as a 18-μm-thick copper foil. The bumps 4 are formed by laminating a metal mask having a through hole at a predetermined position on the conductive support 5, screen-printing a conductive paste such as a silver paste on the metal mask, and drying. You.
[0018]
Next, as shown in FIG. 2B, a synthetic resin sheet 2 such as a prepreg is laminated on the conductive support 5 on which the bumps 4 are formed, and the bumps 4 are formed on the synthetic resin sheet 2 by pressing. The end is exposed from the synthetic resin sheet 2. The synthetic resin sheet 2 has a thickness of, for example, 60 μm, and the bump 4 penetrates the synthetic resin sheet 2. Is formed to have a size of 0.1 mm.
[0019]
Next, as shown in FIG. 2C, the conductive support 5 having the synthetic resin sheet 2 laminated on the conductive support 5 such as a separately prepared copper foil is used. The layers are laminated with the surface exposed from the sheet 2 made of paper downward, and pressure-bonded. Next, as shown in FIG. 2D, the conductive support 5 is etched to form the wiring layer 2, and the core substrate 1 shown in FIG. 1 is obtained. FIG. 1 is an enlarged view of a main part of the core substrate 1 of FIG.
[0020]
Next, a method for manufacturing the multilayer wiring board of the present embodiment using the core substrate 1 will be described with reference to FIGS.
[0021]
First, as shown in FIG. 3, an insulator layer 2 made of a synthetic resin sheet such as a prepreg is formed on both front and back surfaces of a core substrate 1. Note that the formed insulator layer 2 corresponds to the second insulator layer of the present invention. Then, the insulator layer 2 on the wiring layer 3 of the core substrate 1 is irradiated with a laser beam to form a hole 6 on the bump 4 as shown in FIG. The hole 6 is formed, for example, so that the diameter of the opening is 0.1 mm.
[0022]
Next, as shown in FIG. 5, the surface of the insulator layer 2 laminated on the core substrate 1 is plated to form a conductor layer 7 having a thickness of, for example, 18 μm (the first conductor layer of the present invention). Is formed). The plating is also applied to the hole 6 at the same time, and a via 6 a connecting the conductor layer 7 and the wiring layer 3 is formed in the hole 6.
[0023]
The plating is performed by cleaning the surface of the insulator layer 2, removing burrs when the hole 6 is formed, polishing the inside of the hole 6 with an abrasive, and washing with water. Processing, electroless plating, and electrolytic plating are performed in this order.
[0024]
The desmear process is a process of removing the smear formed by the solidification of the resin chips melted by the heat generated when the hole 6 is formed on the inner wall of the hole 6. In the desmear treatment, the core substrate 1 on which the insulator layer 2 and the hole 6 are formed is immersed in a swelling solution, washed with hot water, and dissolved in a potassium permanganate solution or a sodium permanganate solution to remove the smear. I do. Then, after neutralization with sulfuric acid and washing with water, attached manganese dioxide is removed.
[0025]
In the pretreatment following the desmear treatment, the surfaces of the insulator layer 2 and the holes 6 are degreased and cleaned with a degreasing agent, washed with hot water, and then with a soft etching agent (a mixed solution of a hydrogen peroxide solution and a copper sulfate solution, or (A cupric solution) to remove the oxide film on the surface of the insulator layer 2 and the hole 6. Next, the residue (smut) of the soft etching agent is removed by pre-dip. Then, the substrate is treated with a palladium compound solution, and a palladium compound for generating nuclei for electroless plating is attached.
[0026]
In the electroless plating subsequent to the pretreatment, the palladium compound is first reduced by a reducing agent to generate palladium which is a core of the electroless plating. Next, after the reducing agent is washed with water and removed, the core substrate 1 on which the insulator layer 2 and the holes 6 are formed is immersed in an electroless plating bath. The electroless plating bath comprises copper sulfate, formalin, sodium hydroxide, a chelating agent, and a surfactant, and reduces copper sulfate with formalin to precipitate copper. As a result, a copper plating layer is formed on the surfaces of the insulator layer 2 and the hole 6. The core substrate 1 on which the copper plating layer is formed is washed with water to remove residues of the electroless plating bath.
[0027]
The electrolytic plating subsequent to the electroless plating is performed for thickening the copper plating layer. The electrolytic plating is performed by immersing the core substrate 1 on which the copper plating layer is formed in an electrolytic plating bath, and applying a current between both electrodes using the copper plating layer as a cathode and an electrode plate made of phosphorous copper as an anode. As the electroplating bath, a bath containing copper sulfate, sulfuric acid, chlorine ions, and additives is used. The conductor layer 7 and the via 6a are formed by the electrolytic plating. The multilayer wiring board 8 on which the conductor layer 7 and the via 6a are formed is washed with water to remove residues of the electrolytic plating bath.
[0028]
Next, as shown in FIG. 6, the plated layer 9 is formed by plating the via 6a of the multilayer wiring board 8 on which the conductor layer 7 and the via 6a are formed as described above. As a result, a recess 9a is formed in the opening of the via 6a, as indicated by a virtual line in FIG. At this time, by selecting the component ratio of the material constituting the electrolytic plating bath and the setting of the current value, the plating filling the via 6a occupies 50% or more of the volume in the via 6a. When performing the step of pressing the tip of the bump 4 on the surface of the plating layer 9 (see FIG. 8), excellent connection reliability between the plating layer 9 and the bump 4 can be obtained.
[0029]
Next, by etching the conductor layer 7, a multilayer wiring board 11 having a wiring pattern 10 (corresponding to a first wiring pattern of the present invention) is obtained as shown in FIG. This step corresponds to the first etching step of the present invention. The etching can be performed, for example, as follows.
[0030]
First, a photosensitive film (dry film) serving as an etching resist film is attached to cover a necessary portion of the conductor layer 7 as the wiring pattern 10 and close an opening of the via 6a (the surface of the plating layer 9). . Next, exposure and development are performed using an exposure film, and an etching resist film is left only in a portion necessary for the wiring pattern 10 and an opening of the via 6a. Then, when the etchant is sprayed, the portion of the conductor layer 7 not covered with the etching resist film is dissolved and removed, and the wiring pattern 10 is formed. At this time, since the surface of the plating layer 9 is covered with the etching resist film, it can be left as it is without being dissolved and removed by the etching solution.
[0031]
In the multilayer wiring board 11 shown in FIG. 7, the land diameter connected to the via 6a can be made smaller than the land diameter connected to the bump 4 in the wiring layer 3, and the wiring pattern 10 can be made denser. Further, the multilayer wiring board 11 has a four-layer configuration in which the wiring layer 10 is connected to the wiring layer 3 of the core substrate 1 via the via 6a, and the wiring pattern 10 is superior to the wiring layer 3. Connection reliability can be obtained.
[0032]
Next, as shown in FIG. 2 (b), apart from the multilayer wiring board 11, a sheet 2 made of a synthetic resin similar to that manufactured in the step of manufacturing the core substrate 1 (third sheet of the present invention) A conductive support 5 (corresponding to the laminate of the present invention) is provided in which the bumps 4 (corresponding to the second bump of the present invention) are laminated and the tips of the bumps 4 are exposed. Here, the step shown in FIG. 2B corresponds to the laminate forming step of the present invention.
[0033]
Then, as shown in FIG. 8, a wiring pattern 10 is formed on the conductive support 5 on which the synthetic resin sheet 2 is laminated so that the tip of the bump 4 is disposed on the surface of the plating layer 9. It is pressure-bonded to both sides of the multilayer wiring board 11. Then, the multilayer wiring board 11 in which the conductive support 5 on which the synthetic resin sheet 2 is laminated is pressure-bonded on both sides is mounted on a multilayer press, and heated and pressed in a vacuum, as shown in FIG. Integrate. At this time, the surface of the plating layer 9, which is the outermost layer of the multilayer wiring board 11, is concave, but when the bump 4 penetrating the synthetic resin sheet 2 is pressed against the plating layer 9, the tip 4a of the bump 4 (FIG. 9 is crushed and filled in the depressions on the surface of the plating layer 9 so that the bumps 4 and the plating layer 9 adhere to each other, and the depressions on the surface of the plating layer 9 are eliminated by the bumps 4a.
[0034]
Next, a photosensitive film serving as an etching resist film is adhered to the conductive support 5 integrated with the multilayer wiring board 11 via the synthetic resin sheet 2, and a conductive pattern necessary for the conductive support 5 is formed. Etching is performed so as to leave a portion. This step corresponds to the second etching step of the present invention, and can be performed by a method similar to the first etching step. As a result, as shown in FIG. 10, a multilayer wiring board 13 including the wiring pattern 12 (corresponding to the second wiring pattern of the present invention) is obtained.
[0035]
The multilayer wiring board 13 has a six-layer structure in which the wiring pattern 12 is connected to the wiring pattern 10 via the bump 4 and the wiring pattern 10 is connected to the wiring layer 3 of the core substrate 1 via the via 6a. I have. The wiring pattern 12 is composed of a conductive support 5 on which the bumps 4 are provided. When the bumps 4 are pressed against the plating layer 9, the tips 4 a of the bumps 4 are crushed and the surface of the plating layer 9 is crushed. Since the recesses are filled and the bumps 4 and the plating layer 9 are in close contact with each other, excellent connection reliability with the wiring pattern 10 via the plating layer 9 can be obtained.
[0036]
According to the above embodiment, the bumps and the vias can be alternately and substantially vertically stacked between the wiring layers by crimping the tips of the bumps at the locations where the vias are filled with the plating layer. Can be enhanced. The outermost wiring pattern 12 is preferably coated with an insulating ink to form a resist having a thickness of, for example, 20 μm for heat-resistant coating and protection from the external environment.
[0037]
(Second Embodiment) The method for manufacturing a multilayer wiring board of the present invention is not limited to the first embodiment. For example, as shown in FIG. 11, the multilayer wiring board 13 of the first embodiment is formed in the same manner as the process up to forming the wiring pattern 10 of the first embodiment. The synthetic resin sheet 2 (corresponding to the fourth insulator layer of the present invention) is formed on both sides, and the hole 6 (corresponding to the second hole of the present invention) is formed by irradiating a laser beam. The via 6a and the plating layer 9 are formed by plating. Then, the wiring pattern 14 (corresponding to a third wiring pattern of the present invention) is etched from above by etching (corresponding to a third etching step of the present invention) while leaving the plating layer 9 and necessary portions (corresponding to a third etching step of the present invention). May be formed. In this case, a multilayer wiring board 15 having an eight-layer structure is manufactured, and the land diameter of the outermost layer is smaller than the land diameter of the bump 4, so that a CSP or the like having a small pitch can be mounted.
[0038]
(Third Embodiment) As shown in FIG. 12, the process up to forming the wiring pattern 12 in the first embodiment is completely different from the eight-layered multilayer wiring board 15 of the second embodiment. The conductive support 5 integrated with the synthetic resin sheet 2 (corresponding to the third insulator layer of the present invention) is laminated on both surfaces of the multilayer wiring board 15 by the same method (this step). Corresponds to the laminating step of the present invention). Then, the conductive support 5 may be etched to form a wiring pattern 16 (corresponding to a fourth etching step of the present invention) (corresponding to a fourth wiring pattern of the present invention). In this case, a multilayer wiring board 17 having a ten-layer structure can be manufactured.
[0039]
In the first to third embodiments, the insulator layer and the conductor layer are laminated on both surfaces of the core substrate 1. However, a multilayer wiring board is manufactured so as to be laminated only on one surface of the core substrate 1. You may make it.
[Brief description of the drawings]
FIG. 1 is an explanatory cross-sectional view showing one configuration example of a core substrate used in the manufacturing method of the first embodiment.
FIG. 2 is an explanatory sectional view showing a method for manufacturing the core substrate shown in FIG. 1;
FIG. 3 is an explanatory sectional view showing a state where an insulator layer is laminated on the core substrate shown in FIG. 1;
FIG. 4 is an explanatory sectional view showing a state in which a hole is formed in the substrate shown in FIG. 3;
FIG. 5 is an explanatory sectional view showing a state where the substrate shown in FIG. 4 is plated.
FIG. 6 is an explanatory sectional view showing a state where a plating layer is formed on the substrate shown in FIG. 5;
FIG. 7 is an explanatory sectional view showing a state in which the substrate shown in FIG. 6 is etched.
FIG. 8 is an explanatory sectional view showing a process of laminating another layer on the substrate shown in FIG. 7;
FIG. 9 is an illustrative sectional view showing a state where another layer is laminated on the substrate shown in FIG. 7;
FIG. 10 is an illustrative sectional view showing the multilayer wiring board manufactured by the manufacturing method according to the first embodiment;
FIG. 11 is an illustrative sectional view showing a multilayer wiring board manufactured by the manufacturing method according to the second embodiment;
FIG. 12 is an illustrative sectional view showing a multilayer wiring board manufactured by the manufacturing method according to the third embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Core board, 2 ... Insulator layer, 3 ... Wiring layer, 4 ... Bump, 5 ... Conductive support, 6 ... Hole, 6a ... Via, 7: Conductor layer, 8, 11, 13, 15, 17: Multilayer wiring board, 9: Plating layer, 9a: Concavity, 10, 12, 14, 16: Wiring pattern.

Claims (4)

Two wiring layers formed on both surfaces of the first insulator layer are made of synthetic resin on at least one of the wiring layers of the wiring board connected by the first bump penetrating the first insulator layer. Forming a second insulator layer;
Irradiating the surface of the second insulator layer with a laser beam to form a hole exposing a position of the wiring layer connected to the first bump;
Plating is applied to the second insulator layer and the hole, and a first conductor layer is formed by plating applied to the second insulator layer. Forming a via connecting the first conductor layer and the wiring layer by plating,
Forming a plating layer to fill the via by plating the via;
A first etching step of etching the first conductor layer to form a predetermined first wiring pattern;
Separately, a third insulating layer made of a synthetic resin is laminated on a sheet-shaped conductive support having a second bump formed at a predetermined position, and the second insulating bump is pressed by the third insulating layer. Forming a laminate of a sheet-shaped conductive support and a third insulator layer by penetrating through the body layer and exposing the tip of the second bump from the third insulator layer; ,
The tip of the second bump formed in the stack forming step is pressed against the surface of the plating layer on the via remaining in the first etching step, and the first wiring formed in the first etching step is pressed. Laminating the third insulator layer and the sheet-shaped conductive support on a pattern;
A second etching step of etching the sheet-shaped conductive support to form a predetermined second wiring pattern,
A method for manufacturing a multilayer wiring board, comprising: forming an interlayer connection in which the first bump, the via, the plating layer, and the second bump are vertically stacked. Forming a fourth insulator layer made of a synthetic resin on the second wiring pattern formed in the second etching step;
Irradiating the surface of the fourth insulator layer with a laser beam to form a second hole that exposes a position of the second wiring pattern connected to the second bump;
Plating on the fourth insulator layer and the second hole to form a second conductor layer by plating on the fourth insulator layer; Forming a second via connecting the second conductor layer and the second wiring pattern by plating applied to the hole of
Plating the second via to form a second plating layer filling the second via;
A third etching step of etching the second conductor layer to form a predetermined third wiring pattern;
2. The method according to claim 1, wherein an interlayer connection in which the second via is vertically stacked is formed on the second bump. The tip of the second bump formed in the laminate forming step is pressed against the surface of the second plating layer on the second via formed in the third etching step, and the third etching step is performed. A laminating step of laminating the third insulator layer and the sheet-shaped conductive support on the third wiring pattern formed by
A fourth etching step of etching the sheet-like conductive support laminated in the laminating step to form a predetermined fourth wiring pattern;
3. The interlayer connection according to claim 2, wherein the second bumps stacked in the stacking step are vertically stacked on the second plating layer filled in the second via. A method for manufacturing a multilayer wiring board. Forming, on the other wiring layer of the wiring substrate, the same configuration as that stacked on the one wiring layer, the via and the bump stacked on the other wiring layer; 4. The method for manufacturing a multilayer wiring board according to claim 1, wherein an interlayer connection is formed by vertically stacking the one bump.

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