JP2010103195A5 - - Google Patents

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JP2010103195A5
JP2010103195A5 JP2008271360A JP2008271360A JP2010103195A5 JP 2010103195 A5 JP2010103195 A5 JP 2010103195A5 JP 2008271360 A JP2008271360 A JP 2008271360A JP 2008271360 A JP2008271360 A JP 2008271360A JP 2010103195 A5 JP2010103195 A5 JP 2010103195A5
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semiconductor device
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metal pattern
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積層された複数の半導体チップを備える積層型半導体装置であって、
前記複数の半導体チップは、回路領域と、前記回路領域の素子と電気的に接続された第１のバンプと、前記回路領域の素子に電気的に接続されない第２のバンプとをそれぞれ有し、重なり合う前記半導体チップ間で対向する前記第１のバンプ同士、および、重なり合う前記半導体チップ間で対向する前記第２のバンプ同士が接合されている積層型半導体装置。 A stacked semiconductor device comprising a plurality of stacked semiconductor chips,
The plurality of semiconductor chips each have a circuit region, a first bump electrically connected to an element in the circuit region, and a second bump not electrically connected to an element in the circuit region, A stacked semiconductor device in which the first bumps facing each other between the overlapping semiconductor chips and the second bumps facing each other between the overlapping semiconductor chips are joined. 前記複数の半導体チップはそれぞれ複数のＴＳＶ（Through Si Via）を備え、
前記第１のバンプおよび前記第２のバンプは、それぞれ前記ＴＳＶの先端に形成されている請求項１に記載の積層型半導体装置。 Each of the plurality of semiconductor chips includes a plurality of TSVs (Through Si Vias),
The stacked semiconductor device according to claim 1, wherein each of the first bump and the second bump is formed at a tip of the TSV. 前記半導体チップ上にメタルパターンを備え、
前記第２のバンプは、前記メタルパターン上に形成されている請求項１または２に記載の積層型半導体装置。 A metal pattern is provided on the semiconductor chip,
The stacked semiconductor device according to claim 1, wherein the second bump is formed on the metal pattern. 前記メタルパターン上には、複数の前記第２のバンプが形成されており、
前記複数の第２のバンプは、少なくとも接合後において一体となり前記メタルパターン上で隙間の無い接合層を形成する請求項３に記載の積層型半導体装置。 A plurality of the second bumps are formed on the metal pattern,
The stacked semiconductor device according to claim 3, wherein the plurality of second bumps are integrated at least after bonding to form a bonding layer having no gap on the metal pattern. 前記メタルパターンは、前記回路領域を閉じて囲むパターンである請求項３または４に記載の積層型半導体装置。   The stacked semiconductor device according to claim 3, wherein the metal pattern is a pattern that closes and surrounds the circuit region. 前記メタルパターンは、前記半導体チップの外周部に接するパターンである請求項３ないし５のいずれか１項に記載の積層型半導体装置。   6. The stacked semiconductor device according to claim 3, wherein the metal pattern is a pattern in contact with an outer peripheral portion of the semiconductor chip. 前記メタルパターンは、前記半導体チップの外周部から離間したパターンである請求項３ないし５のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 3, wherein the metal pattern is a pattern separated from an outer peripheral portion of the semiconductor chip. 前記回路領域の発熱分布において、発熱の大きい領域に隣接する前記メタルパターンの幅は、発熱の小さい領域に隣接する前記メタルパターンの幅よりも大きい請求項３ないし７のいずれか１項に記載の積層型半導体装置。   8. The heat generation distribution of the circuit area according to claim 3, wherein a width of the metal pattern adjacent to a region where heat generation is large is larger than a width of the metal pattern adjacent to a region where heat generation is small. Stacked semiconductor device. 前記半導体チップは、複数の前記第１のバンプと複数の前記第２のバンプとを有し、前記第２のバンプの単位面積あたりの密度は、前記第１のバンプの単位あたりの密度より大きい請求項１ないし８のいずれか１項に記載の積層型半導体装置。   The semiconductor chip has a plurality of the first bumps and a plurality of the second bumps, and the density per unit area of the second bumps is larger than the density per unit of the first bumps. The stacked semiconductor device according to claim 1. 前記第１のバンプと前記第２のバンプはそれぞれ同一の材質である請求項１ないし９のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the first bump and the second bump are made of the same material. 前記第１のバンプと前記第２のバンプはそれぞれ同一の大きさである請求項１ないし１０のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the first bump and the second bump have the same size. 前記第１のバンプの直径と前記第２のバンプの直径は同一である請求項１ないし１１のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein a diameter of the first bump and a diameter of the second bump are the same. 前記半導体チップの表面からの前記第１のバンプの接合面の高さは、前記半導体チップの表面からの前記第２のバンプの接合面の高さと同一である請求項１ないし１２のいずれか１項に記載の積層型半導体装置。   The height of the bonding surface of the first bump from the surface of the semiconductor chip is the same as the height of the bonding surface of the second bump from the surface of the semiconductor chip. The stacked semiconductor device according to the item. 前記半導体チップの表面からの前記第１のバンプの接合面の高さは、前記半導体チップの表面からの前記第２のバンプの接合面の高さよりも高い請求項１ないし１２のいずれか１項に記載の積層型半導体装置。   The height of the bonding surface of the first bump from the surface of the semiconductor chip is higher than the height of the bonding surface of the second bump from the surface of the semiconductor chip. 2. A stacked semiconductor device according to 1. 前記第１のバンプと前記第２のバンプとは、同一工程により形成される請求項１ないし１４のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the first bump and the second bump are formed by the same process. 前記第２のバンプは、前記回路領域の外側に形成される請求項１ないし１５のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the second bump is formed outside the circuit region. 積層した半導体チップ間にアンダーフィルが充填されている請求項１ないし１６のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein an underfill is filled between stacked semiconductor chips. 積層された前記複数の半導体チップのうち最外の前記半導体チップの少なくとも一面に接合されたヒートスプレッタを備える請求項１ないし１７のいずれか１項に記載の積層型半導体装置。   18. The stacked semiconductor device according to claim 1, further comprising a heat spreader bonded to at least one surface of the outermost semiconductor chip among the plurality of stacked semiconductor chips. 前記最外の半導体チップの前記第２のバンプが前記ヒートスプレッタに接合される請求項１８に記載の積層型半導体装置。   The stacked semiconductor device according to claim 18, wherein the second bump of the outermost semiconductor chip is bonded to the heat spreader. 積層された複数の半導体チップを備える積層型半導体装置であって、
前記複数の半導体チップは、回路領域と、前記回路領域の素子に電気的に接続されたバンプとをそれぞれ有し、互いに重なり合った前記半導体チップ間で対向する前記バンプ同士が接合されており、
互いに重なり合った前記半導体チップの少なくとも一方には、重なり合う前記半導体チップ間の接合を補強する、前記半導体チップの前記少なくとも一方の表面の一部を露出した状態で予め定められた高さを有する凸部が設けられている積層型半導体装置。 A stacked semiconductor device comprising a plurality of stacked semiconductor chips,
The plurality of semiconductor chips each have a circuit region and a bump electrically connected to an element of the circuit region, and the bumps facing each other between the semiconductor chips overlapping each other are bonded together,
At least one of the semiconductor chips overlapping each other has a convex portion having a predetermined height in a state in which a part of the at least one surface of the semiconductor chip is exposed to reinforce the bonding between the overlapping semiconductor chips. A stacked semiconductor device provided with 前記凸部は、前記複数の半導体チップのそれぞれに設けられており、重なり合う前記半導体チップ間で対向する前記凸部同士が接合されている請求項２０に記載の積層型半導体装置。   21. The stacked semiconductor device according to claim 20, wherein the convex portion is provided on each of the plurality of semiconductor chips, and the convex portions facing each other between the overlapping semiconductor chips are bonded to each other. 前記凸部は、前記回路領域の素子に電気的に接続されていない請求項２０または２１に記載の積層型半導体装置。   The stacked semiconductor device according to claim 20, wherein the convex portion is not electrically connected to an element in the circuit region. 前記複数の半導体チップはそれぞれ複数のＴＳＶ（Through Si Via）を備え、
前記バンプおよび前記凸部は、それぞれ前記ＴＳＶの先端に形成されている請求項２０から２２のいずれか一項に記載の積層型半導体装置。 Each of the plurality of semiconductor chips includes a plurality of TSVs (Through Si Vias),
The stacked semiconductor device according to any one of claims 20 to 22, wherein the bump and the protrusion are each formed at a tip of the TSV. 前記半導体チップ上にメタルパターンを備え、
前記凸部は、前記メタルパターン上に形成されている請求項２０から２３のいずれか一項に記載の積層型半導体装置。 A metal pattern is provided on the semiconductor chip,
24. The stacked semiconductor device according to claim 20, wherein the convex portion is formed on the metal pattern. 前記バンプと前記凸部とはそれぞれ同一の材質である請求項２０から２４のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to any one of claims 20 to 24, wherein the bump and the protrusion are made of the same material. 前記バンプと前記凸部とは、同一工程により形成される請求項２０から２５のいずれか１項に記載の積層型半導体装置。   26. The stacked semiconductor device according to claim 20, wherein the bump and the protrusion are formed in the same process. 回路領域を有する半導体チップに、前記回路領域の素子と電気的に接続された第１のバンプと、前記回路領域の素子とは電気的に接続されない第２のバンプとを形成するバンプ形成ステップと、
前記バンプ形成ステップを経た複数の前記半導体チップを積み重ね、対向する第１のバンプ同士、および対向する第２のバンプ同士を接合する積層ステップと、
を備える積層型半導体装置の製造方法。 A bump forming step of forming, on a semiconductor chip having a circuit area, a first bump electrically connected to an element in the circuit area and a second bump not electrically connected to an element in the circuit area; ,
Stacking the plurality of semiconductor chips that have undergone the bump forming step, and laminating the first bumps facing each other, and the second bumps facing each other,
A method for manufacturing a stacked semiconductor device. 前記半導体チップにＴＳＶ（Through Si Via）を形成するＴＳＶ形成ステップを更に備え、
前記バンプ形成ステップでは、前記第１のバンプおよび前記第２のバンプを、それぞれ前記ＴＳＶの先端に形成する請求項２７に記載の積層型半導体装置の製造方法。 A TSV forming step of forming a TSV (Through Si Via) on the semiconductor chip;
28. The method of manufacturing a stacked semiconductor device according to claim 27, wherein, in the bump forming step, the first bump and the second bump are each formed at a tip of the TSV. 前記半導体チップ上にメタルパターンを形成するメタルパターン形成ステップを更に備え、
前記バンプ形成ステップでは、前記第２のバンプを前記メタルパターン上に形成する請求項２７または２８に記載の積層型半導体装置の製造方法。 A metal pattern forming step of forming a metal pattern on the semiconductor chip;
29. The method for manufacturing a stacked semiconductor device according to claim 27, wherein, in the bump forming step, the second bump is formed on the metal pattern. 前記バンプ形成ステップでは、複数の前記第２のバンプを形成し、
前記複数の第２のバンプは、前記積層ステップにより一体となり、前記メタルパターン上で隙間の無い接合層を形成する請求項２９に記載の積層型半導体装置の製造方法。 In the bump forming step, a plurality of the second bumps are formed,
30. The method of manufacturing a stacked semiconductor device according to claim 29, wherein the plurality of second bumps are integrated by the stacking step to form a bonding layer having no gap on the metal pattern. 前記メタルパターン形成ステップにより形成する前記メタルパターンは、前記回路領域を閉じて囲むパターンである請求項２９または３０に記載の積層型半導体装置の製造方法。   31. The method for manufacturing a stacked semiconductor device according to claim 29, wherein the metal pattern formed by the metal pattern forming step is a pattern that closes and surrounds the circuit region. 前記メタルパターン形成ステップにより形成する前記メタルパターンは、前記半導体チップの外周部に接するパターンである請求項２９ないし３１のいずれか１項に記載の積層型半導体装置の製造方法。   32. The method for manufacturing a stacked semiconductor device according to claim 29, wherein the metal pattern formed by the metal pattern forming step is a pattern in contact with an outer peripheral portion of the semiconductor chip. 前記メタルパターン形成ステップにより形成する前記メタルパターンは、前記半導体チップの外周部に接しないパターンである請求項２９ないし３２のいずれか１項に記載の積層型半導体装置の製造方法。   33. The method of manufacturing a stacked semiconductor device according to claim 29, wherein the metal pattern formed by the metal pattern forming step is a pattern that does not contact an outer peripheral portion of the semiconductor chip. 前記回路領域の発熱分布において、発熱の大きい領域に隣接する前記メタルパターンの幅が、発熱の小さい領域に隣接する前記メタルパターンの幅よりも大きくなるように、前記バンプ形成ステップにより形成する請求項２９ないし３３のいずれか１項に記載の積層型半導体装置の製造方法。   The heat generation distribution of the circuit region is formed by the bump forming step so that a width of the metal pattern adjacent to a region where heat generation is large is larger than a width of the metal pattern adjacent to a region where heat generation is small. 34. A method of manufacturing a stacked semiconductor device according to any one of 29 to 33. 前記バンプ形成ステップでは、複数の前記第１のバンプと複数の前記第２のバンプとを形成し、
前記バンプ形成ステップにより形成する前記複数の第２のバンプの単位面積あたりの密度は、前記複数の第１のバンプの単位あたりの密度より大きい請求項２７ないし３４のいずれか１項に記載の積層型半導体装置の製造方法。 In the bump forming step, a plurality of the first bumps and a plurality of the second bumps are formed,
35. The lamination according to claim 27, wherein a density per unit area of the plurality of second bumps formed by the bump forming step is larger than a density per unit of the plurality of first bumps. Type semiconductor device manufacturing method. 前記バンプ形成ステップでは、前記第１のバンプと前記第２のバンプとをそれぞれ同一の材質で形成する請求項２９ないし３５のいずれか１項に記載の積層型半導体装置の製造方法。   36. The method for manufacturing a stacked semiconductor device according to claim 29, wherein, in the bump forming step, the first bump and the second bump are formed of the same material. 前記バンプ形成ステップでは、前記第１のバンプと前記第２のバンプとをそれぞれ同一の大きさで形成する請求項２９ないし３６のいずれか１項に記載の積層型半導体装置の製造方法。   37. The method for manufacturing a stacked semiconductor device according to claim 29, wherein, in the bump forming step, the first bump and the second bump are formed to have the same size. 前記バンプ形成ステップでは、前記第１のバンプの直径と前記第２のバンプの直径が同一になるように形成する請求項２９ないし３７のいずれか１項に記載の積層型半導体装置の製造方法。   38. The method of manufacturing a stacked semiconductor device according to any one of claims 29 to 37, wherein in the bump forming step, the first bump and the second bump are formed to have the same diameter. 前記バンプ形成ステップでは、前記半導体チップの表面からの前記第１のバンプの接合面の高さが、前記半導体チップの表面からの前記第２のバンプの接合面の高さと同一になるように形成する請求項２９ないし３８のいずれか１項に記載の積層型半導体装置の製造方法。   In the bump forming step, the height of the bonding surface of the first bump from the surface of the semiconductor chip is the same as the height of the bonding surface of the second bump from the surface of the semiconductor chip. The method for manufacturing a stacked semiconductor device according to any one of claims 29 to 38. 前記バンプ形成ステップでは、前記半導体チップの表面からの前記第１のバンプの接合面の高さが、前記半導体チップの表面からの前記第２のバンプの接合面の高さよりも高くなるように形成する請求項２９ないし３８のいずれか１項に記載の積層型半導体装置の製造方法。   In the bump forming step, the height of the bonding surface of the first bump from the surface of the semiconductor chip is higher than the height of the bonding surface of the second bump from the surface of the semiconductor chip. The method for manufacturing a stacked semiconductor device according to any one of claims 29 to 38. 前記バンプ形成ステップでは、前記第１のバンプと前記第２のバンプとを同一工程で形成する請求項２９ないし４０のいずれか１項に記載の積層型半導体装置の製造方法。   41. The method for manufacturing a stacked semiconductor device according to claim 29, wherein, in the bump forming step, the first bump and the second bump are formed in the same process. 前記バンプ形成ステップでは、前記第２のバンプを前記回路領域の外側に形成する請求項２９ないし４１のいずれか１項に記載の積層型半導体装置の製造方法。   42. The method for manufacturing a stacked semiconductor device according to claim 29, wherein, in the bump forming step, the second bump is formed outside the circuit region. 前記積層ステップは、前記バンプ形成ステップを経た前記半導体チップが２次元的に複数配置された半導体基板を、積み重ねて接合する請求項２９ないし４２のいずれか１項に記載の積層型半導体装置の製造方法。   43. The manufacturing of a stacked semiconductor device according to any one of claims 29 to 42, wherein the stacking step stacks and joins semiconductor substrates on which a plurality of the semiconductor chips subjected to the bump forming step are two-dimensionally arranged. Method. 前記積層ステップは、２次元的に複数配置される半導体チップの境界に設けられた指標をアライメントマークとして位置合わせを行い、複数の半導体基板を積み重ねる請求項４３に記載の積層型半導体装置の製造方法。   44. The method of manufacturing a stacked semiconductor device according to claim 43, wherein the stacking step performs alignment using an index provided at a boundary between a plurality of two-dimensionally arranged semiconductor chips as an alignment mark, and stacks a plurality of semiconductor substrates. . 積層した半導体チップ間をアンダーフィルで充填するアンダーフィル充填ステップを更に備える請求項２９ないし４４のいずれか１項に記載の積層型半導体装置の製造方法。   45. The method for manufacturing a stacked semiconductor device according to any one of claims 29 to 44, further comprising an underfill filling step of filling a space between the stacked semiconductor chips with an underfill. 積層した半導体チップの最外面の少なくとも一面にヒートスプレッタを接合するヒートスプレッタ接合ステップを更に備える請求項２９ないし４５のいずれか１項に記載の積層型半導体装置の製造方法。   46. The method for manufacturing a stacked semiconductor device according to any one of claims 29 to 45, further comprising a heat spreader bonding step of bonding a heat spreader to at least one of the outermost surfaces of the stacked semiconductor chips. 回路領域を有する半導体チップに、前記回路領域の素子と電気的に接続されたバンプを形成するバンプ形成ステップと、
前記バンプ形成ステップを経た複数の前記半導体チップを積み重ね、対向する前記バンプ同士を接合する積層ステップと、
互いに重なり合った前記半導体チップの少なくとも一方には、重なり合う前記半導体チップ間の接合を補強する、前記半導体チップの前記少なくとも一方の表面の一部を露出した状態で予め定められた高さを有する凸部を形成する凸部形成ステップと、
を有する積層型半導体装置の製造方法。 Forming a bump electrically connected to an element of the circuit region on a semiconductor chip having a circuit region; and
A plurality of the semiconductor chips that have undergone the bump forming step are stacked, and a stacking step of bonding the bumps facing each other;
At least one of the semiconductor chips overlapping each other has a convex portion having a predetermined height in a state in which a part of the at least one surface of the semiconductor chip is exposed to reinforce the bonding between the overlapping semiconductor chips. A convex forming step for forming
A method of manufacturing a stacked semiconductor device having 前記凸部形成ステップでは、前記複数の半導体チップのそれぞれに前記凸部を形成し、
前記積層ステップでは、重なり合う前記半導体チップ間で対向する前記凸部同士を接合する請求項４７に記載の積層型半導体装置の製造方法。 In the convex portion forming step, the convex portion is formed on each of the plurality of semiconductor chips,
48. The method for manufacturing a stacked semiconductor device according to claim 47, wherein, in the stacking step, the convex portions facing each other between the overlapping semiconductor chips are joined. 前記凸部は、前記回路領域の素子に電気的に接続されていない請求項４７または４８に記載の積層型半導体装置の製造方法。   49. The method for manufacturing a stacked semiconductor device according to claim 47, wherein the convex portion is not electrically connected to an element in the circuit region. 前記半導体チップにＴＳＶ（Through Si Via）を形成するＴＳＶ形成ステップを更に備え、
前記バンプ形成ステップでは、前記バンプおよび前記凸部を、それぞれ前記ＴＳＶの先端に形成する請求項４７から４９のいずれか一項に記載の積層型半導体装置の製造方法。 A TSV forming step of forming a TSV (Through Si Via) on the semiconductor chip;
50. The method for manufacturing a stacked semiconductor device according to any one of claims 47 to 49, wherein, in the bump forming step, the bump and the convex portion are respectively formed at a tip of the TSV. 前記半導体チップ上にメタルパターンを形成するメタルパターン形成ステップを更に備え、
前記バンプ形成ステップでは、前記凸部を前記メタルパターン上に形成する請求項４７から５０のいずれか一項に記載の積層型半導体装置の製造方法。 A metal pattern forming step of forming a metal pattern on the semiconductor chip;
51. The method for manufacturing a stacked semiconductor device according to claim 47, wherein in the bump forming step, the convex portion is formed on the metal pattern. 前記バンプ形成ステップおよび前記凸部形成ステップでは、前記バンプと前記凸部とをそれぞれ同一の材質で形成する請求項４７から５１のいずれか１項に記載の積層型半導体装置の製造方法。   52. The method for manufacturing a stacked semiconductor device according to claim 47, wherein, in the bump forming step and the convex portion forming step, the bump and the convex portion are formed of the same material. 前記凸部形成ステップでは、前記バンプ形成ステップと同一工程により前記凸部を形成する請求項４７から５２のいずれか１項に記載の積層型半導体装置の製造方法。   53. The method for manufacturing a stacked semiconductor device according to any one of claims 47 to 52, wherein in the projecting portion forming step, the projecting portion is formed by the same process as the bump forming step. 回路領域と、
前記回路領域の素子と電気的に接続された第１のバンプと、
前記回路領域の素子に電気的に接続されない第２のバンプと、をそれぞれ有する半導体基板であって、
他の半導体基板と積層されるときに、前記第１のバンプは、前記他の半導体基板に設けられた、前記他の半導体基板の前記回路領域の素子と電気的に接続された第１のバンプと接合され、前記第２のバンプは、前記他の半導体基板に設けられた、前記他の半導体基板の前記回路領域の素子と電気的に接続されない第２のバンプと接合される半導体基板。 Circuit area,
A first bump electrically connected to an element in the circuit area;
A semiconductor substrate having a second bump that is not electrically connected to an element in the circuit region,
When stacked with another semiconductor substrate, the first bump is provided on the other semiconductor substrate and electrically connected to an element in the circuit region of the other semiconductor substrate. And the second bump is bonded to a second bump that is provided on the other semiconductor substrate and is not electrically connected to an element in the circuit region of the other semiconductor substrate. 複数のＴＳＶ（Through Si Via）をさらに備え、
前記第１のバンプおよび前記第２のバンプは、それぞれ前記ＴＳＶの先端に形成されている請求項５４に記載の半導体基板。 A plurality of TSVs (Through Si Via)
55. The semiconductor substrate according to claim 54, wherein each of the first bump and the second bump is formed at a tip of the TSV. メタルパターンをさらに備え、
前記第２のバンプは、前記メタルパターン上に形成されている請求項５４または５５に記載の半導体基板。 It further has a metal pattern,
56. The semiconductor substrate according to claim 54 or 55, wherein the second bump is formed on the metal pattern. 前記メタルパターン上には、複数の前記第２のバンプが形成されており、
前記複数の第２のバンプは、少なくとも接合後において一体となり前記メタルパターン上で隙間の無い接合層を形成する請求項５６に記載の半導体基板。 A plurality of the second bumps are formed on the metal pattern,
57. The semiconductor substrate according to claim 56, wherein the plurality of second bumps are integrated at least after bonding to form a bonding layer having no gap on the metal pattern. 前記メタルパターンは、前記回路領域を閉じて囲むパターンである請求項５６または５７に記載の半導体基板。   58. The semiconductor substrate according to claim 56, wherein the metal pattern is a pattern that closes and surrounds the circuit region. 前記半導体基板は複数の半導体チップを含み、
前記メタルパターンは、前記半導体チップの外周部に接するパターンである請求項５６ないし５８のいずれか１項に記載の半導体基板。 The semiconductor substrate includes a plurality of semiconductor chips,
59. The semiconductor substrate according to claim 56, wherein the metal pattern is a pattern in contact with an outer peripheral portion of the semiconductor chip. 前記半導体基板は複数の半導体チップを含み、
前記メタルパターンは、前記半導体チップの外周部から離間したパターンである請求項５６ないし５８のいずれか１項に記載の半導体基板。 The semiconductor substrate includes a plurality of semiconductor chips,
59. The semiconductor substrate according to claim 56, wherein the metal pattern is a pattern separated from an outer peripheral portion of the semiconductor chip. 前記回路領域の発熱分布において、発熱の大きい領域に隣接する前記メタルパターンの幅は、発熱の小さい領域に隣接する前記メタルパターンの幅よりも大きい請求項５６ないし６０のいずれか１項に記載の半導体基板。   61. The heat distribution of the circuit area according to claim 56, wherein a width of the metal pattern adjacent to a region where heat generation is large is larger than a width of the metal pattern adjacent to a region where heat generation is small. Semiconductor substrate. 前記半導体チップは、複数の前記第１のバンプと複数の前記第２のバンプとを有し、前記第２のバンプの単位面積あたりの密度は、前記第１のバンプの単位あたりの密度より大きい請求項５４ないし６１のいずれか１項に記載の半導体基板。   The semiconductor chip has a plurality of the first bumps and a plurality of the second bumps, and the density per unit area of the second bumps is larger than the density per unit of the first bumps. The semiconductor substrate according to any one of claims 54 to 61. 前記第１のバンプと前記第２のバンプはそれぞれ同一の材質である請求項５４ないし６２のいずれか１項に記載の半導体基板。   The semiconductor substrate according to any one of claims 54 to 62, wherein the first bump and the second bump are made of the same material. 前記第１のバンプと前記第２のバンプはそれぞれ同一の大きさである請求項５４ないし６３のいずれか１項に記載の半導体基板。   64. The semiconductor substrate according to claim 54, wherein the first bump and the second bump have the same size. 前記第１のバンプの直径と前記第２のバンプの直径は同一である請求項５４ないし６４のいずれか１項に記載の半導体基板。   65. The semiconductor substrate according to claim 54, wherein a diameter of the first bump and a diameter of the second bump are the same. 前記半導体チップの表面からの前記第１のバンプの接合面の高さは、前記半導体チップの表面からの前記第２のバンプの接合面の高さと同一である請求項５４ないし６５のいずれか１項に記載の半導体基板。   66. The height of the bonding surface of the first bump from the surface of the semiconductor chip is the same as the height of the bonding surface of the second bump from the surface of the semiconductor chip. The semiconductor substrate according to item. 前記半導体チップの表面からの前記第１のバンプの接合面の高さは、前記半導体チップの表面からの前記第２のバンプの接合面の高さよりも高い請求項５４ないし６５のいずれか１項に記載の半導体基板。   66. The height of the bonding surface of the first bump from the surface of the semiconductor chip is higher than the height of the bonding surface of the second bump from the surface of the semiconductor chip. A semiconductor substrate according to 1. 前記第１のバンプと前記第２のバンプとは、同一工程により形成される請求項５４ないし６７のいずれか１項に記載の半導体基板。   68. The semiconductor substrate according to claim 54, wherein the first bump and the second bump are formed by the same process. 前記第２のバンプは、前記回路領域の外側に形成される請求項５４ないし６８のいずれか１項に記載の半導体基板。   69. The semiconductor substrate according to claim 54, wherein the second bump is formed outside the circuit region. 積層した半導体チップ間にアンダーフィルが充填される請求項５４ないし６９のいずれか１項に記載の半導体基板。   The semiconductor substrate according to any one of claims 54 to 69, wherein an underfill is filled between the stacked semiconductor chips. 積層された前記複数の半導体チップのうち最外の前記半導体チップの少なくとも一面に接合されたヒートスプレッタを備える請求項５４ないし７０のいずれか１項に記載の半導体基板。   71. The semiconductor substrate according to any one of claims 54 to 70, further comprising a heat spreader bonded to at least one surface of the outermost semiconductor chip among the plurality of stacked semiconductor chips. 前記最外の半導体チップの前記第２のバンプが前記ヒートスプレッタに接合される請求項７１に記載の半導体基板。   The semiconductor substrate according to claim 71, wherein the second bumps of the outermost semiconductor chip are bonded to the heat spreader. 回路領域と、
前記回路領域の素子に電気的に接続され、他の半導体基板の回路領域の素子に電気的に接続されたバンプと接合されるバンプと、
前記他の半導体基板と接合される表面の一部を露出した状態で予め定められた高さを有する凸部と
を備える半導体基板。 Circuit area,
Bumps that are electrically connected to the elements in the circuit region and bonded to the bumps electrically connected to the elements in the circuit region of the other semiconductor substrate;
A semiconductor substrate comprising a convex portion having a predetermined height in a state in which a part of a surface to be bonded to the other semiconductor substrate is exposed. 前記半導体基板は複数の半導体チップを含み、
前記凸部は、前記複数の半導体チップのそれぞれに設けられており、重なり合う前記半導体チップ間で対向する前記凸部同士が接合されている請求項７３に記載の半導体基板。 The semiconductor substrate includes a plurality of semiconductor chips,
The semiconductor substrate according to claim 73, wherein the convex portions are provided in each of the plurality of semiconductor chips, and the convex portions facing each other between the overlapping semiconductor chips are bonded to each other. 前記凸部は、前記回路領域の素子に電気的に接続されていない請求項７３または７４に記載の半導体基板。   The semiconductor substrate according to claim 73 or 74, wherein the convex portion is not electrically connected to an element in the circuit region. 複数のＴＳＶ（Through Si Via）をさらに備え、
前記バンプおよび前記凸部は、それぞれ前記ＴＳＶの先端に形成されている請求項７３から７５のいずれか一項に記載の半導体基板。 A plurality of TSVs (Through Si Via)
The semiconductor substrate according to any one of claims 73 to 75, wherein the bump and the protrusion are each formed at a tip of the TSV. メタルパターンをさらに備え、
前記凸部は、前記メタルパターン上に形成されている請求項７３から７６のいずれか一項に記載の半導体基板。 It further has a metal pattern,
77. The semiconductor substrate according to claim 73, wherein the convex portion is formed on the metal pattern. 前記バンプと前記凸部とはそれぞれ同一の材質である請求項７３から７７のいずれか１項に記載の半導体基板。   The semiconductor substrate according to any one of claims 73 to 77, wherein the bump and the convex portion are made of the same material. 前記バンプと前記凸部とは、同一工程により形成される請求項７３から７８のいずれか１項に記載の半導体基板。   79. The semiconductor substrate according to claim 73, wherein the bump and the convex portion are formed by the same process.
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