CN104009014A - Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method - Google Patents
Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method Download PDFInfo
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- CN104009014A CN104009014A CN201410173160.6A CN201410173160A CN104009014A CN 104009014 A CN104009014 A CN 104009014A CN 201410173160 A CN201410173160 A CN 201410173160A CN 104009014 A CN104009014 A CN 104009014A
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- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
The invention relates to an integrated passive device wafer-level packaging three-dimensional stacked structure and a manufacturing method. The integrated passive device wafer-level packaging three-dimensional stacked structure comprises a wafer-level packaging chip and an IPD chip. The IPD chip comprises a glass substrate, wherein an IPD device and a metal wiring layer are arranged on the front surface of the glass substrate, the back surface of the glass substrate is etched to form TGV holes, back surface metal wiring layers are arranged on the back surface of the glass substrate and the inner surfaces of the TGV holes, a welding ball is arranged on a welding pad of each back surface metal wiring layer, and the welding balls are connected with a PCB. The manufacturing method of the three-dimensional stacked structure comprises the following steps that (1) the wafer-level packaging chip and the IPD chip of the glass substrate are stacked; (2) the back surface of the IPD chip is etched to form the TGV holes, the back surface metal wiring layer is manufactured on the back surface of the glass substrate; (3) the back surface metal wiring layer is etched into two insulated parts; the welding pads and welding balls are manufactured on the two parts of the back surface metal wiring layer, and the welding balls are connected with the PCB. By means of the integrated passive device wafer-level packaging three-dimensional stacked structure and the manufacturing method, short-distance interconnection between the chip and the IPD device is achieved, and the electric quality is improved.
Description
Technical field
The present invention relates to a kind of wafer-level packaging three-dimensional stacking structure, especially a kind of integrated passive devices wafer-level packaging three-dimensional stacking structure and manufacture method, belong to high-density electronic package technical field.
Background technology
Wafer-level packaging and traditional different being of packaged type, traditional chip package is first to cut envelope again to survey, the former chip size of Area Ratio after encapsulation at least increases by 20%; Wafer-level packaging is first on full wafer wafer, to carry out packaging and testing, and then scribing cuts apart, and therefore, volume and bare chip after encapsulation are measure-alike, can significantly reduce the chip size after encapsulation.Wafer stage chip encapsulation provides and can substitute current bonding wire BGA(Ball Grid Array, the PCB of ball grid array structure) and flip-chip the BGA low cost, the high-performance integration packaging that encapsulate.Wafer scale RDL(wiring layer is more directly passed through in the wiring of the signal of wafer-level packaging, electric power and ground wire) technique realization, no longer need wafer convex point preparation and base plate for packaging, thereby reduction packaging cost, and can provide the electrical functions that is better than traditional bonding wire BGA and flip-chip BGA encapsulation.
Film integrating passive technology can provide the best functional density conventionally, and maximum set Cheng Du and minimum volume.Yet, the passive device of conventional films integrating passive deposits metal on Si wafer, and in high-frequency circuit, Semiconductor substrate Si can produce high-frequency vortex phenomenon, cause the performance of circuit to reduce, cannot meet high-frequency circuit, particularly RF(radio frequency) performance requirement of device.And the passive device of integrating passive in glass substrate can solve that the electric capacity quality factor q value running in Si integrated passive devices is lower, inductance bandwidth is narrower and high-frequency vortex problem, meets high-frequency circuit, the particularly performance requirement of RF device.
In prior art, the weak point of wafer stage chip encapsulation and the passive device maximum of film integrating passive is that integrated level is lower.Generally, wafer stage chip encapsulates the not passive device of integrating passive, and the passive device mating with it has occupied approximately 80% board area and 70% assembling product cost.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of integrated passive devices wafer-level packaging three-dimensional stacking structure and manufacture method are provided, wafer stage chip encapsulation and the passive device of glass integrating passive (IPD) are bonded together by wafer scale bonding technology, realize the short distance interconnection between chip and IPD device, promoted electricity quality.
According to technical scheme provided by the invention, described integrated passive devices wafer-level packaging three-dimensional stacking structure, comprises wafer-level packaging chip and IPD chip; It is characterized in that: described IPD chip comprises glass substrate, IPD device and the metal wiring layer that is connected IPD device are set in the front of glass substrate, metal wiring layer is connected with the chip signal port of wafer-level packaging chip; Back-etching at described glass substrate forms TGV hole, and metal wiring layer goes directly in TGV hole; At the back side of described glass substrate and the inner surface in TGV hole, back metal wiring layer is set, back metal wiring layer is divided into two parts of mutually insulated, this two parts back metal wiring layer is connected with metal wiring layer respectively, and on the pad of two parts back metal wiring layer, soldered ball being set respectively, soldered ball is connected with pcb board.
The thermal coefficient of expansion of described glass substrate is greater than silicon substrate, is less than pcb board.
Described IPD device is concordant with the front of IPD chip with metal wiring layer.
The manufacture method of described integrated passive devices wafer-level packaging three-dimensional stacking structure, is characterized in that, comprises the following steps:
(1) the IPD chip of wafer-level packaging chip and glass substrate is carried out stacking, the metal wiring layer of IPD chip front side is connected with the chip signal port of wafer-level packaging chip;
(2) back-etching at IPD chip obtains TGV hole, TGV hole by the back-etching of glass substrate to positive metal wiring layer;
(3) at the back spatter metal of glass substrate, at the back side of glass substrate, the inner surface in TGV hole obtains back metal wiring layer;
(4) back metal wiring layer is carried out to etching, back metal wiring layer is etched into two parts of mutually insulated;
(5) on the back metal wiring layer of two parts insulation, make respectively pad, on pad, make respectively soldered ball;
(6) said structure is interconnected by soldered ball and pcb board, complete the making of integrated passive devices wafer-level packaging three-dimensional stacking structure.
The present invention is that the three-dimensional of wafer stage chip encapsulation and the passive device of film integrating passive is integrated provides a set of efficient solution, that electronic product continues minification, increases one of solution of function, the trend that meets portable type electronic product " sooner, less, lighter ", and cost performance improves constantly.The present invention realizes the short distance interconnection between chip and passive passive integrated device (IPD), has promoted electricity quality; Meanwhile, the passive device of glass integrating passive has great lifting compared with the resonant circuit quality factor Q value of the passive device of Si integrating passive; And; the thermal coefficient of expansion of glass IPD chip is (thermal coefficient of expansion Si< glass <PCB) between Si chip and PCB support plate; the present invention has realized the step by step amplification of thermal coefficient of expansion in packaging body Z direction, for the Si chip of the superiors provides good stress buffer protective effect.Enforcement of the present invention meets the trend of electronic product development, mates with existing production technology, and be the three-dimensional Integrated Solution of a set of compact size high reliability.
Accompanying drawing explanation
Fig. 1～Fig. 6 is the schematic diagram of the manufacture process of three-dimensional stacking structure of the present invention.
Fig. 1 is the chip-stacked schematic diagram of wafer-level packaging chip and IPD.
Fig. 2 for making the schematic diagram in TGV hole on IPD chip.
Fig. 3 makes the schematic diagram of back metal wiring layer at the glass substrate back side.
Fig. 4 is for carrying out the schematic diagram of etching to back metal wiring layer.
Fig. 5 is for making the schematic diagram of soldered ball.
Fig. 6 is the schematic diagram of integrated passive devices wafer-level packaging three-dimensional stacking structure of the present invention.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Figure 6: described integrated passive devices wafer-level packaging three-dimensional stacking structure comprises pcb board 1, wafer-level packaging chip 2, IPD chip 3, glass substrate 4, IPD device 5, metal wiring layer 6, TGV hole 7, back metal wiring layer 8, pad 9, soldered ball 10, chip signal port one 1 etc.
As shown in Figure 6, three-dimensional stacking structure of the present invention is packaged on pcb board 1, comprises wafer-level packaging chip 2 and IPD chip 3; Described IPD chip 3 comprises glass substrate 4, IPD device 5 and the metal wiring layer 6 that is connected IPD device 5 are set in the front of glass substrate 4, IPD device 5 is concordant with the front of IPD chip 1 with metal wiring layer 6, and metal wiring layer 6 is connected with the chip signal port one 1 of wafer-level packaging chip 2; Back-etching at described glass substrate 4 forms TGV hole 7, the through metal wiring layer 6 in TGV hole 7; At the back side of described glass substrate 4 and the inner surface in TGV hole 7, back metal wiring layer 8 is set, back metal wiring layer 8 is divided into two parts of mutually insulated, this two parts back metal wiring layer 8 is connected with metal wiring layer 6 respectively, and on the pad 9 of two parts back metal wiring layer 8, soldered ball 10 being set respectively, soldered ball 10 is connected with pcb board 1;
The thermal coefficient of expansion of described glass substrate 4 is greater than silicon substrate, is less than pcb board 1; in three-dimensional stacking structure of the present invention; realized the step by step amplification of hot expansion system in packaging body Z direction, for the silicon of the superiors provides good stress buffer protective effect.
As shown in Fig. 1～Fig. 6, the manufacture method of integrated passive devices wafer-level packaging three-dimensional stacking structure of the present invention, comprises the following steps:
(1) as shown in Figure 1, the IPD chip of wafer-level packaging chip 2 and glass substrate 43 is carried out stacking, the metal wiring layer 6 in IPD chip 3 fronts is connected with the chip signal port one 1 of wafer-level packaging chip 2, and the signal of realizing between IPD chip 3 and wafer-level packaging chip 2 connects;
(2) as shown in Figure 2, at the back-etching of IPD chip 3, obtain TGV(Through Glass Via) hole 7, TGV hole 7 by the back-etching of glass substrate 4 to positive metal wiring layer 6;
(3) as shown in Figure 3,, at the back spatter metal of glass substrate 4, as copper or tungsten etc., at the back side of glass substrate 4,, the inner surface in TGV hole 7 obtains back metal wiring layer 8, the thickness of back metal wiring layer 8 is 1～30 micron;
(4) as shown in Figure 4, back metal wiring layer 8 is carried out to etching, back metal wiring layer 8 is etched into two parts of mutually insulated; The effect of described two parts back metal wiring layer 8 is that TGV hole is re-assigned to other position, to facilitate with pcb board 1, interconnects;
(5) as shown in Figure 5, on the back metal wiring layer 8 of two parts insulation, make respectively pad 9, on pad 9, make respectively soldered ball 10, realize and being connected with outside function;
(6) as shown in Figure 6, said structure is interconnected by soldered ball 10 and pcb board 1, complete the making of integrated passive devices wafer-level packaging three-dimensional stacking structure.
Claims (4)
1. an integrated passive devices wafer-level packaging three-dimensional stacking structure, comprises wafer-level packaging chip (2) and IPD chip (3); It is characterized in that: described IPD chip (3) comprises glass substrate (4), IPD device (5) and the metal wiring layer (6) that is connected IPD device (5) are set in the front of glass substrate (4), and metal wiring layer (6) is connected with the chip signal port (11) of wafer-level packaging chip (2); Back-etching at described glass substrate (4) forms TGV hole (7), and TGV hole (7) metal wiring layer (6) goes directly; At the back side of described glass substrate (4) and the inner surface of TGV hole (7), back metal wiring layer (8) is set, back metal wiring layer (8) is divided into two parts of mutually insulated, this two parts back metal wiring layer (8) is connected with metal wiring layer (6) respectively, and on the pad (9) of two parts back metal wiring layer (8), soldered ball (10) being set respectively, soldered ball (10) is connected with pcb board (1).
2. integrated passive devices wafer-level packaging three-dimensional stacking structure as claimed in claim 1, is characterized in that: the thermal coefficient of expansion of described glass substrate (4) is greater than silicon substrate, is less than pcb board (1).
3. integrated passive devices wafer-level packaging three-dimensional stacking structure as claimed in claim 1, is characterized in that: described IPD device (5) is concordant with the front of IPD chip (1) with metal wiring layer (6).
4. a manufacture method for integrated passive devices wafer-level packaging three-dimensional stacking structure, is characterized in that, comprises the following steps:
(1) the IPD chip (3) of wafer-level packaging chip (2) and glass substrate (4) is carried out stacking, the positive metal wiring layer (6) of IPD chip (3) is connected with the chip signal port (11) of wafer-level packaging chip (2);
(2) back-etching at IPD chip (3) obtains TGV hole (7), TGV hole (7) by the back-etching of glass substrate (4) to positive metal wiring layer (6);
(3) at the back spatter metal of glass substrate (4), at the back side of glass substrate (4), the inner surface of TGV hole (7) obtains back metal wiring layer (8);
(4) back metal wiring layer (8) is carried out to etching, back metal wiring layer (8) is etched into two parts of mutually insulated;
(5) on the back metal wiring layer (8) of two parts insulation, make respectively pad (9), on pad (9), make respectively soldered ball (10);
(6) said structure is interconnected by soldered ball (10) and pcb board (1), complete the making of integrated passive devices wafer-level packaging three-dimensional stacking structure.
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| CN104486907A (en) * | 2014-12-10 | 2015-04-01 | 华进半导体封装先导技术研发中心有限公司 | Three-dimensional integrated wafer-level package structure and package method for high-frequency IPD (Integrated Passive Device) module |
| CN107871718A (en) * | 2016-09-22 | 2018-04-03 | 台湾积体电路制造股份有限公司 | Semiconductor package part and forming method thereof |
| CN108346588A (en) * | 2017-09-30 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN113443602A (en) * | 2021-06-02 | 2021-09-28 | 中国科学院地质与地球物理研究所 | Wafer level packaging structure of micro electro mechanical system chip and manufacturing process thereof |
| CN116913875A (en) * | 2023-07-27 | 2023-10-20 | 华天科技（昆山）电子有限公司 | Wafer-level 3D stacking structure and manufacturing method thereof |
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