JP2003273321A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module by which the noise produced among wiring patterns is reduced and the heat dissipation effect can be obtained. <P>SOLUTION: The semiconductor module has upper and lower substrates which are arranged one above the other. Several signal wires and common potential wires which surround each of the signal wires at some intervals are provided on the upper and lower substrates. Semiconductors having electrode pads which are electrically connected with the signal wires and the common potential wires are provided on the upper and lower substrates. A support substrate having wiring patterns is provided under the lower substrate. First and second connection conductive layers provided between the upper substrate and the lower substrate electrically and mutually connect the signal wires and the common potential wires on the substrates. A third connection conductive layer is provided through the supporting substrate and electrically connects the first and the second connection conductive layers and the wiring patterns. The third connection conductive layer is connected to external connection terminals provided on the wiring patterns. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor module configured by laminating a plurality of substrates provided with semiconductor chips, and more particularly to the structure of the substrate.

[0002]

2. Description of the Related Art For example, SRAM (Static Random Access)
Memory), flash memory, DRAM (Dynamic RA)
Memory such as M) and CPU (Central Processing Uni
t) etc., and stack multiple semiconductor chips of different types or the same type.
Stacked modules in one package are being developed. That is, a chip / substrate structure in which semiconductor chips are arranged is formed on a substrate, and a plurality of chip / substrate structures are stacked. As such a semiconductor module, an SBM (System Block) in which each semiconductor chip is one functional block is used.
ck Module) is known.

FIG. 6 is a sectional view schematically showing a conventional semiconductor module. As shown in FIG. 6, the semiconductor module 51 has a structure in which a plurality of chip / substrate structures 55 each having a wiring pattern 53 and a semiconductor chip 54 are stacked on a substrate 52. An interlayer substrate 56 is provided between each chip / substrate structure 55, and a plurality of connection conductive layers 57 are provided on the interlayer substrate 56. The connection conductive layer 57 electrically connects the wiring patterns 53 of each chip / substrate structure 55 to each other.

The lowermost substrate 52 of the semiconductor module 51
A wiring pattern 59 having a predetermined pattern is provided on a, and a plurality of external electrodes 6 are formed on the wiring pattern 59.
0 is provided. The external electrodes 60 are formed by bumps, for example, and have a so-called ball grid array structure, as shown in FIG.

FIG. 8 schematically shows the chip / substrate structure 55. As shown in FIG. 8, a wiring pattern 53 having a predetermined pattern on the upper surface and the lower surface of the substrate 52.
Is formed. Wiring pattern 5 on the upper and lower surfaces of the substrate 52
3 are electrically connected to each other by through holes 61.

FIG. 9 is a plan view schematically showing the substrate 52 and the wiring pattern 3. A plurality of wiring patterns 3 are arranged on the substrate 52. One end of the wiring pattern 53 is the substrate 5
It is located at a substantially central portion of 2, and is connected to the bump of the semiconductor chip 54 here.

[0007]

By the way, recently, there is an increasing demand for high-speed operation of the semiconductor module as described above. Noise such as switching noise becomes a problem in realizing high-speed operation. Such noise is generated between the wiring patterns, which causes various semiconductor chips to malfunction and the signal propagation speed to decrease. As a result, the characteristics of the semiconductor chip cannot be fully obtained, and the performance of the semiconductor module as a whole deteriorates.

Conventionally, as a method for avoiding the above problem, a measure for increasing the distance between the wiring patterns 53 has been adopted. Thereby, the influence of noise can be reduced. However, this method alone cannot sufficiently reduce the noise and cannot fully exhibit the characteristics of the semiconductor chip. Further, with the sophistication of semiconductor chips and the miniaturization of semiconductor modules, it is not possible to secure a sufficient space between the wiring patterns 53, and this method alone limits the noise reduction measures.

Further, in the case of the semiconductor module having a laminated structure, the influence of noise generated by the wiring patterns 53 vertically adjacent between the respective chip / substrate structures 55 becomes large, and the performance of the semiconductor module deteriorates.

Further, a semiconductor chip operating at a high speed has a large amount of heat generation, and it is necessary to radiate heat accurately. In particular, in the case of a structure in which the semiconductor chip is completely shielded from the outside by sealing like the semiconductor module described above,
Development of effective heat dissipation method is desired.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor module capable of reducing the noise generated between wiring patterns and obtaining a heat dissipation effect. It is the one we are trying to provide.

[0012]

In order to solve the above problems, a semiconductor module of the present invention is a semiconductor module in which a plurality of substrate structures having semiconductor chips arranged on a substrate are laminated, Flexible upper substrate, an insulating lower substrate disposed below the upper substrate, and a plurality of signal wirings respectively disposed on the upper and lower substrates,
First common potential wirings respectively disposed on the upper and lower substrates so as to surround each of the signal wirings at intervals, and respectively disposed on the upper and lower substrates,
A semiconductor chip having an electrode pad electrically connected to the signal wiring and the first common potential wiring, and a semiconductor chip disposed below the lower substrate and on a surface opposite to the lower substrate. A supporting substrate having an established wiring pattern;
A first connection conductive layer disposed between the upper substrate and the lower substrate and electrically connecting the signal wirings on the upper and lower substrates to each other; and the upper substrate and the lower substrate. A second connection conductive layer which is disposed between the first and second substrates and electrically connects the first common potential wirings on the upper and lower substrates to each other, and the second connection conductive layer which penetrates through the support substrate. It is characterized by comprising: a first and a second connection conductive layer; a third connection conductive layer for electrically connecting the wiring pattern; and an external connection terminal arranged on the wiring pattern.

Further, the embodiments of the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when the invention is extracted by omitting some of the constituent elements shown in the embodiment, when omitting the extracted invention, the omitted part is appropriately supplemented by a well-known conventional technique. It is something that will be done.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description, constituent elements having substantially the same functions and configurations are designated by the same reference numerals, and redundant description will be given only when necessary.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a cross-sectional view schematically showing the semiconductor module according to the embodiment of FIG. As shown in FIG. 1, the semiconductor module 1 is
It has a structure in which a plurality of chip / substrate structures 5 each provided with a wiring pattern 3 and a semiconductor chip 4 are stacked on a substrate 2. The detailed structure of the chip / substrate structure 5 will be described later. An interlayer substrate 6 having an opening corresponding to a position where the semiconductor chip 4 is provided in a plane is provided between each chip / substrate structure 5, and the interlayer substrate 6 is provided with a plurality of connection conductive layers 7. With this connection conductive layer 7,
The wiring patterns 3 of each chip / substrate structure 5 are electrically connected to each other. Of the connection conductive layers 7, the connection conductive layer 7a
Is for signal wiring, for example, and the connection conductive layer 7b is used for common potential wiring, for example. The common potential wiring can be used as, for example, a ground or a power supply line. The opening of the interlayer substrate 6 is sealed with resin 8, for example.

When forming the above-mentioned semiconductor module, for example, a hot pressing method which is a lamination technique of glass epoxy substrates is used. That is, after the respective chips / substrate structures 5 and the interlayer substrate 6 are aligned with each other, they are subjected to hot pressing to collectively form a laminated structure. A wiring pattern 9 having a predetermined pattern is provided on the lowermost substrate 2a of the semiconductor module 1, and a plurality of external electrodes (external connection terminals) 10 are provided on the wiring pattern 9. The external electrode 10 is formed of, for example, a bump and has a ball grid array structure. Reference numeral 11 is a solder resist that covers the wiring pattern 9.

FIG. 2 schematically shows a chip / substrate structure 5. As shown in FIG. 2, the wiring pattern 3 having a predetermined pattern is formed on the upper surface and the lower surface of the substrate 2. The wiring patterns 3 on the upper surface and the lower surface of the substrate 2 are electrically connected to each other through the through holes 21. The through hole 21a of the through hole 21 is for signal wiring, for example, and is connected to the connection conductive layer 7a of FIG. The through hole 21b is for common potential wiring, for example, and is connected to the connection conductive layer 7b of FIG. A semiconductor chip 4 is provided on the lower surface of the substrate 2. Semiconductor chip 4
Is bonded to the substrate 2 by thermocompression bonding using, for example, the adhesive film 22. The substrate 2 and the semiconductor chip 4 may be bonded to each other by using a liquid adhesive, for example. The semiconductor chip 4 has a plurality of internal bumps (electrode pads) 23, and is electrically connected to the wiring pattern 3 via the internal bumps 23.

FIG. 3 shows the substrate 2 and the wiring patterns 3a, 3
It is a top view which shows b roughly. A wiring pattern 3 made of, for example, copper is provided on the substrate 2. The wiring pattern 3 is composed of, for example, a plurality of wiring patterns 3a as signal wirings and a wiring pattern 3b as a common potential wiring. One end 3a-1 of the wiring pattern 3a is
It is located in the approximate center of the substrate 2 and is connected to the internal bumps 23 of the semiconductor chip 4 here. The other end of the wiring pattern 3 reaches the through hole 21a.

A planar wiring pattern 3b is provided on substantially the entire surface of the substrate 2 except the portions where the wiring pattern 3a and the through holes 21a are provided. This wiring pattern 3b
Reduces the noise generated between the wiring patterns 3a and has a heat dissipation effect. Copper, for example, is used as the wiring pattern 3b. 21b is a wiring pattern 3
It is a through hole for b. The wiring pattern 3b has a connecting portion 3b-1 and is connected to the connecting portion 3b-1 and the internal bump 23 of the semiconductor chip 4.

The wiring patterns 3a and 3b are formed on the substrate 2
It can be formed by forming copper on the entire upper surface and patterning the copper using a well-known technique. The wiring pattern 3b does not necessarily have to be formed on the entire surface of the substrate 2, and may cover the periphery of each wiring pattern 3a. Further, it may be provided so as to cover the periphery of the wiring pattern 3a and fill the area between the wiring patterns 3a. This can eliminate the influence of noise between the adjacent wiring patterns 3a. Further, by setting the intervals between the wiring patterns 3a and 3b to be similar values in all the wiring patterns 3a, the influence of the electromagnetic field in each wiring pattern 3a can be made the same.

When the wiring pattern 3b is formed, noise between the wiring patterns 3a can be reduced by satisfying the above-mentioned minimum condition, but it is desirable that the wiring pattern 3b be formed large regardless of this. This is for the following reason. That is, a larger heat dissipation effect can be obtained by increasing the area of the wiring pattern 3b. Further, in general, when there is a step on the surface of the substrate 2, air bubbles are entrained when the semiconductor chip 4 and the substrate 2 are thermocompression bonded, and therefore good adhesion cannot be obtained. Therefore, the wiring pattern 3 is formed on the entire surface of the substrate 2 as much as possible.
By forming b, it is possible to prevent the formation of a step and reduce the generation of bubbles.

According to the first embodiment, a wiring pattern 3a and a planar wiring pattern 3b are provided on the substrate 2 in a region other than the wiring pattern 3a, and a semiconductor chip 4 is formed on the substrate 2. A plurality of substrate structures 5 are stacked. Each chip / substrate structure 5 is connected by a through hole 21 provided in the substrate 2 and a connection conductive layer 7 provided between the chip / substrate structures 5. Since the wiring pattern 3b is provided so as to cover the wiring pattern 3a and is used as a common potential line such as ground, the wiring patterns 3a are mutually sealed. Therefore, noise between the wiring patterns 3a can be reduced, malfunction of each semiconductor chip 5 and delay of signal propagation speed can be prevented, and the characteristics of the semiconductor chip 5 can be sufficiently obtained.

Further, by making the wiring pattern 3b planar, the heat generated from the semiconductor chip 4 can be effectively dissipated. In the case of a semiconductor module in which a plurality of semiconductor chips are laminated, this heat dissipation effect is particularly effective. Furthermore, since a step difference caused by a slight difference in thickness between the wiring patterns 3a can be reduced, air bubbles are reduced when the substrate 2 and the semiconductor chip 4 are thermocompression bonded, and the substrate 2 and the semiconductor chip 4 are reduced.
And can be laminated more closely.

(Second Embodiment) The second embodiment has almost the same structure as the first embodiment. The difference is that the planar wiring pattern 3b is provided on the entire surface of the substrate 2 even on the surface where the wiring pattern 3a is not formed.

FIG. 4 is a sectional view schematically showing a semiconductor module according to the second embodiment of the present invention. As shown in FIG. 4, a planar wiring pattern 31 is provided on the surface of the substrate 2 where the wiring pattern 3a is not formed (the upper surface of the substrate 2 in FIG. 4). The wiring pattern 31 can be uniformly provided on the entire upper surface, for example. The wiring pattern 31 provided on the upper surface of the substrate is used as a ground or a common potential, for example, and is electrically connected to the wiring pattern 3b through the through hole 7b. The other structure is similar to that of the first embodiment, and thus the description thereof is omitted.

According to the second embodiment, in addition to the structure of the first embodiment, a planar wiring pattern 31 is also provided on the back surface. As a result, the same effect as that of the first embodiment can be obtained.

Further, by providing the wiring pattern 31 on the upper surface, another chip / substrate structure 5 adjacent vertically is formed.
Noise generated between the upper wiring patterns 3a can be almost completely removed. As a result, malfunction of the semiconductor module as a whole and delay of signal propagation speed can be prevented more effectively.

(Third Embodiment) The pitch between wiring patterns has been reduced with the miniaturization of semiconductor modules, the higher speed and higher functionality of semiconductor chips. For this reason, as shown in the first and second embodiments, it may be technically difficult to form the ground wiring in the region excluding the wiring pattern 3. Therefore, in the third embodiment, a substrate structure in which only a planar wiring pattern is provided on the substrate is provided between the chip / substrate structure 1.

FIG. 5 is a sectional view schematically showing a semiconductor module according to the third embodiment of the present invention. As shown in FIG. 5, a wiring pattern / substrate structure 41 is provided between the conventional chip / substrate structures 34. The wiring pattern / substrate structure 41 has, for example, a planar wiring pattern 31 provided on the entire surface of one surface or both surfaces of the substrate 1. This wiring pattern 31 is formed of the other wiring pattern 3 by the through hole 21b and the connection conductive layer 7b.
It is connected to b and has the same potential. Other structures are the same as those of the conventional semiconductor module and the first and second embodiments, and thus the description thereof will be omitted.

According to the third embodiment, the wiring pattern / substrate structure 41 in which the planar wiring pattern 31 is provided on substantially the entire surface of the substrate 2 is the conventional chip / substrate structure 34.
It is provided between each other. Accordingly, even in the case where it is difficult to configure the chip / substrate structure 1 as shown in the first and second embodiments, it is possible to prevent noise from occurring between the wiring patterns 3.

Further, by providing the wiring pattern / substrate structure 41, a greater heat radiation effect can be obtained as compared with the conventional semiconductor module.

Further, in the wiring pattern / substrate structure 41, by providing the wiring patterns 31 on both surfaces of the substrate 2, higher noise reduction effect and heat dissipation effect can be obtained as compared with the case where they are provided on one surface. To be

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modifications and modifications, and those modifications and modifications are also within the scope of the present invention. Understood.

[0034]

As described above in detail, according to the present invention,
Noise generated between wiring patterns can be reduced,
It is possible to provide a semiconductor module capable of obtaining a heat dissipation effect.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor module according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a chip / substrate structure of the semiconductor module shown in FIG.

3 is a plan view schematically showing a substrate and a wiring pattern of the semiconductor module shown in FIG.

FIG. 4 is a sectional view schematically showing a semiconductor module according to a second embodiment of the present invention.

FIG. 5 is a sectional view schematically showing a semiconductor module according to a third embodiment of the present invention.

FIG. 6 is a sectional view schematically showing a conventional semiconductor module.

FIG. 7 is a diagram showing an arrangement of external connection terminals.

FIG. 8 is a diagram schematically showing a conventional chip / substrate structure.

FIG. 9 is a plan view schematically showing a conventional substrate and wiring pattern.

[Explanation of symbols]

1 ... Semiconductor module, 2 ... substrate, 3 ... Wiring pattern, 4 ... Semiconductor chip, 5 ... Chip / substrate structure, 6 ... Interlayer substrate, 7 ... Connection conductive layer, 8 ... Resin, 9 ... Wiring pattern, 10 ... External connection terminal.

Claims (9)

[Claims] 1. A semiconductor module in which a plurality of substrate structures, each having a semiconductor chip disposed on a substrate, are stacked, the upper module having an insulating property, and the insulating feature disposed below the upper substrate. A lower substrate, a plurality of signal wirings respectively arranged on the upper and lower substrates, and a plurality of signal wirings respectively arranged on the upper and lower substrates so as to surround each of the signal wirings at intervals. A first common potential wiring; a semiconductor chip having electrode pads respectively disposed on the upper and lower substrates and electrically connected to the signal wiring and the first common potential wiring; A support substrate disposed below the substrate and having a wiring pattern disposed on a surface opposite to the lower substrate, and disposed between the upper substrate and the lower substrate, and The signal wiring on the upper and lower substrates And a first connection conductive layer electrically connecting the first common potential wiring on the upper and lower substrates and electrically connected to each other. A second connection conductive layer that is connected to the second connection conductive layer, a third connection conductive layer that is disposed so as to penetrate the support substrate, and that electrically connects the first and second connection conductive layers and the wiring pattern, An external connection terminal disposed on the wiring pattern, and a semiconductor module. 2. The signal wiring and the first common potential wiring are on a first surface of the upper substrate facing the lower substrate and on a second surface of the lower substrate opposite to the first surface. The semiconductor module according to claim 1, wherein the semiconductor module is provided in the semiconductor module. 3. An insulating interlayer substrate disposed between the upper substrate and the lower substrate, wherein the first connection conductive layer is formed so as to penetrate the interlayer substrate. The semiconductor module according to claim 1, wherein the semiconductor module is a semiconductor module. 4. The first common potential wiring is arranged so as to surround each of the signal wirings with a space and to fill the space between each of the signal wirings. 1. The semiconductor module according to 1 or 2. 5. The first common potential wirings surround each of the signal wirings at intervals and fill the spaces between the signal wirings, and substantially the entire surfaces of the upper and lower substrates. It is provided on the upper side, and is characterized by the above-mentioned.
Alternatively, the semiconductor module according to item 2. 6. The semiconductor module according to claim 1, wherein the first common potential wiring is a ground line or a power supply line. 7. The entire first common potential wiring is on a third surface of the upper substrate facing the first surface and on a fourth surface of the lower substrate facing the second surface. 6. The semiconductor module according to claim 1, wherein the first common potential wiring is further electrically connected to each other. 8. An intermediate substrate, further comprising: an intermediate substrate, which is disposed between the upper substrate and the lower substrate and has planar second common potential wirings disposed on an upper surface and a lower surface, The semiconductor module according to claim 1, wherein the first and second common potential wirings are electrically connected to each other. 9. The semiconductor module according to claim 8, wherein the second common potential wiring is provided on substantially the entire upper surface and the lower surface.